On Mon, Apr 29, 2019 at 05:08:46PM -0700, Sean Christopherson wrote:
On Mon, Apr 29, 2019 at 03:22:09PM -0700, Linus Torvalds wrote:
On Mon, Apr 29, 2019 at 3:08 PM Sean Christopherson sean.j.christopherson@intel.com wrote:
FWIW, Lakemont (Quark) doesn't block NMI/SMI in the STI shadow, but I'm not sure that counters the "horrible errata" statement ;-). SMI+RSM saves and restores STI blocking in that case, but AFAICT NMI has no such protection and will effectively break the shadow on its IRET.
Ugh. I can't say I care deeply about Quark (ie never seemed to go anywhere), but it's odd. I thought it was based on a Pentium core (or i486+?). Are you saying those didn't do it either?
It's 486 based, but either way I suspect the answer is "yes". IIRC, Knights Corner, a.k.a. Larrabee, also had funkiness around SMM and that was based on P54C, though I'm struggling to recall exactly what the Larrabee weirdness was.
Aha! Found an ancient comment that explicitly states P5 does not block NMI/SMI in the STI shadow, while P6 does block NMI/SMI.