From: Peter Zijlstra
Sent: 07 May 2019 12:31 To: David Laight On Tue, May 07, 2019 at 09:18:51AM +0000, David Laight wrote:
From: Peter Zijlstra
Sent: 07 May 2019 09:58
...
- /*
* When we're here from kernel mode; the (exception) stack looks like:** 4*4(%esp) - <previous context>* 3*4(%esp) - flags* 2*4(%esp) - cs* 1*4(%esp) - ip* 0*4(%esp) - orig_eaxAm I right in thinking that this is the only 'INT3' stack frame that needs to be 'fiddled' with? And that the 'emulate a call instruction' has verified that is the case?? So the %cs is always the kernel %cs.
Only the INT3 thing needs 'the gap', but the far bigger change here is that kernel frames now have a complete pt_regs set and all sorts of horrible crap can go away.
I'm not doubting that generating the 'five register' interrupt stack frame for faults in kernel space makes life simpler just suggesting that the 'emulated call' can be done by emulating the 'iret' rather than generating a gap in the stack.
For 32bit 'the gap' happens naturally when building a 5 entry frame. Yes it is possible to build a 5 entry frame on top of the old 3 entry one, but why bother...
Presumably there is 'horrid' code to generate the gap in 64bit mode? (less horrid than 32bit, but still horrid?) Or does it copy the entire pt_regs into a local stack frame and use that for the iret?
I've just tried to parse the pseudo code for IRET in the intel docs. Does anyone find that readable? I wonder if you can force 32bit mode to do a stack switch 'iret' by doing something like a far jump to a different %cs ?
David
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