On Fri, Sep 19, 2025 at 04:14:49PM +0100, Marc Zyngier wrote:
FGUs are uniform, because when something doesn't exist on a vcpu, it doesn't exist on *any* vcpu. Non-FGU use of FGTs, however, has to be more flexible because that's part of the emulation, and is actually pretty rare that we want to trap something at all times, on all vcpus.
For the same reason, conflating the R and W registers doesn't work either. For the above example, I want to be able to trap write accesses to MDSCR_EL1, and not reads, just like the Ampere brain-damage.
So please make this per-vcpu, decouple R and W FGTs, and convert the Ampere horror to this scheme.
OK, that makes more sense - it was a bit confusing that all the FGT handling was done per VM not per vCPU without even any provision for per-vCPU or distinct R/W stuff, it seemed strange. Since the SME requirement also ends up being per VM anyway I just tried to fit in with what was there but if we don't want that behaviour it's certainly more obvious to make it per-vCPU and to split read and write.