Re: [PATCH v10 05/14] riscv: vector: Use vlenb from DT for thead

Charlie Jenkins charlie@rivosinc.com 於 2024年9月12日 週四 下午1:57寫道：

If thead,vlenb is provided in the device tree, prefer that over reading the vlenb csr.

Signed-off-by: Charlie Jenkins charlie@rivosinc.com Acked-by: Conor Dooley conor.dooley@microchip.com

---

arch/riscv/Kconfig.vendor | 13 +++++++ arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/include/asm/vendor_extensions/thead.h | 6 +++ arch/riscv/kernel/cpufeature.c | 48 ++++++++++++++++++++++++ arch/riscv/kernel/vector.c | 12 +++++- arch/riscv/kernel/vendor_extensions/thead.c | 11 ++++++ 6 files changed, 91 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 9897442bd44f..b096548fe0ff 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -26,6 +26,19 @@ config RISCV_ISA_VENDOR_EXT_THEAD extensions. Without this option enabled, T-Head vendor extensions will not be detected at boot and their presence not reported to userspace.

•     If you don't know what to do here, say Y.
  

+config RISCV_ISA_XTHEADVECTOR

•   bool "xtheadvector extension support"
  

•   depends on RISCV_ISA_VENDOR_EXT_THEAD
  

•   depends on RISCV_ISA_V
  

•   depends on FPU
  

•   default y
  

•   help
  

•     Say N here if you want to disable all xtheadvector related procedures
  

•     in the kernel. This will disable vector for any T-Head board that
  

•     contains xtheadvector rather than the standard vector.
  

•     If you don't know what to do here, say Y.
  

endmenu

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 45f9c1171a48..28bdeb1005e0 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS];

+extern u32 thead_vlenb_of;

void riscv_user_isa_enable(void);

#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \ diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/include/asm/vendor_extensions/thead.h index 48421d1553ad..190c91e37e95 100644 --- a/arch/riscv/include/asm/vendor_extensions/thead.h +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -13,4 +13,10 @@

extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead;

+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD +void disable_xtheadvector(void); +#else +void disable_xtheadvector(void) { } +#endif

#endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 46e69b9d66a7..9340efd79af9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -37,6 +37,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS];

+u32 thead_vlenb_of;

/**

• riscv_isa_extension_base() - Get base extension word

@@ -772,6 +774,46 @@ static void __init riscv_fill_vendor_ext_list(int cpu) } }

+static int has_thead_homogeneous_vlenb(void) +{

•   int cpu;
  

•   u32 prev_vlenb = 0;
  

•   u32 vlenb;
  

•   /* Ignore thead,vlenb property if xtheavector is not enabled in the kernel */
  

•   if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR))
  

•           return 0;
  

•   for_each_possible_cpu(cpu) {
  

•           struct device_node *cpu_node;
  

•           cpu_node = of_cpu_device_node_get(cpu);
  

•           if (!cpu_node) {
  

•                   pr_warn("Unable to find cpu node\n");
  

•                   return -ENOENT;
  

•           }
  

•           if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) {
  

•                   of_node_put(cpu_node);
  

•                   if (prev_vlenb)
  

•                           return -ENOENT;
  

•                   continue;
  

•           }
  

•           if (prev_vlenb && vlenb != prev_vlenb) {
  

•                   of_node_put(cpu_node);
  

•                   return -ENOENT;
  

•           }
  

•           prev_vlenb = vlenb;
  

•           of_node_put(cpu_node);
  

•   }
  

•   thead_vlenb_of = vlenb;
  

•   return 0;
  

+}

static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) { unsigned int cpu; @@ -825,6 +867,12 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) riscv_fill_vendor_ext_list(cpu); }

•   if (riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTOR) &&
  

•       has_thead_homogeneous_vlenb() < 0) {
  

•           pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n");
  

•           disable_xtheadvector();
  

•   }
  

•   if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
            return -ENOENT;
  
  

diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 682b3feee451..9775d6a9c8ee 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) { unsigned long this_vsize;

•   /* There are 32 vector registers with vlenb length. */
  

•   /*
  

•    * There are 32 vector registers with vlenb length.
  

•    *
  

•    * If the thead,vlenb property was provided by the firmware, use that
  

•    * instead of probing the CSRs.
  

•    */
  

•   if (thead_vlenb_of) {
  

•           this_vsize = thead_vlenb_of * 32;
  

•           return 0;
  

•   }
  

•   riscv_v_enable();
    this_vsize = csr_read(CSR_VLENB) * 32;
    riscv_v_disable();
  

diff --git a/arch/riscv/kernel/vendor_extensions/thead.c b/arch/riscv/kernel/vendor_extensions/thead.c index 0f27baf8d245..519dbf70710a 100644 --- a/arch/riscv/kernel/vendor_extensions/thead.c +++ b/arch/riscv/kernel/vendor_extensions/thead.c @@ -5,6 +5,7 @@ #include <asm/vendor_extensions/thead.h>

#include <linux/array_size.h> +#include <linux/cpumask.h> #include <linux/types.h>

/* All T-Head vendor extensions supported in Linux */ @@ -16,3 +17,13 @@ struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead = { .ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_thead), .ext_data = riscv_isa_vendor_ext_thead, };

+void disable_xtheadvector(void) +{

•   int cpu;
  

•   for_each_possible_cpu(cpu)
  

•           clear_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu].isa);
  

•   clear_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap.isa);
  

+}

Given that we already have an infra to resolve and validate isa, with riscv_resolve_isa(), shouldn't we reuse that part of the code and assign "has_thead_homogeneous_vlenb()" as a validate function? I know it would need some modifications because it seems like riscv_resolve_isa is not there for vendor extensions yet.

Sorry I am late on reviewing this series. I think we can refactor it as follow up patches if we want to keep up development.

Thanks, Andy