Add hcontext/scontext CSRs definition to csr.h
As riscv-state-enable [1] Smstateen extension spec: Sdtrig CSRs: hcontext/scontext availability are controlled by bit 57 of Smstateen CSRs.
Link: https://github.com/riscvarchive/riscv-state-enable/releases/download/v1.0.0/... [1] Signed-off-by: Max Hsu max.hsu@sifive.com --- arch/riscv/include/asm/csr.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..308ae795dc82 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -204,6 +204,8 @@ #define ENVCFG_FIOM _AC(0x1, UL)
/* Smstateen bits */ +#define SMSTATEEN0_HSCONTEXT_SHIFT 57 +#define SMSTATEEN0_HSCONTEXT (_ULL(1) << SMSTATEEN0_HSCONTEXT_SHIFT) #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) #define SMSTATEEN0_AIA_SHIFT 59 @@ -480,6 +482,10 @@ #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
+/* riscv-debug-spec: Sdtrig extension */ +#define CSR_SCONTEXT 0x5a8 +#define CSR_HCONTEXT 0x6a8 + #ifndef __ASSEMBLY__
#define csr_swap(csr, val) \