Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string

On Mon, Oct 2, 2023 at 11:57 AM Christoph Hellwig hch@infradead.org wrote:

On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote:

...

The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension.

Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI.

Umm, I though Linux/riscv would never support vendor specific extensions?

We already have few T-Head specific extensions so Linux RISC-V does allow vendor extensions.

Regards, Anup