On Tue, 23 Dec 2025 at 01:22, Mark Brown broonie@kernel.org wrote:
SME is configured by the system registers SMCR_EL1 and SMCR_EL2, add definitions and userspace access for them. These control the SME vector length in a manner similar to that for SVE and also have feature enable bits for SME2 and FA64. A subsequent patch will add management of them for guests as part of the general floating point context switch, as is done for the equivalent SVE registers.
Signed-off-by: Mark Brown broonie@kernel.org
arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/asm/vncr_mapping.h | 1 + arch/arm64/kvm/sys_regs.c | 36 ++++++++++++++++++++++++++++++++++- 3 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index b41700df3ce9..f24441244a68 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -504,6 +504,7 @@ enum vcpu_sysreg { CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ HACR_EL2, /* Hypervisor Auxiliary Control Register */ ZCR_EL2, /* SVE Control Register (EL2) */
SMCR_EL2, /* SME Control Register (EL2) */ TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */@@ -542,6 +543,7 @@ enum vcpu_sysreg { VNCR(ACTLR_EL1),/* Auxiliary Control Register */ VNCR(CPACR_EL1),/* Coprocessor Access Control */ VNCR(ZCR_EL1), /* SVE Control */
VNCR(SMCR_EL1), /* SME Control */ VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ VNCR(TCR_EL1), /* Translation Control Register */diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h index c2485a862e69..44b12565321b 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -44,6 +44,7 @@ #define VNCR_HDFGWTR_EL2 0x1D8 #define VNCR_ZCR_EL1 0x1E0 #define VNCR_HAFGRTR_EL2 0x1E8 +#define VNCR_SMCR_EL1 0x1F0 #define VNCR_TTBR0_EL1 0x200 #define VNCR_TTBR1_EL1 0x210 #define VNCR_FAR_EL1 0x220 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3576e69468db..5c912139d264 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2827,6 +2827,37 @@ static bool access_gic_elrsr(struct kvm_vcpu *vcpu, return true; }
+static unsigned int sme_el2_visibility(const struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)+{
return __el2_visibility(vcpu, rd, sme_visibility);+}
+static bool access_smcr_el2(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,const struct sys_reg_desc *r)+{
unsigned int vq;u64 smcr;if (guest_hyp_sve_traps_enabled(vcpu)) {
Should this be guest_hyp_sme_traps_enabled() ?
kvm_inject_nested_sve_trap(vcpu);
And by the same token, should this be kvm_inject_nested_sme_trap()? That function doesn't exist, but would inject ESR_ELx_EC_SME instead of ESR_ELx_EC_SVE.
return false;}if (!p->is_write) {p->regval = __vcpu_sys_reg(vcpu, SMCR_EL2);return true;}smcr = p->regval;vq = SYS_FIELD_GET(SMCR_ELx, LEN, smcr) + 1;vq = min(vq, vcpu_sme_max_vq(vcpu));__vcpu_assign_sys_reg(vcpu, SMCR_EL2, SYS_FIELD_PREP(SMCR_ELx, LEN,vq - 1));
I think this might be wrong. This code only writes the LEN, discarding other fields in SMCR_EL2. The analogous SVE code in access_zcr_el2() is only concerned with the length, and doesn't need to worry about other bits to preserve.
Should this be something along the lines of the below instead?
+ smcr = p->regval; + vq = SYS_FIELD_GET(SMCR_ELx, LEN, smcr) + 1; + vq = min(vq, vcpu_sme_max_vq(vcpu)); + smcr &= ~SMCR_ELx_LEN_MASK; + smcr |= SYS_FIELD_PREP(SMCR_ELx, LEN, vq - 1); + __vcpu_assign_sys_reg(vcpu, SMCR_EL2, smcr);
Cheers, /fuad
return true;+}
static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -3291,7 +3322,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, { SYS_DESC(SYS_TRFCR_EL1), undef_access }, { SYS_DESC(SYS_SMPRI_EL1), undef_access },
{ SYS_DESC(SYS_SMCR_EL1), undef_access },
{ SYS_DESC(SYS_SMCR_EL1), NULL, reset_val, SMCR_EL1, 0, .visibility = sme_visibility }, { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },@@ -3655,6 +3686,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
EL2_REG_FILTERED(SMCR_EL2, access_smcr_el2, reset_val, 0,sme_el2_visibility),EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),-- 2.47.3