On Mon, Nov 20, 2023 at 08:26:31AM +0000, Tian, Kevin wrote:
From: Liu, Yi L yi.l.liu@intel.com Sent: Friday, November 17, 2023 9:18 PM
This adds the data structure for flushing iotlb for the nested domain allocated with IOMMU_HWPT_DATA_VTD_S1 type.
This only supports invalidating IOTLB, but no for device-TLB as device-TLB invalidation will be covered automatically in the IOTLB invalidation if the underlying IOMMU driver has enabled ATS for the affected device.
"no for device-TLB" is misleading. Here just say that cache invalidation request applies to both IOTLB and device TLB (if ATS is enabled ...)
I think we should forward the ATS invalidation from the guest too? That is what ARM and AMD will have to do, can we keep them all consistent?
I understand Intel keeps track of enough stuff to know what the RIDs are, but is it necessary to make it different?
Jason