Hi Palmer,
On Thu, Oct 5, 2023 at 11:35 AM Anup Patel anup@brainfault.org wrote:
On Tue, Oct 3, 2023 at 9:22 AM Anup Patel apatel@ventanamicro.com wrote:
This series extends KVM RISC-V to allow Guest/VM discover and use conditional operations related ISA extensions (namely XVentanaCondOps and Zicond).
To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1 branch at: https://github.com/avpatel/kvmtool.git
These patches are based upon the latest riscv_kvm_queue and can also be found in the riscv_kvm_condops_v3 branch at: https://github.com/avpatel/linux.git
Changes since v2:
- Dropped patch1, patch2, and patch5 since these patches don't meet the requirements of patch acceptance policy.
Changes since v1:
- Rebased the series on riscv_kvm_queue
- Split PATCH1 and PATCH2 of v1 series into two patches
- Added separate test configs for XVentanaCondOps and Zicond in PATCH7 of v1 series.
Anup Patel (6): dt-bindings: riscv: Add Zicond extension entry RISC-V: Detect Zicond from ISA string RISC-V: KVM: Allow Zicond extension for Guest/VM KVM: riscv: selftests: Add senvcfg register to get-reg-list test KVM: riscv: selftests: Add smstateen registers to get-reg-list test KVM: riscv: selftests: Add condops extensions to get-reg-list test
Queued this series for Linux-6.7
I have created shared tag kvm-riscv-shared-tag-6.7 in the KVM RISC-V repo at: https://github.com/kvm-riscv/linux.git
This shared tag is based on 6.6-rc5 and contains following 4 patches: dt-bindings: riscv: Add Zicond extension entry RISC-V: Detect Zicond from ISA string dt-bindings: riscv: Add smstateen entry RISC-V: Detect Smstateen extension
Thanks, Anup
Thanks, Anup
.../devicetree/bindings/riscv/extensions.yaml | 6 +++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 + .../selftests/kvm/riscv/get-reg-list.c | 54 +++++++++++++++++++ 6 files changed, 65 insertions(+)
-- 2.34.1