From: Liu, Yi L yi.l.liu@intel.com Sent: Friday, November 17, 2023 9:18 PM
This adds the data structure for flushing iotlb for the nested domain allocated with IOMMU_HWPT_DATA_VTD_S1 type.
This only supports invalidating IOTLB, but no for device-TLB as device-TLB invalidation will be covered automatically in the IOTLB invalidation if the underlying IOMMU driver has enabled ATS for the affected device.
"no for device-TLB" is misleading. Here just say that cache invalidation request applies to both IOTLB and device TLB (if ATS is enabled ...)
+/**
- enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
stage-1 cache invalidation
- @IOMMU_VTD_INV_FLAGS_LEAF: The LEAF flag indicates whether only
the
leaf PTE caching needs to be invalidated
and other paging structure caches can be
preserved.
remove the words after 'and'
+/**
- struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
(IOMMU_HWPT_DATA_VTD_S1)
- @addr: The start address of the addresses to be invalidated. It needs
to be 4KB aligned.
remove "of the addresses"
- @npages: Number of contiguous 4K pages to be invalidated.
- @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
- @__reserved: Must be 0
- The Intel VT-d specific invalidation data for user-managed stage-1 cache
- invalidation in nested translation. Userspace uses this structure to
- tell the impacted cache scope after modifying the stage-1 page table.
- Invalidating all the caches related to the page table by setting @addr
- to be 0 and @npages to be __aligned_u64(-1). This includes the
- corresponding device-TLB if ATS is enabled on the attached devices.
put words about device-TLB to last paragraph. Putting it here is confusing as if it only applies to invalidate-all.