Allow userspace to change the guest-visible value of the register with some severe limitation:
- No changes to features not virtualized by KVM (MPAM_frac, RAS_frac, SME, RNDP_trap).
- No changes to features (CSV2_frac, NMI, MTE_frac, GCS, THE, MTEX, DF2, PFAR) which haven't been added into the ftr_id_aa64pfr1[]. Because the struct arm64_ftr_bits definition for each feature in the ftr_id_aa64pfr1[] is used by arm64_check_features. If they're not existing in the ftr_id_aa64pfr1[], the for loop won't check the if the new_val is safe for those features.
For the question why can't those fields be hidden depending on the VM configuration? I don't find there is the related VM configuration, maybe we should add the new VM configuration?
I'm not sure I'm right, so if there're any problems please help to point out and I will fix them.
Also add the selftest for it.
Changelog: ---------- v2 -> v3: * Give more description about why only part of the fields can be writable. * Updated the writable mask by referring the latest ARM spec.
v1 -> v2: * Tackling the full register instead of single field. * Changing the patch title and commit message.
RFCv1 -> v1: * Fix the compilation error. * Delete the machine specific information and make the description more generable.
RFCv1: https://lore.kernel.org/all/20240612023553.127813-1-shahuang@redhat.com/ v1: https://lore.kernel.org/all/20240617075131.1006173-1-shahuang@redhat.com/ v2: https://lore.kernel.org/all/20240618063808.1040085-1-shahuang@redhat.com/
Shaoqin Huang (2): KVM: arm64: Allow userspace to change ID_AA64PFR1_EL1 KVM: selftests: aarch64: Add writable test for ID_AA64PFR1_EL1
arch/arm64/kvm/sys_regs.c | 4 +++- tools/testing/selftests/kvm/aarch64/set_id_regs.c | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-)
Add writable test for the ID_AA64PFR1_EL1 register.
Signed-off-by: Shaoqin Huang shahuang@redhat.com --- tools/testing/selftests/kvm/aarch64/set_id_regs.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c index a7de39fa2a0a..7fd4d6f26456 100644 --- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -133,6 +133,13 @@ static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = { REG_FTR_END, };
+static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = { + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, MTE, ID_AA64PFR1_EL1_MTE_NI), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0), + REG_FTR_END, +}; + static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = { REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0), @@ -199,6 +206,7 @@ static struct test_feature_reg test_regs[] = { TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), + TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1), TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
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