Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

4 participants
11017 discussions

[toolchain/ci/interesting-commits] branch linaro-local/ci/tcwg_kernel updated (ca10ccf -> 11bbd39)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel in repository toolchain/ci/interesting-commits. from ca10ccf Add regression 4e3d3e40726e1b68bf52fa205c68495124ea60b8 from [...] new 11bbd39 Add regression 4e3d3e40726e1b68bf52fa205c68495124ea60b8 from [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[binutils-gdb] branch master updated (6b8c53f2f1c -> cada5fc921e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 6b8c53f2f1c gdb/testsuite/fortran: Add mixed language stack test new cada5fc921e gdb: Handle W and X remote packets without giving a warning The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 5 + gdb/remote.c | 46 ++++- gdb/testsuite/ChangeLog | 5 + gdb/testsuite/gdb.server/exit-multiple-threads.c | 202 +++++++++++++++++++++ gdb/testsuite/gdb.server/exit-multiple-threads.exp | 136 ++++++++++++++ 5 files changed, 384 insertions(+), 10 deletions(-) create mode 100644 gdb/testsuite/gdb.server/exit-multiple-threads.c create mode 100644 gdb/testsuite/gdb.server/exit-multiple-threads.exp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-check_binutils updated (a632ece2e -> 491700083)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-check_binutils in repository toolchain/ci/base-artifacts. discards a632ece2e 3: update: binutils-b9414a8064c4e10c469ef5e0aebbf46c9fbdcf80: 1 new 491700083 3: update: binutils-b9414a8064c4e10c469ef5e0aebbf46c9fbdcf80: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a632ece2e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-release-aarch64- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 410 +- 03-build_abe-check_binutils/console.log | 11515 +++++---- 04-build_abe-check_binutils-check/console.log | 16439 +++++++------ 05-check_regression/console.log | 382 +- 06-update_baseline/console.log | 1451 +- console.log | 30363 ++++++++++++------------ jenkins/manifest.sh | 6 +- regressions.txt | 2 +- sumfiles/binutils.sum | 2 +- sumfiles/gas.sum | 2 +- sumfiles/ld.sum | 2 +- 12 files changed, 30359 insertions(+), 30381 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[gcc] branch master updated (bb83e069eba -> 02f7334ac93)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] new 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/cp/ChangeLog | 8 +++ gcc/cp/cp-gimplify.c | 17 +++-- gcc/cp/parser.c | 2 + libgomp/ChangeLog | 5 ++ libgomp/testsuite/libgomp.c++/pr93931.C | 120 ++++++++++++++++++++++++++++++++ 5 files changed, 146 insertions(+), 6 deletions(-) create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig updated (ac309e7744be -> 5076190daded)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from ac309e7744be Merge branch 'for-linus' of git://git.kernel.org/pub/scm/l [...] adds fd4d9c7d0c71 mm: slub: add missing TID bump in kmem_cache_alloc_bulk() adds 5076190daded mm: slub: be more careful about the double cmpxchg of freelist No new revisions were added by this update. Summary of changes: mm/slub.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig updated (52c365aa9ca -> 35627038123)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project. from 52c365aa9ca Revert "[Concepts] Fix incorrect DeclContext for transforme [...] adds cfa792458fc [Transforms] add phase ordering tests for min/max/abs; NFC adds 623461b2ce4 [EarlyCSE] avoid crashing when detecting min/max/abs patter [...] adds 5401d393f88 ../llvm/utils/update_test_checks.py --opt-binary bin/opt .. [...] adds a36a14b70f1 [Concepts] Fix incorrect DeclContext for transformed Requir [...] adds 35627038123 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Sema/Sema.h | 6 +- clang/lib/Parse/ParseDecl.cpp | 6 ++ clang/lib/Parse/ParseTemplate.cpp | 3 +- clang/lib/Sema/SemaTemplate.cpp | 13 ++- clang/lib/Sema/TreeTransform.h | 2 +- clang/test/SemaCXX/invalid-member-expr.cpp | 1 + clang/test/SemaCXX/typo-correction.cpp | 5 +- .../SemaTemplate/instantiate-requires-expr.cpp | 13 +++ .../ms-lookup-template-base-classes.cpp | 1 + llvm/lib/Transforms/Scalar/EarlyCSE.cpp | 51 +++++++-- llvm/test/Transforms/EarlyCSE/commute.ll | 85 +++++++++++++-- .../Transforms/PhaseOrdering/min-max-abs-cse.ll | 114 +++++++++++++++++++++ 12 files changed, 276 insertions(+), 24 deletions(-) create mode 100644 llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig updated (a9a60fe3a -> eea1ba3c1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards a9a60fe3a 0: update: llvm-linux: all new eea1ba3c1 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a9a60fe3a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-build_llvm/console.log | 12598 +++++++++++++++-------------- 03-build_linux/console.log | 3878 +++++---- 04-boot_linux/console.log | 6 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 16616 +++++++++++++++++++------------------- jenkins/manifest.sh | 14 +- 8 files changed, 16611 insertions(+), 16635 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig updated (4e3d3e40726 -> b5562f1187d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig in repository toolchain/ci/gcc. from 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] adds 529ea7d9596 Complete change to resolve pr90275. adds 07fe4af4d51 rs6000: Add back some w* constraints (PR91886) adds b3341826531 libstdc++: Fix is_trivially_constructible (PR 94033) adds b5562f1187d Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 3375 ++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 55 + gcc/analyzer/diagnostic-manager.cc | 2 +- gcc/analyzer/engine.cc | 13 +- gcc/analyzer/exploded-graph.h | 7 +- gcc/analyzer/region-model.cc | 265 +- gcc/analyzer/region-model.h | 90 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/asan.c | 2 +- gcc/cgraphunit.c | 13 +- gcc/config/aarch64/aarch64.c | 48 +- gcc/config/aarch64/aarch64.md | 22 +- gcc/config/arc/arc.c | 2 +- gcc/config/arm/arm-builtins.c | 188 + gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.c | 25 + gcc/config/arm/arm_mve.h | 16961 ++++++++++++++++--- gcc/config/arm/arm_mve_builtins.def | 506 + gcc/config/arm/constraints.md | 16 +- gcc/config/arm/mve.md | 6415 ++++++- gcc/config/arm/predicates.md | 16 + gcc/config/gcn/gcn-valu.md | 31 +- gcc/config/gcn/gcn.h | 4 + gcc/config/rs6000/constraints.md | 11 + gcc/cp/ChangeLog | 15 + gcc/cp/constraint.cc | 6 +- gcc/cp/coroutines.cc | 4 +- gcc/cp/logic.cc | 8 +- gcc/cp/parser.c | 20 +- gcc/cp/pt.c | 2 +- gcc/cp/tree.c | 20 +- gcc/cse.c | 1 - gcc/d/ChangeLog | 6 + gcc/d/d-target.cc | 2 +- gcc/d/expr.cc | 2 +- gcc/fortran/ChangeLog | 6 + gcc/fortran/class.c | 2 +- gcc/fortran/trans-types.c | 2 +- gcc/gimple-fold.c | 6 + gcc/gimple-loop-versioning.cc | 2 +- gcc/ipa-predicate.c | 2 +- gcc/optinfo-emit-json.cc | 2 +- gcc/testsuite/ChangeLog | 1369 +- .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 +- gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 + gcc/testsuite/g++.dg/abi/mangle74.C | 30 + .../g++.dg/goacc/firstprivate-mappings-1.C | 12 +- gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 + gcc/testsuite/gcc.dg/attr-weakref-5.c | 31 + gcc/testsuite/gcc.dg/torture/pr94206.c | 17 + gcc/testsuite/gcc.target/aarch64/pr94201.c | 13 + .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +- 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.../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 23 + .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 22 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 22 + .../vldrdq_gather_shifted_offset_z_s64.c | 22 + .../vldrdq_gather_shifted_offset_z_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 14 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 22 + .../vldrhq_gather_shifted_offset_z_f16.c | 22 + .../vldrhq_gather_shifted_offset_z_s16.c | 22 + .../vldrhq_gather_shifted_offset_z_s32.c | 22 + .../vldrhq_gather_shifted_offset_z_u16.c | 22 + .../vldrhq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 22 + .../vldrwq_gather_shifted_offset_z_f32.c | 22 + .../vldrwq_gather_shifted_offset_z_s32.c | 22 + .../vldrwq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 23 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 23 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 23 + 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.../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 24 + 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+ .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 22 + .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 24 + 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+ .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 23 + 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+ .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 23 + 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+ .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 22 + 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c create mode 100644 libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig updated (4e9c15214 -> fe6a5278c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allyesconfig in repository toolchain/ci/base-artifacts. from 4e9c15214 1: reset: gcc-4e3d3e40726e1b68bf52fa205c68495124ea60b8: 18453 new fe6a5278c 2: update: gcc-b5562f1187d47b0e8a20687a8d31d00c187aada9: 18453 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 129 +- 02-prepare_abe/console.log | 418 +- 03-build_abe-binutils/console.log | 10267 +++++----- 04-build_abe-stage1/console.log | 20168 +++++++++--------- 05-build_linux/console.log | 7288 +++---- 07-check_regression/console.log | 68 +- 07-check_regression/trigger-bisect | 3 - 08-update_baseline/console.log | 45 +- console.log | 38383 +++++++++++++++++------------------ jenkins/manifest.sh | 10 +- regressions.txt | 20 +- reset-baseline | 0 12 files changed, 38359 insertions(+), 38440 deletions(-) delete mode 100644 07-check_regression/trigger-bisect delete mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[binutils-gdb] branch master updated (19a2740f7f2 -> 6b8c53f2f1c)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 19a2740f7f2 gdb: Remove C++ symbol aliases from completion list new 6b8c53f2f1c gdb/testsuite/fortran: Add mixed language stack test The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/testsuite/ChangeLog | 7 + .../mixed-lang-stack.c} | 41 +++--- gdb/testsuite/gdb.fortran/mixed-lang-stack.cpp | 85 +++++++++++ gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 163 +++++++++++++++++++++ gdb/testsuite/gdb.fortran/mixed-lang-stack.f90 | 116 +++++++++++++++ 5 files changed, 388 insertions(+), 24 deletions(-) copy gdb/testsuite/{gdb.base/execl-update-breakpoints.c => gdb.fortran/mixed-lang- [...] create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.cpp create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.exp create mode 100644 gdb/testsuite/gdb.fortran/mixed-lang-stack.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

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Tcwg-commits March 2020