---------- Forwarded message ----------
From: Mike Leach <mike.leach(a)linaro.org>
Date: 2 January 2017 at 22:55
Subject: [PATCH] coresight: etm4x: Fix enabling of cycle accurate tracing
in perf.
To: mathieu.poirier(a)linaro.org
Cc: linux-arm-kernel(a)lists.infradead.org, coresignt(a)lists.linaro.org, Mike
Leach <mike.leach(a)linaro.org>
Using perf record 'cyclacc' option in cs_etm event was not setting up cycle
accurate trace correctly.
Corrects bit set in TRCCONFIGR to enable cycle accurate trace.
Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec.
Signed-off-by: Mike Leach <mike.leach(a)linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++--
drivers/hwtracing/coresight/coresight-etm4x.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index 4db8d6a..07be032 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct
etmv4_drvdata *drvdata,
goto out;
/* Go from generic option to ETMv4 specifics */
- if (attr->config & BIT(ETM_OPT_CYCACC))
- config->cfg |= ETMv4_MODE_CYCACC;
+ if (attr->config & BIT(ETM_OPT_CYCACC)) {
+ config->cfg |= BIT(4);
+ /* TRM: Must program this for cycacc to work */
+ config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
+ }
if (attr->config & BIT(ETM_OPT_TS))
config->cfg |= ETMv4_MODE_TIMESTAMP;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h
b/drivers/hwtracing/coresight/coresight-etm4x.h
index ba8d3f8..8a62c6c 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -146,6 +146,7 @@
#define ETM_ARCH_V4 0x40
#define ETMv4_SYNC_MASK 0x1F
#define ETM_CYC_THRESHOLD_MASK 0xFFF
+#define ETM_CYC_THRESHOLD_DEFAULT 256
#define ETMv4_EVENT_MASK 0xFF
#define ETM_CNTR_MAX_VAL 0xFFFF
#define ETM_TRACEID_MASK 0x3f
--
2.7.4
--
Mike Leach
Principal Engineer, ARM Ltd.
Blackburn Design Centre. UK
On 8 December 2016 at 02:04, Chunyan Zhang <zhang.chunyan(a)linaro.org> wrote:
>
> Hi Nicolas,
>
> On 8 December 2016 at 16:07, Nicolas GUION <nicolas.guion(a)st.com> wrote:
>
>> Chunyan,
>>
>> No problem and it offers me the opportunity to inform you that this last
>> months in ST I worked on ARM coresight trace.
>>
>> Several month ago I contacted Mathieu about ARM STM coresight feature.
>> Actually this year we started a new SOC project Accorod5, around A7ss and
>> of course with integration of ARM coresight components. Mathieu described
>> me the status in january, the next steps and especially added me in the
>> group for all patch dedicated to this topic.
>>
>>
>> So I followed the progression of the patch set delivery in official linux
>> stream, and in october I started the integration of this topic in our BSP
>> (based form 4.1)
>>
>> -update the both components (stm_class/coresight) of hwtracing from
>> recent kernel in our old kernel.
>> -integrate the on-going ftrace patch (it was the version 6)
>>
>>
> So happy to know you have been following the progress of this patch
> series, Steven Rostedt has included these for next merge window, it's
> supposed to be merged into 4.10.
> git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git
> <http://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.gitfor-n…>
> for-next
>
>>
>> One difference with the Linaro usage that your team usually describes is
>> the capture way, instead to use the target itself
>> we configure the stm to tpiu directly (skip ETF path) and use an external
>> probe to capture the trace (Lauterbach tool),
>> (to cover a long trace session, get the trace for kernel
>> crash/deadlock...)
>>
>
> As an assignee from Spreadtrum, I believe that Spreadtrum also would need
> this functionality.
>
Hello Nicolas,
First and foremost congratulation on the very good integration work. I
have been adamant on that point many times before and today won't be
different - ST has really good tracing technology and knowledge. You guys
have been working on this for a very long time and the results are there.
Au plaisir,
Mathieu
>
>> Here is a view of the T32 output with 2 masters (Cortex A7 and Cortex
>> M3), and 2 STM client for A7 part (Kernel log and FTRACE)
>>
> That's amazing, but I haven't seen the snapshot you mentioned here :)
>
>
>> this snaphot is not the last version, now the Timestamp are correctly
>> handled and the differentiation between the both A7 CPUs has been deported
>> on STMchannel due to a regression of our SOC
>> (our SOC didn't implement correctly the AHB link between the both A7
>> master to STM, so I used the even channel for A7_0 and odd channel for
>> A7_1, it was more or less the only modification from your patch)
>>
>>
>> Thanks for sharing,
> Chunyan
>
>>
>> *Great Job for all this coresight trace development!*
>>
>>
>> br
>>
>> Nicolas
>>
>>
>>
>> On 12/08/2016 08:30 AM, Chunyan Zhang wrote:
>>
>>
>>
>> On 8 December 2016 at 15:04, Nicolas GUION <nicolas.guion(a)st.com> wrote:
>>
>>> Hi Chunyan,
>>>
>>> Are you sure that you pointed the correct Nicolas, cause I'm really far
>>> to know the Dragonboard 410c board?
>>>
>>
>> Ah, my mistake, thanks for telling me :)
>>
>> Chunyan
>>
>>
>>> I'm working in STMicroelectronics and not usual with other boards than
>>> ST ones.
>>>
>>> br
>>> Nicolas
>>>
>>>
>>> On 12/08/2016 07:24 AM, Chunyan Zhang wrote:
>>>
>>> Hi Nicolas,
>>>
>>> I noticed on 96boards forum, some person reported a similar problem "*Dragonboard
>>> not working after failed linux instalation*" [1] which has been
>>> annoying me recently.
>>>
>>> I posted some details on that page the day before yesterday. Could you
>>> give me some suggestion on how to retrieve my Dragon board?
>>>
>>> Many thanks,
>>> Chunyan
>>>
>>>
>>> [1] http://www.96boards.org/forums/topic/dragonboard-not-working
>>> -after-failed-linux-instalation/#post-18901&gsc.tab=0
>>>
>>>
>>>
>>
>>
>
