CoreSight August 2020

coresight@lists.linaro.org

22 participants
31 discussions

[PATCH v3 0/6] tracing: export event trace and trace_marker

by Tingwei Zhang

Ftrace has ability to export trace packets to other destination. Currently, only function trace can be exported. This series extends the support to event trace and trace_maker. STM is one possible destination to export ftrace. Use separate channel for each CPU to avoid mixing up packets from different CPUs together. Change from v2: Change flag definition to BIT(). (Steven) Add comment in stm_ftrace_write() to clarify it's safe to use smp_processor_id() here since preempt is disabled. (Steven) Change from v1: All changes are suggested by Steven Rostedt. User separate flag to control function trace, event trace and trace mark. Allocate channels according to num_possible_cpu() dynamically. Move ftrace_exports routines up so all ftrace can use them. Tingwei Zhang (6): stm class: ftrace: change dependency to TRACING tracing: add flag to control different traces tracing: add trace_export support for event trace tracing: add trace_export support for trace_marker stm class: ftrace: enable supported trace export flag stm class: ftrace: use different channel accroding to CPU drivers/hwtracing/stm/Kconfig | 2 +- drivers/hwtracing/stm/ftrace.c | 7 +- include/linux/trace.h | 7 + kernel/trace/trace.c | 270 ++++++++++++++++++--------------- 4 files changed, 159 insertions(+), 127 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

4 years, 4 months

[RFC] Making trace reads independent to task scheduling

by Andrea Brunato

Good morning, I noticed the trace data is read from the buffer only when the target task is scheduled in/out, leading to high variability of the trace data size. This can be an issue because trace data gets very different as in size (and thus as in its coverage) under different system load. Is getting trace reads independent w.r.t. task scheduling an idea which has already been considered? One possibility I’m considering is using an independent timer which triggers periodically trace reads from the sink buffer to achieve less variability. A couple of buffers (struct etr_buf) could also be used: one for gathering the trace data coming from the sink and another whose content to be copied over to the perf aux buffer. When the timer triggers, the buffers are switched such that it's always possible to copy the trace data to the perf aux buffer (in one buffer) while gathering the trace data coming from all the ETMs (in the other one). I have been thinking about this solution with a N:1 source:sink topology in mind, but I'm not sure how this would fit in a N:N topology, where every sink has its own buffer. What do you think about it? Are you aware of any limitations that should be taken into account? If we think this could work, the next step would probably be to prototype something that works on my N:1 topology board Thanks, Andrea

4 years, 4 months

Questions on OpenCSD tool

by Smitha Gautham

Hello, I am a PhD student from Virginia Commonwealth University. I wanted to use the OpenCSD tool to decode ETM and PTM traces. I have downloaded the OpenCSD tool and have decoded the test examples that come with it. I have some questions about the tool: 1) OpenCSD Interface to read trace a) As a first step towards learning about OpenCSD, I have installed it on my PC. I have Cortex M4 and Cortex A9 boards that have ETM/PTM modules. What are the interfaces supported by OpenCSD to read the trace from these boards ? b) Are there any specific boards, software and interfaces that OpenCSD has been tested against ? c) Can OpenCSD decoder interface with debuggers such as Segger JTrace or Keil Ulink Pro and decode instruction traces read from them ? d) Can OpenCSD be installed on a ARM Cortex processor and decode the traces for an application running on the same processor or a co-processor? 2) Can we decode traces of exceptions, changes in processor instruction set state, changes in processor security state, global system timestamps with OpenCSD ? 3) Is there a way to get raw decoded traces which have only Atom information(branch taken or not) and addresses from OpenCSD ? Thank you for your time and help with these questions. regards, Smitha

4 years, 4 months

[PATCH V2] coresight: Make sysFS functional on topologies with per core sink

by Linu Cherian

Coresight driver assumes sink is common across all the ETMs, and tries to build a path between ETM and the first enabled sink found using bus based search. This breaks sysFS usage on implementations that has multiple per core sinks in enabled state. For this, - coresight_find_sink API is updated with an additional flag so that it is able to return an enabled sink - coresight_get_enabled_sink API is updated to do a connection based search, when a source reference is given. Change-Id: I6cc91ddb3ef8936a8f41a5f7c7c455b0ece9d85d Signed-off-by: Linu Cherian <lcherian(a)marvell.com> --- Applies on https://git.linaro.org/kernel/coresight.git/log/?h=next Changes in V2: - Fixed few typos in commit message - Rephrased commit message .../hwtracing/coresight/coresight-etm-perf.c | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 5 +- drivers/hwtracing/coresight/coresight.c | 51 +++++++++++++++++-- 3 files changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 1a3169e69bb1..25041d2654e3 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -223,7 +223,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, id = (u32)event->attr.config2; sink = coresight_get_sink_by_id(id); } else { - sink = coresight_get_enabled_sink(true); + sink = coresight_get_enabled_sink(NULL, true); } mask = &event_data->mask; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index f2dc625ea585..010ed26db340 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -148,10 +148,13 @@ static inline void coresight_write_reg_pair(void __iomem *addr, u64 val, void coresight_disable_path(struct list_head *path); int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data); struct coresight_device *coresight_get_sink(struct list_head *path); -struct coresight_device *coresight_get_enabled_sink(bool reset); +struct coresight_device * +coresight_get_enabled_sink(struct coresight_device *source, bool reset); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * coresight_find_default_sink(struct coresight_device *csdev); +struct coresight_device * +coresight_find_enabled_sink(struct coresight_device *csdev); struct list_head *coresight_build_path(struct coresight_device *csdev, struct coresight_device *sink); void coresight_release_path(struct list_head *path); diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index e9c90f2de34a..ae69169c58d3 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -566,6 +566,10 @@ static int coresight_enabled_sink(struct device *dev, const void *data) /** * coresight_get_enabled_sink - returns the first enabled sink found on the bus + * When a source reference is given, enabled sink is found using connection based + * search. + * + * @source: Coresight source device reference * @deactivate: Whether the 'enable_sink' flag should be reset * * When operated from perf the deactivate parameter should be set to 'true'. @@ -576,10 +580,21 @@ static int coresight_enabled_sink(struct device *dev, const void *data) * parameter should be set to 'false', hence mandating users to explicitly * clear the flag. */ -struct coresight_device *coresight_get_enabled_sink(bool deactivate) +struct coresight_device * +coresight_get_enabled_sink(struct coresight_device *source, bool deactivate) { struct device *dev = NULL; + struct coresight_device *sink; + + if (!source) + goto bus_search; + sink = coresight_find_enabled_sink(source); + if (sink && deactivate) + sink->activated = false; + + return sink; +bus_search: dev = bus_find_device(&coresight_bustype, NULL, &deactivate, coresight_enabled_sink); @@ -828,6 +843,7 @@ coresight_select_best_sink(struct coresight_device *sink, int *depth, * * @csdev: source / current device to check. * @depth: [in] search depth of calling dev, [out] depth of found sink. + * @enabled: flag to search only enabled sinks * * This will walk the connection path from a source (ETM) till a suitable * sink is encountered and return that sink to the original caller. @@ -839,7 +855,7 @@ coresight_select_best_sink(struct coresight_device *sink, int *depth, * return best sink found, or NULL if not found at this node or child nodes. */ static struct coresight_device * -coresight_find_sink(struct coresight_device *csdev, int *depth) +coresight_find_sink(struct coresight_device *csdev, int *depth, bool enabled) { int i, curr_depth = *depth + 1, found_depth = 0; struct coresight_device *found_sink = NULL; @@ -862,7 +878,8 @@ coresight_find_sink(struct coresight_device *csdev, int *depth) child_dev = csdev->pdata->conns[i].child_dev; if (child_dev) - sink = coresight_find_sink(child_dev, &child_depth); + sink = coresight_find_sink(child_dev, &child_depth, + enabled); if (sink) found_sink = coresight_select_best_sink(found_sink, @@ -872,6 +889,10 @@ coresight_find_sink(struct coresight_device *csdev, int *depth) } return_def_sink: + /* Check if we need to return an enabled sink */ + if (enabled && found_sink) + if (!found_sink->activated) + found_sink = NULL; /* return found sink and depth */ if (found_sink) *depth = found_depth; @@ -901,10 +922,30 @@ coresight_find_default_sink(struct coresight_device *csdev) /* look for a default sink if we have not found for this device */ if (!csdev->def_sink) - csdev->def_sink = coresight_find_sink(csdev, &depth); + csdev->def_sink = coresight_find_sink(csdev, &depth, false); return csdev->def_sink; } +/** + * coresight_find_enabled_sink: Find the suitable enabled sink + * + * @csdev: starting source to find a connected sink. + * + * Walks connections graph looking for a suitable sink to enable for the + * supplied source. Uses CoreSight device subtypes and distance from source + * to select the best sink. + * + * Used in cases where the CoreSight user (sysfs) has selected a sink. + */ +struct coresight_device * +coresight_find_enabled_sink(struct coresight_device *csdev) +{ + int depth = 0; + + /* look for the enabled sink */ + return coresight_find_sink(csdev, &depth, true); +} + static int coresight_remove_sink_ref(struct device *dev, void *data) { struct coresight_device *sink = data; @@ -992,7 +1033,7 @@ int coresight_enable(struct coresight_device *csdev) * Search for a valid sink for this session but don't reset the * "enable_sink" flag in sysFS. Users get to do that explicitly. */ - sink = coresight_get_enabled_sink(false); + sink = coresight_get_enabled_sink(csdev, false); if (!sink) { ret = -EINVAL; goto out; -- 2.25.1

4 years, 4 months

[PATCH v2] coresight: stm: support marked packet

by Tingwei Zhang

STP_PACKET_MARKED is not supported by STM currently. Add STM_FLAG_MARKED to support marked packet in STM. Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org> --- drivers/hwtracing/coresight/coresight-stm.c | 11 +++++++---- include/uapi/linux/coresight-stm.h | 1 + 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index b908ca104645..f1969051a6aa 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -412,6 +412,7 @@ static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, void __iomem *ch_addr; struct stm_drvdata *drvdata = container_of(stm_data, struct stm_drvdata, stm); + unsigned int stm_flags; if (!(drvdata && local_read(&drvdata->mode))) return -EACCES; @@ -421,8 +422,9 @@ static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, ch_addr = stm_channel_addr(drvdata, channel); - flags = (flags == STP_PACKET_TIMESTAMPED) ? STM_FLAG_TIMESTAMPED : 0; - flags |= test_bit(channel, drvdata->chs.guaranteed) ? + stm_flags = (flags & STP_PACKET_TIMESTAMPED) ? + STM_FLAG_TIMESTAMPED : 0; + stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ? STM_FLAG_GUARANTEED : 0; if (size > drvdata->write_bytes) @@ -432,7 +434,7 @@ static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, switch (packet) { case STP_PACKET_FLAG: - ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, flags); + ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags); /* * The generic STM core sets a size of '0' on flag packets. @@ -444,7 +446,8 @@ static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, break; case STP_PACKET_DATA: - ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, flags); + stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0; + ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags); stm_send(ch_addr, payload, size, drvdata->write_bytes); break; diff --git a/include/uapi/linux/coresight-stm.h b/include/uapi/linux/coresight-stm.h index 8847dbf24151..7ff3709c01b8 100644 --- a/include/uapi/linux/coresight-stm.h +++ b/include/uapi/linux/coresight-stm.h @@ -5,6 +5,7 @@ #include <linux/const.h> #define STM_FLAG_TIMESTAMPED _BITUL(3) +#define STM_FLAG_MARKED _BITUL(4) #define STM_FLAG_GUARANTEED _BITUL(7) /* -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

4 years, 4 months

[RFC PATCH 00/14] coresight: Support for ETMv4.4 system instructions

by Suzuki K Poulose

CoreSight ETMv4.4 introduced system instructions for accessing the ETM. This also implies that they may not be on the amba bus. Right now all the CoreSight components are accessed via memory map. Also, we have some common routines in coresight generic code driver (e.g, CS_LOCK, claim/disclaim), which assume the mmio. In order to preserve the generic algorithms at a single place and to allow dynamic switch for ETMs, this series introduces an abstraction layer for accessing a coresight device. It is designed such that the mmio access are fast tracked (i.e, without an indirect function call). This will also help us to get rid of the driver+attribute specific sysfs show/store routines and replace them with a single routine to access a given register offset (which can be embedded in the dev_ext_attribute). This is not currently implemented in the series, but can be achieved. Further we switch the generic routines to work with the abstraction. With this in place, we refactor the etm4x code a bit to allow for supporting the system instructions with very little new code. The changes also switch to using the system instructions by default even when we may have an MMIO. The series has been mildly tested on a model. I would really appreciate any testing on real hardware. Applies on coresight/next tree. The tree is also available here : git://linux-arm.org/linux-skp.git etm-4.4/rfc Suzuki K Poulose (14): coresight: etm4x: Skip save/restore before device registration coresight: Introduce device access abstraction coresight: tpiu: Use coresight device access abstraction coresight: etm4x: Free up argument of etm4_init_arch_data coresight: Convert coresight_timeout to use access abstraction coresight: Convert claim and lock operations to use access wrappers coresight: etm4x: Always read the registers on the host CPU coresight: etm4x: Convert all register accesses coresight: etm4x: Add sysreg access helpers coresight: etm4x: Define DEVARCH register fields coresight: etm4x: Detect system register access support coresight: etm4x: Refactor probing routine coresight: etm4x: Add support for sysreg only devices dts: bindings: coresight: ETMv4.4 system register access only units .../devicetree/bindings/arm/coresight.txt | 6 +- drivers/hwtracing/coresight/coresight-catu.c | 17 +- .../hwtracing/coresight/coresight-cpu-debug.c | 26 +- .../hwtracing/coresight/coresight-cti-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-cti.c | 31 +- drivers/hwtracing/coresight/coresight-etb10.c | 26 +- .../coresight/coresight-etm3x-sysfs.c | 8 +- drivers/hwtracing/coresight/coresight-etm3x.c | 45 +- .../coresight/coresight-etm4x-sysfs.c | 32 +- drivers/hwtracing/coresight/coresight-etm4x.c | 580 +++++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 403 +++++++++++- .../hwtracing/coresight/coresight-funnel.c | 19 +- drivers/hwtracing/coresight/coresight-priv.h | 9 +- .../coresight/coresight-replicator.c | 28 +- drivers/hwtracing/coresight/coresight-stm.c | 49 +- .../hwtracing/coresight/coresight-tmc-etf.c | 36 +- .../hwtracing/coresight/coresight-tmc-etr.c | 19 +- drivers/hwtracing/coresight/coresight-tmc.c | 10 +- drivers/hwtracing/coresight/coresight-tpiu.c | 32 +- drivers/hwtracing/coresight/coresight.c | 130 +++- include/linux/coresight.h | 189 +++++- 21 files changed, 1273 insertions(+), 426 deletions(-) -- 2.24.1

4 years, 4 months

[PATCHv3] coresight: etm4x: Fix etm4_count race by moving cpuhp callbacks to init

by Sai Prakash Ranjan

etm4_count keeps track of number of ETMv4 registered and on some systems, a race is observed on etm4_count variable which can lead to multiple calls to cpuhp_setup_state_nocalls_cpuslocked(). This function internally calls cpuhp_store_callbacks() which prevents multiple registrations of callbacks for a given state and due to this race, it returns -EBUSY leading to ETM probe failures like below. coresight-etm4x: probe of 7040000.etm failed with error -16 This race can easily be triggered with async probe by setting probe type as PROBE_PREFER_ASYNCHRONOUS and with ETM power management property "arm,coresight-loses-context-with-cpu". Prevent this race by moving cpuhp callbacks to etm driver init since the cpuhp callbacks doesn't have to depend on the etm4_count and can be once setup during driver init. Similarly we move cpu_pm notifier registration to driver init and completely remove etm4_count usage. Also now we can use non cpuslocked version of cpuhp callbacks with this movement. Fixes: 9b6a3f3633a5 ("coresight: etmv4: Fix CPU power management setup in probe() function") Fixes: 58eb457be028 ("hwtracing/coresight-etm4x: Convert to hotplug state machine") Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org> --- Changes in v3: * Minor cleanups from v2 and change to device_initcall (Stephen Boyd) * Move to non cpuslocked cpuhp callbacks and rename to etm_pm_setup() (Mike Leach) Changes in v2: * Rearrange cpuhp callbacks and move them to driver init (Suzuki K Poulose) --- drivers/hwtracing/coresight/coresight-etm4x.c | 65 +++++++++---------- 1 file changed, 31 insertions(+), 34 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 6d7d2169bfb2..fddfd93b9a7b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -48,8 +48,6 @@ module_param(pm_save_enable, int, 0444); MODULE_PARM_DESC(pm_save_enable, "Save/restore state on power down: 1 = never, 2 = self-hosted"); -/* The number of ETMv4 currently registered */ -static int etm4_count; static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; static void etm4_set_default_config(struct etmv4_config *config); static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, @@ -1398,28 +1396,25 @@ static struct notifier_block etm4_cpu_pm_nb = { .notifier_call = etm4_cpu_pm_notify, }; -/* Setup PM. Called with cpus locked. Deals with error conditions and counts */ -static int etm4_pm_setup_cpuslocked(void) +/* Setup PM. Deals with error conditions and counts */ +static int __init etm4_pm_setup(void) { int ret; - if (etm4_count++) - return 0; - ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb); if (ret) - goto reduce_count; + return ret; - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, - "arm/coresight4:starting", - etm4_starting_cpu, etm4_dying_cpu); + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING, + "arm/coresight4:starting", + etm4_starting_cpu, etm4_dying_cpu); if (ret) goto unregister_notifier; - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, - "arm/coresight4:online", - etm4_online_cpu, NULL); + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight4:online", + etm4_online_cpu, NULL); /* HP dyn state ID returned in ret on success */ if (ret > 0) { @@ -1428,21 +1423,15 @@ static int etm4_pm_setup_cpuslocked(void) } /* failed dyn state - remove others */ - cpuhp_remove_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING); + cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); unregister_notifier: cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); - -reduce_count: - --etm4_count; return ret; } -static void etm4_pm_clear(void) +static void __init etm4_pm_clear(void) { - if (--etm4_count != 0) - return; - cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); if (hp_online) { @@ -1498,22 +1487,12 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) if (!desc.name) return -ENOMEM; - cpus_read_lock(); etmdrvdata[drvdata->cpu] = drvdata; if (smp_call_function_single(drvdata->cpu, etm4_init_arch_data, drvdata, 1)) dev_err(dev, "ETM arch init failed\n"); - ret = etm4_pm_setup_cpuslocked(); - cpus_read_unlock(); - - /* etm4_pm_setup_cpuslocked() does its own cleanup - exit on error */ - if (ret) { - etmdrvdata[drvdata->cpu] = NULL; - return ret; - } - if (etm4_arch_supported(drvdata->arch) == false) { ret = -EINVAL; goto err_arch_supported; @@ -1560,7 +1539,6 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) err_arch_supported: etmdrvdata[drvdata->cpu] = NULL; - etm4_pm_clear(); return ret; } @@ -1598,4 +1576,23 @@ static struct amba_driver etm4x_driver = { .probe = etm4_probe, .id_table = etm4_ids, }; -builtin_amba_driver(etm4x_driver); + +static int __init etm4x_init(void) +{ + int ret; + + ret = etm4_pm_setup(); + + /* etm4_pm_setup() does its own cleanup - exit on error */ + if (ret) + return ret; + + ret = amba_driver_register(&etm4x_driver); + if (ret) { + pr_err("Error registering etm4x driver\n"); + etm4_pm_clear(); + } + + return ret; +} +device_initcall(etm4x_init); -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

4 years, 4 months

[PATCH v7 00/25] coresight: allow to build coresight as modules

by Tingwei Zhang

Allow to build coresight as modules. This gives developers the feasibility to test their code without reboot. This series is based on below two series. - "coresight: allow to build components as modules" https://lkml.org/lkml/2018/6/5/989 - "coresight: make drivers modular" https://lkml.org/lkml/2020/1/17/468 Change from v6: Correct module description for CATU (Mike) Check ect_ret equals 0 and set ect_enabled flag (Mike) Add Tested-by and Reviewed-by from Mike Change from v5: Add below CTI clean up change from Mike into series -https://lists.linaro.org/pipermail/coresight/2020-July/004349.html Increase module reference count when enabling CTI device (Mike) Change from v4: Fix error handling in coresight_grab_devicei() (Greg) Add coresight: cti: Fix remove sysfs link error from Mike -https://lists.linaro.org/pipermail/coresight/2020-July/004275.html Move cti_remove_conn_xrefs() into cti_remove() (Mike) Align patch subject to coresight: <component>: <description> (Mike) Change from v3: Rebase to coresight-next (Mike and Mathieu) Reorder try_get_module() (Suzuki) Clean up etmdrvdata[] in device remote path (Mike) Move cti_remove_conn_xrefs to cti_remove (Mike) Change from v2: Rebase to 5.8-rc5. Export coresight_add_sysfs_link and coresight_remove_sysfs_link Fix one cut and paste error on MODULE_DESCRIPTION of CTI Change from v1: Use try_module_get() to avoid module to be unloaded when device is used in active trace session. (Mathieu P) Change from above two series. This series adds the support to dynamically remove module when the device in that module is enabled and used by some trace path. It disables all trace paths with that device and release the trace path. Kim Phillips (7): coresight: use IS_ENABLED for CONFIGs that may be modules coresight: etm3x: allow etm3x to be built as a module coresight: etm4x: allow etm4x to be built as a module coresight: etb: allow etb to be built as a module coresight: tpiu: allow tpiu to be built as a module coresight: tmc: allow tmc to be built as a module coresight: allow funnel and replicator drivers to be built as modules Mian Yousaf Kaukab (4): coresight: export global symbols coresight: funnel: remove multiple init calls from funnel driver coresight: replicator: remove multiple init calls coresight: tmc-etr: add function to register catu ops Mike Leach (1): coresight: cti: Fix remove sysfs link error Tingwei Zhang (13): coresight: cpu_debug: add module name in Kconfig coresight: cpu_debug: define MODULE_DEVICE_TABLE coresight: add coresight prefix to barrier_pkt coresight: add try_get_module() in coresight_grab_device() coresight: stm: allow to build coresight-stm as a module coresight: etm: perf: Fix warning caused by etm_setup_aux failure coresight: cti: add function to register cti associate ops coresight: cti: Fix bug clearing sysfs links on callback coresight: cti: don't disable ect device if it's not enabled coresight: cti: increase reference count when enabling cti coresight: cti: allow cti to be built as a module coresight: catu: allow catu drivers to be built as modules coresight: allow the coresight core driver to be built as a module drivers/hwtracing/coresight/Kconfig | 54 +++++-- drivers/hwtracing/coresight/Makefile | 22 +-- drivers/hwtracing/coresight/coresight-catu.c | 37 ++++- drivers/hwtracing/coresight/coresight-catu.h | 2 - .../{coresight.c => coresight-core.c} | 134 +++++++++++++++--- .../hwtracing/coresight/coresight-cpu-debug.c | 2 + .../{coresight-cti.c => coresight-cti-core.c} | 62 ++++++-- drivers/hwtracing/coresight/coresight-etb10.c | 22 ++- .../hwtracing/coresight/coresight-etm-perf.c | 13 +- .../hwtracing/coresight/coresight-etm-perf.h | 5 +- ...resight-etm3x.c => coresight-etm3x-core.c} | 27 +++- ...resight-etm4x.c => coresight-etm4x-core.c} | 26 +++- .../hwtracing/coresight/coresight-funnel.c | 62 +++++++- .../hwtracing/coresight/coresight-platform.c | 1 + drivers/hwtracing/coresight/coresight-priv.h | 24 ++-- .../coresight/coresight-replicator.c | 63 +++++++- drivers/hwtracing/coresight/coresight-stm.c | 20 ++- drivers/hwtracing/coresight/coresight-sysfs.c | 2 + .../{coresight-tmc.c => coresight-tmc-core.c} | 19 ++- .../hwtracing/coresight/coresight-tmc-etf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etr.c | 21 ++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpiu.c | 19 ++- include/linux/coresight.h | 3 +- 24 files changed, 559 insertions(+), 86 deletions(-) rename drivers/hwtracing/coresight/{coresight.c => coresight-core.c} (93%) rename drivers/hwtracing/coresight/{coresight-cti.c => coresight-cti-core.c} (94%) rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (97%) rename drivers/hwtracing/coresight/{coresight-etm4x.c => coresight-etm4x-core.c} (98%) rename drivers/hwtracing/coresight/{coresight-tmc.c => coresight-tmc-core.c} (96%) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

4 years, 4 months

[PATCH] arm64: dts: qcom: sdm845: Save Restore ETM Context

by Andrea Brunato

Specify coresight-loses-context-with-cpu, making the ETM driver to save the context on power-down. While running system-wide tracing (-a) on DragonBoard845c, I hit the following: WARNING: CPU: 0 PID: 488 at drivers/hwtracing/coresight/coresight.c:209 coresight_disclaim_device_unlocked+0x1c/0x38 Modules linked in: CPU: 0 PID: 488 Comm: plain_perf Not tainted 5.8.0-rc6-34384-g9a3868dbef01 #6 Hardware name: Thundercomm Dragonboard 845c (DT) pstate: 80400085 (Nzcv daIf +PAN -UAO BTYPE=--) pc : coresight_disclaim_device_unlocked+0x1c/0x38 lr : etm4_disable_hw+0xb8/0xf0 sp : ffff8000126139a0 x29: ffff8000126139a0 x28: ffff0000e9c90000 x27: ffff0000f158f180 x26: ffff0000f524d800 x25: ffff0000fd6aba30 x24: 0000000000000004 x23: ffff0000f158fa00 x22: ffff3aa88d4f9000 x21: ffff0000f5196800 x20: ffff0000f524d800 x19: ffff0000f524d080 x18: 0000000000000000 x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000 x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 x11: 0000000000000000 x10: 0000000000000000 x9 : ffffc5586ed1ef88 x8 : ffff0000e9c90000 x7 : 00000000afa099e8 x6 : 00000000295ce537 x5 : 0000000000000001 x4 : ffff8000105152a4 x3 : 0000000000000001 x2 : ffff0000f524d1fc x1 : 0000000000000000 x0 : ffff800010515fa4 Call trace: coresight_disclaim_device_unlocked+0x1c/0x38 etm4_disable+0x5c/0xe0 etm_event_stop+0xb4/0x128 etm_event_del+0x1c/0x28 event_sched_out.isra.0+0xbc/0x250 group_sched_out.part.0+0x48/0xb8 __perf_event_disable+0xec/0x258 event_function+0xa4/0x130 remote_function+0x64/0x78 generic_exec_single+0xc4/0x150 smp_call_function_single+0x178/0x208 event_function_call+0x150/0x160 _perf_event_disable+0x48/0x70 perf_event_for_each_child+0x40/0x90 _perf_ioctl+0x220/0x630 perf_ioctl+0x50/0x80 ksys_ioctl+0xb0/0xf0 __arm64_sys_ioctl+0x28/0x38 el0_svc_common.constprop.0+0x7c/0x198 do_el0_svc+0x2c/0x98 el0_sync_handler+0x9c/0x1b8 el0_sync+0x158/0x180 This looks like due to ETM losing context with CPU power down and thus losing the CLAIM tags, leading to an empty CLAIM tag set while disabling the ETM. Adding the "coresight-loses-context-with-cpu" property to the ETM nodes fixes the issue. Also the amount of trace collected is significantly larger than without the patch. Signed-off-by: Andrea Brunato <andrea.brunato(a)arm.com> Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- PS: I experienced this on DragonBoard845c. I am not sure if this issue persists on other board based on the sd845. Sai, could you please share your thoughts? --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8eb5a31346d2..42f5a08d8d34 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2643,6 +2643,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -2662,6 +2663,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -2681,6 +2683,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -2700,6 +2703,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -2719,6 +2723,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -2738,6 +2743,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -2757,6 +2763,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -2776,6 +2783,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { -- 2.17.1

4 years, 4 months

Désinfectants

by Cecylia Lazar

Bonjour Je contacte au nom du fabricant de savons, liquides et gels pour la désinfection des mains et les produits de nettoyage. Je voudrais vous offrir des produits de désinfection inodores qui nettoient et désinfectent efficacement la peau, éliminant les virus et les bactéries de vos mains. Les produits de désinfection sont destinés à un usage général et professionnel (hôpitaux, salles de traitement, laboratoires et autres). Nous proposons également des savons liquides efficaces avec une large gamme de parfums, gels douche, shampooings et revitalisants capillaires, et des détergents concentrés qui se distinguent sur le marché avec des performances élevées. Nos produits sont sans danger pour tous les types de peau, destinés à un usage quotidien, ils ne contiennent ni silicones ni parabènes. En raison du bon rapport qualité-prix, les cosmétiques et les produits de lavage sont très populaires sur les marchés européens. Puis-je présenter une offre? Cordialement Cecylia Lazar Responsable du développement commercial

4 years, 4 months

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CoreSight August 2020