CoreSight May 2023

coresight@lists.linaro.org

10 participants
26 discussions

by Suzuki K Poulose

Hi Greg Please find a couple of fixes for v6.4 for the coresight self-hosted tracing subsystem. Kindly pull. Suzuki The following changes since commit ac9a78681b921877518763ba0e89202254349d1b: Linux 6.4-rc1 (2023-05-07 13:34:35 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-fixes-v6.4 for you to fetch changes up to 04ac7f98b92181179ea84439642493f3826d04a2: coresight: perf: Release Coresight path when alloc trace id failed (2023-05-11 11:18:21 +0100) ---------------------------------------------------------------- coresight: Fixes for v6.4 Couple of fixes for coresight self-hosted tracing subsystem for v6.4. These include : - Fix signedness bug in tmc_etr_buf_insert_barrier_packet() - Fix memory leak with failing to release the path if trace-id allocation fails Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Dan Carpenter (1): coresight: Fix signedness bug in tmc_etr_buf_insert_barrier_packet() Ruidong Tian (1): coresight: perf: Release Coresight path when alloc trace id failed drivers/hwtracing/coresight/coresight-etm-perf.c | 1 + drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)

12 months

[PATCH] perf cs-etm: Fix contextid validation

by James Clark

Pre 5.11 kernels don't support 'contextid1' and 'contextid2' so validation would be skipped. By adding an additional check for 'contextid', old kernels will still have validation done even though contextid would either be contextid1 or contextid2. Additionally now that it's possible to override options, an existing bug in the validation is revealed. 'val' is overwritten by the contextid1 validation, and re-used for contextid2 validation causing it to always fail. '!val || val != 0x4' is the same as 'val != 0x4' because 0 is also != 4, so that expression can be simplified and the temp variable not overwritten. Fixes: 35c51f83dd1e ("perf cs-etm: Validate options after applying them") Reviewed-by: Leo Yan <leo.yan(a)linaro.org> Link: https://lore.kernel.org/all/20230501073452.GA4660@leoy-yangtze.lan Signed-off-by: James Clark <james.clark(a)arm.com> --- tools/perf/arch/arm/util/cs-etm.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 77cb03e6ff87..9ca040bfb1aa 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -78,9 +78,9 @@ static int cs_etm_validate_context_id(struct auxtrace_record *itr, char path[PATH_MAX]; int err; u32 val; - u64 contextid = - evsel->core.attr.config & - (perf_pmu__format_bits(&cs_etm_pmu->format, "contextid1") | + u64 contextid = evsel->core.attr.config & + (perf_pmu__format_bits(&cs_etm_pmu->format, "contextid") | + perf_pmu__format_bits(&cs_etm_pmu->format, "contextid1") | perf_pmu__format_bits(&cs_etm_pmu->format, "contextid2")); if (!contextid) @@ -114,8 +114,7 @@ static int cs_etm_validate_context_id(struct auxtrace_record *itr, * 0b00100 Maximum of 32-bit Context ID size. * All other values are reserved. */ - val = BMVAL(val, 5, 9); - if (!val || val != 0x4) { + if (BMVAL(val, 5, 9) != 0x4) { pr_err("%s: CONTEXTIDR_EL1 isn't supported, disable with %s/contextid1=0/\n", CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); return -EINVAL; -- 2.34.1

12 months

Re: [PATCH v1] perf arm: Fix include path

by Leo Yan

Hi Ian, On Mon, May 08, 2023 at 02:31:28PM -0700, Ian Rogers wrote: > Change "../cs-etm.h" to just "cs-etm.h" as ../cs-etm.h doesn't exist. > > Signed-off-by: Ian Rogers <irogers(a)google.com> > --- > tools/perf/arch/arm/util/pmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c > index 860a8b42b4b5..46154c226fbb 100644 > --- a/tools/perf/arch/arm/util/pmu.c > +++ b/tools/perf/arch/arm/util/pmu.c > @@ -12,7 +12,7 @@ > #include "arm-spe.h" > #include "hisi-ptt.h" > #include "../../../util/pmu.h" > -#include "../cs-etm.h" This code is a bit tricky. Here it deliberately uses "../cs-etm.h" to avoid including the header file in the same folder, alternatively, the compiler option "-I/home/leoy/Work/linux/tools/perf/util/include" will lead the C file to include "tools/perf/util/include/../cs-etm.h". > +#include "cs-etm.h" So with this change, perf will fail to build actually :) We need to change to: #include "../../../util/cs-etm.h" With above change: Reviewed-by: Leo Yan <leo.yan(a)linaro.org> Thanks for code improvement! > struct perf_event_attr > *perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused) > -- > 2.40.1.521.gf1e218fcd8-goog >

1 year

Re: [PATCH v4 2/3] dt-bindings: arm: Add Coresight Dummy Trace

by Suzuki K Poulose

On 05/05/2023 10:24, Hao Zhang wrote: > Add new coresight-dummy.yaml file describing the bindings required > to define coresight dummy trace in the device trees. > > Signed-off-by: Hao Zhang <quic_hazha(a)quicinc.com> > --- > .../bindings/arm/arm,coresight-dummy.yaml | 102 ++++++++++++++++++ > 1 file changed, 102 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml > > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml > new file mode 100644 > index 000000000000..126518863eea > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy.yaml > @@ -0,0 +1,102 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/arm,coresight-dummy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM Coresight Dummy component > + > +description: | > + Coresight Dummy Trace Module is for the specific devices that kernel > + don't have permission to access or configure, e.g., CoreSight TPDMs > + on Qualcomm platforms. So there need driver to register dummy devices > + as Coresight devices. It may also be used to define components that > + may not have any programming interfaces (e.g, static links), so that > + paths can be established in the driver. Provide Coresight API for > + dummy device operations, such as enabling and disabling dummy devices. > + Build the Coresight path for dummy sink or dummy source for debugging. > + > + The primary use case of the coresight dummy is to build path in kernel > + side for dummy sink and dummy source. > + > +maintainers: > + - Mao Jinlong <quic_jinlmao(a)quicinc.com> > + - Tao Zhang <quic_taozha(a)quicinc.com> > + - Hao Zhang <quic_hazha(a)quicinc.com> > + - Yuanfang Zhang <quic_yuanfang(a)quicinc.com> Given this is a generic "CoreSight" component, I would prefer to have the CoreSight subsystem maintainers listed here (too). I don't mind the entries above, but would like to make sure that the subsystem people are aware of the changes happening here. Please use: Mike Leach <mike.leach(a)linaro.org> Suzuki K Poulose <suzuki.poulose(a)arm.com> Leo Yan <leo.yan(a)linaro.org> With the above: Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > + > +properties: > + compatible: > + items: > + - enum: > + - arm,coresight-dummy-sink > + - arm,coresight-dummy-source > + > + out-ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port: > + description: Output connection from the source to Coresight > + Trace bus. > + $ref: /schemas/graph.yaml#/properties/port > + > + in-ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port: > + description: Input connection from the Coresight Trace bus to > + dummy sink, such as Embedded USB debugger(EUD). > + $ref: /schemas/graph.yaml#/properties/port > + > +required: > + - compatible > + > +if: > + # If the compatible contains the below value > + properties: > + compatible: > + contains: > + const: arm,coresight-dummy-sink > + > +then: > + required: > + - in-ports > + > +else: > + required: > + - out-ports > + > +additionalProperties: false > + > +examples: > + # Minimum dummy sink definition. Dummy sink connect to coresight replicator. > + - | > + sink { > + compatible = "arm,coresight-dummy-sink"; > + > + in-ports { > + port { > + eud_in_replicator_swao: endpoint { > + remote-endpoint = <&replicator_swao_out_eud>; > + }; > + }; > + }; > + }; > + > + # Minimum dummy source definition. Dummy source connect to coresight funnel. > + - | > + source { > + compatible = "arm,coresight-dummy-source"; > + > + out-ports { > + port { > + dummy_riscv_out_funnel_swao: endpoint { > + remote-endpoint = <&funnel_swao_in_dummy_riscv>; > + }; > + }; > + }; > + }; > + > +...

1 year

Re: [PATCH v4 1/3] Coresight: Add coresight dummy driver

by Suzuki K Poulose

On 05/05/2023 10:24, Hao Zhang wrote: > Some Coresight devices that kernel don't have permission to access or > configure. So there need driver to register dummy devices as Coresight > devices. It may also be used to define components that may not have > any programming interfaces (e.g, static links), so that paths can be > established in the driver. Provide Coresight API for dummy device > operations, such as enabling and disabling dummy devices. Build the > Coresight path for dummy sink or dummy source for debugging. > > Signed-off-by: Hao Zhang <quic_hazha(a)quicinc.com> > --- > drivers/hwtracing/coresight/Kconfig | 11 ++ > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-dummy.c | 171 ++++++++++++++++++ > include/linux/coresight.h | 1 + > 4 files changed, 184 insertions(+) > create mode 100644 drivers/hwtracing/coresight/coresight-dummy.c > > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > index 2b5bbfffbc4f..06f0a7594169 100644 > --- a/drivers/hwtracing/coresight/Kconfig > +++ b/drivers/hwtracing/coresight/Kconfig > @@ -236,4 +236,15 @@ config CORESIGHT_TPDA > > To compile this driver as a module, choose M here: the module will be > called coresight-tpda. > + > +config CORESIGHT_DUMMY > + tristate "Dummy driver support" > + help > + Enables support for dummy driver. Dummy driver can be used for > + CoreSight sources/sinks that are owned and configured by some > + other subsystem and use Linux drivers to configure rest of trace > + path > + > + To compile this driver as a module, choose M here: the module will be > + called coresight-dummy. > endif > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index 33bcc3f7b8ae..995d3b2c76df 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -30,3 +30,4 @@ obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o > coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ > coresight-cti-sysfs.o > obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o > +obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o > diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c > new file mode 100644 > index 000000000000..ee9881ff4754 > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-dummy.c > @@ -0,0 +1,171 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/coresight.h> > +#include <linux/of.h> > +#include <linux/pm_runtime.h> Please follow the alphabetical order for the header files ^ > + > +#include "coresight-priv.h" > + > +struct dummy_drvdata { > + struct device *dev; nit: We don't need this really. And that completely removes the need for drvdata too. See below. > + struct coresight_device *csdev; > +}; > + > +DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source"); > +DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink"); > + > +static int dummy_source_enable(struct coresight_device *csdev, > + struct perf_event *event, u32 mode) > +{ > + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + dev_dbg(drvdata->dev, "Dummy source enabled\n"); dev_dbg(csdev->dev.parent, .."); Similarly for all instances below. > + > + return 0; > +} > + > +static void dummy_source_disable(struct coresight_device *csdev, > + struct perf_event *event) > +{ > + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + dev_dbg(drvdata->dev, "Dummy source disabled\n"); > +} > + > +static int dummy_sink_enable(struct coresight_device *csdev, u32 mode, > + void *data) > +{ > + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + dev_dbg(drvdata->dev, "Dummy sink enabled\n"); > + > + return 0; > +} > + > +static int dummy_sink_disable(struct coresight_device *csdev) > +{ > + struct dummy_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + > + dev_dbg(drvdata->dev, "Dummy sink disabled\n"); > + > + return 0; > +} > + > +static const struct coresight_ops_source dummy_source_ops = { > + .enable = dummy_source_enable, > + .disable = dummy_source_disable, > +}; > + > +static const struct coresight_ops dummy_source_cs_ops = { > + .source_ops = &dummy_source_ops, > +}; > + > +static const struct coresight_ops_sink dummy_sink_ops = { > + .enable = dummy_sink_enable, > + .disable = dummy_sink_disable, > +}; > + > +static const struct coresight_ops dummy_sink_cs_ops = { > + .sink_ops = &dummy_sink_ops, > +}; > + > +static int dummy_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct device_node *node = dev->of_node; > + struct coresight_platform_data *pdata; > + struct dummy_drvdata *drvdata; > + struct coresight_desc desc = { 0 }; > + > + if (of_device_is_compatible(node, "arm,coresight-dummy-source")) { > + > + desc.name = coresight_alloc_device_name(&source_devs, dev); > + if (!desc.name) > + return -ENOMEM; > + > + desc.type = CORESIGHT_DEV_TYPE_SOURCE; > + desc.subtype.source_subtype = > + CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; > + desc.ops = &dummy_source_cs_ops; > + } else if (of_device_is_compatible(node, "arm,coresight-dummy-sink")) { > + desc.name = coresight_alloc_device_name(&sink_devs, dev); > + if (!desc.name) > + return -ENOMEM; > + > + desc.type = CORESIGHT_DEV_TYPE_SINK; > + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_DUMMY; > + desc.ops = &dummy_sink_cs_ops; > + } else { > + dev_err(dev, "Device type not set\n"); > + return -EINVAL; > + } > + > + pdata = coresight_get_platform_data(dev); > + if (IS_ERR(pdata)) > + return PTR_ERR(pdata); > + pdev->dev.platform_data = pdata; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + drvdata->dev = &pdev->dev; > + platform_set_drvdata(pdev, drvdata); As above, you may remove the drvdata entirely. Otherwise looks good to me Suzuki

1 year

[PATCH 0/7] perf: cs-etm: Fixes around timestamped and timeless decoding

by James Clark

The first commit contains a fix for a recently introduced regression, but was always a shortcoming in the Coresight code anyway. The following commits are a tidyup in preparation for the last commit, which is a fairly major change to the decode logic that's also indirectly related to the regression so I thought it would be good time to fix that now. Applies to perf/core (9be6ab181b7b) James Clark (7): perf: cs-etm: Fix timeless decode mode detection perf tools: Add util function for overriding user set config values perf: cs-etm: Don't test full_auxtrace because it's always set perf: cs-etm: Validate options after applying them perf: cs-etm: Allow user to override timestamp and contextid settings perf: cs-etm: Use bool type for boolean values perf: cs-etm: Add separate decode paths for timeless and per-thread modes tools/perf/arch/arm/util/cs-etm.c | 223 +++++++++--------- tools/perf/arch/arm/util/pmu.c | 2 + tools/perf/arch/arm64/util/arm-spe.c | 26 +- tools/perf/arch/x86/util/intel-pt.c | 22 +- tools/perf/tests/shell/test_arm_coresight.sh | 24 ++ .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 8 +- tools/perf/util/cs-etm.c | 200 +++++++++++----- tools/perf/util/cs-etm.h | 6 +- tools/perf/util/evsel.c | 29 +++ tools/perf/util/evsel.h | 3 + 10 files changed, 325 insertions(+), 218 deletions(-) -- 2.34.1

1 year

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CoreSight May 2023