FEAT_TRF is a Coresight feature that allows trace capture to be
completely filtered at different exception levels, unlike the existing
TRCVICTLR controls which may still emit target addresses of branches,
even if the following trace is filtered.
Without FEAT_TRF, it was possible to start a trace session on a host and
also collect trace from the guest as TRCVICTLR was never programmed to
exclude guests (and it could still emit target addresses even if it
was). Now when FEAT_TRF is present, because we don't write to
TRFCR_EL1, guest trace will be completely disabled.
This change fixes this issue, and also adds the ability to control it
with the Perf exclude_host and exclude_guest flags.
The first commit moves the register to sysreg because I add the EL12
version in the second commit.
The test results have some single spurious EL2 addresses, but I don't
think this is an issue with this patchset because it happens in the
host-userspace case which maintains the existing programming of
TRFCR. It's likely an issue with the model but I will follow it up
separately.
The corresponding change for nVHE is here [1]. With nVHE the behaviour
is reversed, currently guest trace is always generated because the host
already writes to TRFCR_EL1. This is the same both with and without
FEAT_TRF.
[1]: https://lore.kernel.org/kvmarm/20230804101317.460697-1-james.clark@arm.com/
---
Changes since v1:
* Split new sysreg definitions into TRFCR_EL2 and TRFCR_ELx so that
TRFCR_ELx doesn't include CX which TRFCR_EL1 doesn't have.
* Mask out TS and CX before writing to TRFCR_EL1 because it doesn't
have CX and TS has no effect.
* Expand cover letter
James Clark (2):
arm64/sysreg: Move TRFCR definitions to sysreg
coresight: Allow guests to be traced when FEAT_TRF and VHE are present
arch/arm64/include/asm/sysreg.h | 12 -----
arch/arm64/tools/sysreg | 40 +++++++++++++++
.../coresight/coresight-etm4x-core.c | 51 ++++++++++++++++---
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
drivers/hwtracing/coresight/coresight-priv.h | 3 ++
5 files changed, 89 insertions(+), 19 deletions(-)
--
2.34.1
The timestamp can originate from two sources: the kernel timestamp,
which is recorded in the event PERF_RECORD_AUX, and the Arm CoreSight
hardware trace data. On some Arm platforms, CoreSight trace data fails
to support timestamp tracing. This can be due to either a missed
connection between the timer counter and Arm CoreSight or the absence
of support for the virtual timestamp. If Arm CoreSight fails to support
hardware timestamp tracing, we need to fall back on using the kernel
timestamp.
The current code can support both timestamp sources when synthesizing
samples. However, the decoding flow only relies on the hardware
timestamp. If the hardware timestamp is zero, it becomes impossible to
decode the trace data. Consequently, in this case, the commands below
won't output any samples:
perf record -e cs_etm// --per-thread --timestamp -- ls
perf script
To fix this issue, this patch unifies the method of resolving time:
1) It renames cs_etm__resolve_sample_time() to the more general name
cs_etm__resolve_time();
2) It changes the function argument type from 'cs_etm_traceid_queue' to
'cs_etm_packet_queue';
3) In the end, both the decoding flow and the assignment of timestamps
to samples call cs_etm__resolve_time() to obtain timestamp.
Signed-off-by: Leo Yan <leo.yan(a)linaro.org>
---
tools/perf/util/cs-etm.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 9729d006550d..fa88e731933d 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -400,6 +400,17 @@ void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
etmq->pending_timestamp_chan_id = trace_chan_id;
}
+static u64 cs_etm__resolve_time(struct cs_etm_queue *etmq,
+ struct cs_etm_packet_queue *packet_queue)
+{
+ struct cs_etm_auxtrace *etm = etmq->etm;
+
+ if (!etm->timeless_decoding && etm->has_virtual_ts)
+ return packet_queue->cs_timestamp;
+ else
+ return etm->latest_kernel_timestamp;
+}
+
static u64 cs_etm__etmq_get_timestamp(struct cs_etm_queue *etmq,
u8 *trace_chan_id)
{
@@ -419,8 +430,7 @@ static u64 cs_etm__etmq_get_timestamp(struct cs_etm_queue *etmq,
/* Acknowledge pending status */
etmq->pending_timestamp_chan_id = 0;
- /* See function cs_etm_decoder__do_{hard|soft}_timestamp() */
- return packet_queue->cs_timestamp;
+ return cs_etm__resolve_time(etmq, packet_queue);
}
static void cs_etm__clear_packet_queue(struct cs_etm_packet_queue *queue)
@@ -1434,18 +1444,6 @@ u64 cs_etm__convert_sample_time(struct cs_etm_queue *etmq, u64 cs_timestamp)
return cs_timestamp;
}
-static inline u64 cs_etm__resolve_sample_time(struct cs_etm_queue *etmq,
- struct cs_etm_traceid_queue *tidq)
-{
- struct cs_etm_auxtrace *etm = etmq->etm;
- struct cs_etm_packet_queue *packet_queue = &tidq->packet_queue;
-
- if (!etm->timeless_decoding && etm->has_virtual_ts)
- return packet_queue->cs_timestamp;
- else
- return etm->latest_kernel_timestamp;
-}
-
static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq,
struct cs_etm_traceid_queue *tidq,
u64 addr, u64 period)
@@ -1454,13 +1452,14 @@ static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq,
struct cs_etm_auxtrace *etm = etmq->etm;
union perf_event *event = tidq->event_buf;
struct perf_sample sample = {.ip = 0,};
+ struct cs_etm_packet_queue *packet_queue = &tidq->packet_queue;
event->sample.header.type = PERF_RECORD_SAMPLE;
event->sample.header.misc = cs_etm__cpu_mode(etmq, addr, tidq->el);
event->sample.header.size = sizeof(struct perf_event_header);
/* Set time field based on etm auxtrace config. */
- sample.time = cs_etm__resolve_sample_time(etmq, tidq);
+ sample.time = cs_etm__resolve_time(etmq, packet_queue);
sample.ip = addr;
sample.pid = thread__pid(tidq->thread);
@@ -1505,6 +1504,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq,
struct cs_etm_auxtrace *etm = etmq->etm;
struct perf_sample sample = {.ip = 0,};
union perf_event *event = tidq->event_buf;
+ struct cs_etm_packet_queue *packet_queue = &tidq->packet_queue;
struct dummy_branch_stack {
u64 nr;
u64 hw_idx;
@@ -1520,7 +1520,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq,
event->sample.header.size = sizeof(struct perf_event_header);
/* Set time field based on etm auxtrace config. */
- sample.time = cs_etm__resolve_sample_time(etmq, tidq);
+ sample.time = cs_etm__resolve_time(etmq, packet_queue);
sample.ip = ip;
sample.pid = thread__pid(tidq->prev_packet_thread);
--
2.34.1
Hi Rob,
> -----Original Message-----
> From: Rob Herring <robh(a)kernel.org>
> Sent: Monday, September 4, 2023 11:53 AM
> To: Linu Cherian <lcherian(a)marvell.com>
> Cc: linux-arm-kernel(a)lists.infradead.org; mike.leach(a)linaro.org; Sunil
> Kovvuri Goutham <sgoutham(a)marvell.com>; james.clark(a)arm.com;
> leo.yan(a)linaro.org; linux-kernel(a)vger.kernel.org;
> krzysztof.kozlowski+dt(a)linaro.org; George Cherian
> <gcherian(a)marvell.com>; suzuki.poulose(a)arm.com;
> coresight(a)lists.linaro.org; devicetree(a)vger.kernel.org;
> conor+dt(a)kernel.org; robh+dt(a)kernel.org
> Subject: [EXT] Re: [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add
> "memory-region" property
>
> External Email
>
> ----------------------------------------------------------------------
>
> On Mon, 04 Sep 2023 10:35:41 +0530, Linu Cherian wrote:
> > memory-region 0: Reserved trace buffer memory
> >
> > TMC ETR: When available, use this reserved memory region for
> > trace data capture. Same region is used for trace data
> > retention after a panic or watchdog reset.
> >
> > TMC ETF: When available, use this reserved memory region for
> > trace data retention synced from internal SRAM after a panic or
> > watchdog reset.
> >
> > memory-region 1: Reserved meta data memory
> >
> > TMC ETR, ETF: When available, use this memory for register
> > snapshot retention synced from hardware registers after a panic
> > or watchdog reset.
> >
> > Signed-off-by: Linu Cherian <lcherian(a)marvell.com>
> > ---
> > .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 13
> > +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4:
> [error] syntax error: expected <block end>, but found '<block mapping
> start>' (syntax)
> ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:105:5:
> [warning] wrong indentation: expected 5 but found 4 (indentation)
>
> dtschema/dtc warnings/errors:
> make[2]: *** Deleting file
> 'Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts'
> Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: did
> not find expected key
> make[2]: *** [Documentation/devicetree/bindings/Makefile:26:
> Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts]
> Error 1
> make[2]: *** Waiting for unfinished jobs....
> ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4:
> did not find expected key
> /builds/robherring/dt-review-
> ci/linux/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:
> ignoring, error parsing file
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500:
> dt_binding_check] Error 2
> make: *** [Makefile:234: __sub-make] Error 2
>
> doc reference errors (make refcheckdocs):
>
> See https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__patchwork.ozlabs.org_project_devicetree-
> 2Dbindings_patch_20230904050548.28047-2D2-2Dlcherian-
> 40marvell.com&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=DI9kird_6lFtBC
> VoGa5ogk3dJwsUlHLjLlgu0r46iU4&m=_ay-
> WtrQlhIwxRafvVeVQHuS8jVWvIzZWMmn3Kp2yAVpxITz-
> rjWiL4cMybMomHi&s=zvUJitULz2sVzal1I78gUQ3sBBTSAZmwDziKSNJbxwM&
> e=
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above error(s),
> then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your
> schema.
Ack. Will fix this in next version.
Introduction of TPDM DSB subunit
DSB subunit is responsible for creating a dataset element, and is also
optionally responsible for packing it to fit multiple elements on a
single ATB transfer if possible in the configuration. The TPDM Core
Datapath requests timestamps be stored by the TPDA and then delivering
ATB sized data (depending on ATB width and element size, this could
be smaller or larger than a dataset element) to the ATB Mast FSM.
The DSB subunit must be configured prior to enablement. This series
adds support for TPDM to configure the configure DSB subunit.
Once this series patches are applied properly, the new tpdm nodes for
should be observed at the tpdm path /sys/bus/coresight/devices/tpdm*
which supports DSB subunit.
e.g.
root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l
drwxr-xr-x 2 root root 0 Jan 1 00:00 connections
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type
-rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source
--w------- 1 root root 4096 Jan 1 00:00 integration_test
drwxr-xr-x 2 root root 0 Jan 1 00:00 power
--w------- 1 root root 4096 Jan 1 00:02 reset_dataset
lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight
-rw-r--r-- 1 root root 4096 Apr 5 2021 uevent
-r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier
We can use the commands are similar to the below to configure the
TPDMs which support DSB subunit. Enable coresight sink first.
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset
echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx
echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask
echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val
echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt_ts
echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt_type
echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts
echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5
echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2
echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source
TPDM_DSB commit tree:
https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v8https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v8
Changes in V8:
1. Refine the function "tpda_set_element_size" and rename it
to "tpda_get_element_size" in the patch#4.
-- Suzuki K Poulose
2. Refine the functioin "tpda_enable_port" in the patch#4.
-- Suzuki K Poulose
3. Write a helper to check if the TPDM has DSB dataset in the
patch#5.
-- Suzuki K Poulose
4. Move the function "tpdm_reset_datasets" to "datasets_setup"
to call in the patch#5.
-- Suzuki K Poulose
5. Refine the comment of DSB in "tpdm_drvdata" in the patch#5.
-- Suzuki K Poulose
6. Refine the comments in the documents for this patch series.
-- Suzuki K Poulose
7. Adjust the code alignment in this patch series.
-- Suzuki K Poulose
8. Combine the mode related functions to one in the patch#8.
-- Suzuki K Poulose
9. Refine the R/W functions of "dsb_mode" in the patch#8.
-- Suzuki K Poulose
10. Adjust the macros of mode in the TPDM header file in the
patch#8.
-- Suzuki K Poulose
11. Remove the unused code and fix the warnings in compiling
for the patch#9.
-- kernel test robot
12. Use the following sysfs nodes to read/set edge control
related value in the patch#9.
dsb_edge/
\- ctrl_idx -> Set the index number
\- ctrl_val -> Set the edge control value
\- ctrl_mask -> Set the edge control mask
\- edcr0 ... edcr15 -> Read the edge control value
\- edcmr0 ... edcmr7 -> Read the edge control mask
-- Suzuki K Poulose
13. Use the following sysfs nodes to read/set DSB trigger
pattern value and mask in the patch#10.
dsb_trig_patt/
\- xpr0 ... xpr15 -> (RW) Set/Get the value
\- xpmr0 ... xpmr7 -> (RW) Set/Get the mask
-- Suzuki K Poulose
14. Use the following sysfs nodes to read/set DSB pattern
value and mask in the patch#11.
dsb_patt/
\- tpr0 ... tpr15 -> (RW) Set/Get the value
\- tpmr0 ... tpmr7 -> (RW) Set/Get the mask
-- Suzuki K Poulose
15. Add "Acked-by" tag to the patch#12.
-- Rob Herring
16. Use the following sysfs nodes to read/set DSB MSR in
the patch#13.
dsb_msr/
\- msr0 ... msr31 -> (RW) Set/Get the value
-- Suzuki K Poulose
17. Create the maximal number of DSB MSR sysfs nodes if the
TPDM supports DSB MSR. Write the values set by user space to
the DSB MSR according to the number of MSR supported by the
TPDM.
-- Suzuki K Poulose
Changes in V7:
1. Since the "One value" limitation on SysFs file usage, add
the nodes to read/write the index number for configuring the
DSB TPDM. The following index number nodes are added.
"dsb_edge_ctrl_idx" in the patch #9
"dsb_trig_patt_idx" in the patch #10
"dsb_patt_idx" in the patch #11
"dsb_msr_idx" in the patch #13
-- Suzuki K Poulose
Changes in V6:
1. Align the code to fix the styling issue.
-- Suzuki K Poulose
Changes in V5:
1. Correct data type for DSB element size in dt-bindings patch.
2. Refine the recursive function "tpda_set_element_size".
-- Suzuki K Poulose
3. Get return value of the function "__tpda_enable" in
"tpda_enable".
-- Suzuki K Poulose
4. Refine the comments on "dsb_esize".
-- Suzuki K Poulose
5. Split the chage that introduce the subtype
"SUBTYPE_SOURCE_TPDM" to Coresight driver.
-- Suzuki K Poulose
6. Inline the trigger type setting to "tpdm_enable_dsb" simply.
-- Suzuki K Poulose
7. Split the change that remove the needless CS_{UN,}LOCK in
the function "tpdm_datasets_setup".
-- Suzuki K Poulose
8. Remove the disablement step in the reset node.
-- Suzuki K Poulose
9. Update the kernel version to 6.5 in the sysfs document.
-- Suzuki K Poulose
10. Remove the needless check in "tpdm_dsb_is_visible".
-- Suzuki K Poulose
11. Change the macro to mask the mode of DSB TPDM.
-- Suzuki K Poulose
12. Add a check to make sure "sysfs_emit_at" calling will not
cause overflow.
-- Suzuki K Poulose
13. Change the macro to get "edge_ctrl" value.
-- Suzuki K Poulose
14. Remove the needless comments in the sysfs document.
-- Suzuki K Poulose
15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in
"dsb_msr_show".
-- Suzuki K Poulose
16. Update the check of MSR number in "dsb_msr_store".
-- Suzuki K Poulose
17. Write data to the MSR registers in the DSB TPDM enablement
function.
-- Suzuki K Poulose
Changes in V4:
1. Change the range of the property "qcom,dsb-element-size", and
change the type to enumeration.
-- Suzuki K Poulose, Krzysztof Kozlowski
2. Change dsb_esize from 32 bits to 8 bits.
-- Suzuki K Poulose
3. Update the function tpda_set_element_size since James has
updated the dependency series. Meanwhile, it will send out a
warning if it detects more than one TPDM from the same TPDA
input port.
-- Suzuki K Poulose
4. Add a source_sub_type for TPDM to distinguish TPDM from
the other coresight source.
-- Suzuki K Poulose
5. Return error if the element size is not configured on
devicetree in TPDA enablement.
-- Suzuki K Poulose
6. Move memory allocation from "tpdm_init_datasets" to
"tpdm_datasets_setup". Rename "tpdm_init_datasets" as
"tpdm_reset_datasets".
-- Suzuki K Poulose
7. Replace "coresight_disable" with "coresight_disable_source"
to disable the TPDM in resetting.
-- Suzuki K Poulose
8. Make sure "drvdata" is not NULL pointer before using it.
-- Suzuki K Poulose
9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since
cycle accurate mode is not supported on the current targets.
It is replaced by test mode.
10. Document the value of "dsb_mode".
-- Suzuki K Poulose
11. Macros are used to replace the formulas on dsb edge control
nodes.
-- Suzuki K Poulose
12. Document the values of "dsb_trig_patt_val" and
"dsb_trig_patt_mask".
-- Suzuki K Poulose
13. Combine two pattern related loops to one. And move DSB TIER
register configurations to the new function "set_dsb_tier".
-- Suzuki K Poulose
14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num".
-- Suzuki K Poulose, Krzysztof Kozlowski
Changes in V3:
1. Move the property "qcom,dsb-element-size" to TPDM
devicetree and update the TPDM yaml file for this item.
-- Suzuki K Poulose
2. Add the error message when the DSB element size is not set to
32-bit or 64-bit. -- Suzuki K Poulose
3. Add more information to the comments of patch #3
-- Suzuki K Poulose
4. Combine the value updates to the TPDM_DSB_CR for TPDM.
-- Suzuki K Poulose
5. Remove the function "tpdm_datasets_alloc", and fold its code
to a new function "tpdm_init_datasets". It will complete the
initialization of TPDM. -- Suzuki K Poulose
6. Change the method of qualifying input values.
-- Suzuki K Poulose
7. Add the documentation of the new sysfs handles.
-- Suzuki K Poulose
8. Provide the separate handles for the "mode bits".
-- Suzuki K Poulose
Changes in V2:
1. Change the name of the property "qcom,dsb-elem-size" to
"qcom,dsb-element-size" -- Suzuki K Poulose
2. Update the TPDA yaml file for the item "qcom,dsb-elem-size".
-- Krzysztof Kozlowski
3. Add the full name of DSB in the description of the item
"qcom,dsb-elem-size". -- Rob Herring
Changes in V1:
1. Change the definition of the property "qcom,dsb-elem-size" from
"uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski
2. Add the full name of DSB. -- Rob Herring
3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose
4. Divide the function "tpdm_datasets_alloc" into two functions,
"tpdm_datasets_setup" and "tpdm_datasets_alloc".
5. Detecte the input string with the conventional semantics automatically,
and constrain the size of the input value. -- Suzuki K Poulose
6. Use the hook function "is_visible()" to hide the DSB related knobs if
the data sets are missing. -- Suzuki K Poulose
7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values.
-- Suzuki K Poulose
8. Update the definition of the macros in TPDM driver.
9. Update the comments of the values for the nodes which are for DSB
element creation and onfigure pattern match output. -- Suzuki K Poulose
10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose
Tao Zhang (13):
coresight-tpdm: Remove the unnecessary lock
dt-bindings: arm: Add support for DSB element size
coresight-tpdm: Introduce TPDM subtype to TPDM driver
coresight-tpda: Add DSB dataset support
coresight-tpdm: Initialize DSB subunit configuration
coresight-tpdm: Add reset node to TPDM node
coresight-tpdm: Add nodes to set trigger timestamp and type
coresight-tpdm: Add node to set dsb programming mode
coresight-tpdm: Add nodes for dsb edge control
coresight-tpdm: Add nodes to configure pattern match output
coresight-tpdm: Add nodes for timestamp request
dt-bindings: arm: Add support for DSB MSR register
coresight-tpdm: Add nodes for dsb msr support
.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 159 +++++
.../bindings/arm/qcom,coresight-tpdm.yaml | 20 +
drivers/hwtracing/coresight/coresight-core.c | 3 +
drivers/hwtracing/coresight/coresight-tpda.c | 126 +++-
drivers/hwtracing/coresight/coresight-tpda.h | 2 +
drivers/hwtracing/coresight/coresight-tpdm.c | 682 ++++++++++++++++++++-
drivers/hwtracing/coresight/coresight-tpdm.h | 165 +++++
include/linux/coresight.h | 1 +
8 files changed, 1136 insertions(+), 22 deletions(-)
--
2.7.4
FEAT_TRF is a Coresight feature that allows trace capture to be
completely filtered at different exception levels, unlike the existing
TRCVICTLR controls which may still emit target addresses of branches,
even if the following trace is filtered.
Without FEAT_TRF, it was possible to start a trace session on a host and
also collect trace from the guest as TRCVICTLR was never programmed to
exclude guests (and it could still emit target addresses even if it
was). Now when FEAT_TRF is present, because we don't write to
TRFCR_EL1, guest trace will be completely disabled.
This change fixes this issue, and also adds the ability to control it
with the Perf exclude_host and exclude_guest flags.
The first commit moves the register to sysreg because I add the EL12
version in the second commit.
The test results have some single spurious EL2 addresses, but I don't
think this is an issue with this patchset because it happens in the
host-userspace case which maintains the existing programming of
TRFCR. It's likely an issue with the model but I will follow it up
separately.
The corresponding change for nVHE is here [1]. The nVHE behaviour is
is reversed, currently guest trace is always generated because the host
already writes to TRFCR_EL1. This is the same both with and without
FEAT_TRF.
[1]: https://lore.kernel.org/kvmarm/20230804101317.460697-1-james.clark@arm.com/
---
Changes since v2:
* E0TRE -> E0HTRE in TRFCR_EL2 to match Arm ARM
* Add missing USE_TRFCR_EL1_TS enum value
Changes since v1:
* Split new sysreg definitions into TRFCR_EL2 and TRFCR_ELx so that
TRFCR_ELx doesn't include CX which TRFCR_EL1 doesn't have.
* Mask out TS and CX before writing to TRFCR_EL1 because it doesn't
have CX and TS has no effect.
* Expand cover letter
James Clark (2):
arm64/sysreg: Move TRFCR definitions to sysreg
coresight: Allow guests to be traced when FEAT_TRF and VHE are present
arch/arm64/include/asm/sysreg.h | 12 -----
arch/arm64/tools/sysreg | 41 +++++++++++++++
.../coresight/coresight-etm4x-core.c | 51 ++++++++++++++++---
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
drivers/hwtracing/coresight/coresight-priv.h | 3 ++
5 files changed, 90 insertions(+), 19 deletions(-)
--
2.34.1
This patch series is to improve timestamp handling in per-thread mode.
The current code doesn't validate timestamp and always return success for
per-thread mode, for a sane implementation, the first patch is to allow
validation timestamp tracing in per-thread mode.
The second patch is to respect timestamp option "--timestamp" or "-T",
when users set this option, the tool will automatically enable hardware
timestamp tracing in Arm CoreSight.
Leo Yan (2):
perf cs-etm: Validate timestamp tracing in per-thread mode
perf cs-etm: Respect timestamp option
tools/perf/arch/arm/util/cs-etm.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
--
2.34.1