CoreSight September 2023

coresight@lists.linaro.org

10 participants
39 discussions

[PATCH] coresight: tmc-etr: Disable warnings for allocation failures

by Suzuki K Poulose

Running the following command on Juno triggers the warning: $ perf record -e cs_etm// -m ,128M ... ------------[ cut here ]------------ WARNING: CPU: 1 PID: 412 at mm/page_alloc.c:4453 __alloc_pages+0x334/0x1420 CPU: 1 PID: 412 Comm: perf Not tainted 6.5.0-rc3+ #181 Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Feb 1 2019 pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __alloc_pages+0x334/0x1420 lr : dma_common_alloc_pages+0x108/0x138 sp : ffffffc087fb7440 x29: ffffffc087fb7440 x28: 0000000000000000 x27: ffffffc07e48fba0 x26: 0000000000000001 x25: 000000000000000f x24: ffffffc081f24880 x23: 0000000000000cc0 x22: ffffff88012b6f08 x21: 0000000008000000 x20: ffffff8801433000 x19: 0000000000000000 x18: 0000000000000000 x17: ffffffc080316e5c x16: ffffffc07e46406c x15: ffffffc0803af580 x14: ffffffc08036b460 x13: ffffffc080025cbc x12: ffffffb8108c3fc4 x11: 1ffffff8108c3fc3 x10: 1ffffff810ff6eac x9 : 00000000f204f204 x8 : 000000000000f204 x7 : 00000000f2f2f2f2 x6 : 00000000f3f3f3f3 x5 : 0000000000000001 x4 : 0000000000000000 x3 : 0000000000000000 x2 : 0000000000000cc0 x1 : 0000000000000000 x0 : ffffffc085333000 Call trace: __alloc_pages+0x334/0x1420 dma_common_alloc_pages+0x108/0x138 __dma_alloc_pages+0xf4/0x108 dma_alloc_pages+0x18/0x30 tmc_etr_alloc_flat_buf+0xa0/0x190 [coresight_tmc] tmc_alloc_etr_buf.constprop.0+0x124/0x298 [coresight_tmc] alloc_etr_buf.constprop.0.isra.0+0x88/0xc8 [coresight_tmc] tmc_alloc_etr_buffer+0x164/0x2f0 [coresight_tmc] etm_setup_aux+0x32c/0x520 [coresight] rb_alloc_aux+0x29c/0x3f8 perf_mmap+0x59c/0xce0 mmap_region+0x340/0x10e0 do_mmap+0x48c/0x580 vm_mmap_pgoff+0x160/0x248 ksys_mmap_pgoff+0x1e8/0x278 __arm64_sys_mmap+0x8c/0xb8 With the flat mode, we only attempt to allocate large memory if there is an IOMMU connected to the ETR. If the allocation fails, we always have a fallback path and return an error if nothing else worked. So, suppress the warning for flat mode allocations. Cc: Mike Leach <mike.leach(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 66dc5f97a009..c8df8719f6a0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -610,7 +610,8 @@ static int tmc_etr_alloc_flat_buf(struct tmc_drvdata *drvdata, flat_buf->vaddr = dma_alloc_noncoherent(real_dev, etr_buf->size, &flat_buf->daddr, - DMA_FROM_DEVICE, GFP_KERNEL); + DMA_FROM_DEVICE, + GFP_KERNEL | __GFP_NOWARN); if (!flat_buf->vaddr) { kfree(flat_buf); return -ENOMEM; -- 2.34.1

1 year

[PATCH] coresight: Fix run time warnings while reusing ETR buffer

by Linu Cherian

Fix the below warning by avoding calls to tmc_etr_enable_hw, if we are reusing the ETR buffer for multiple sources in sysfs mode. echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink echo 1 > /sys/bus/coresight/devices/ete1/enable_source echo 1 > /sys/bus/coresight/devices/ete2/enable_source [ 166.918290] ------------[ cut here ]------------ [ 166.922905] WARNING: CPU: 4 PID: 2288 at drivers/hwtracing/coresight/coresight-tmc-etr.c:1037 tmc_etr_enable_hw+0xb0/0xc8 [ 166.933862] Modules linked in: [ 166.936911] CPU: 4 PID: 2288 Comm: bash Not tainted 6.5.0-rc7 #132 [ 166.943084] Hardware name: Marvell CN106XX board (DT) [ 166.948127] pstate: 834000c9 (Nzcv daIF +PAN -UAO +TCO +DIT -SSBS BTYPE=--) [ 166.955083] pc : tmc_etr_enable_hw+0xb0/0xc8 [ 166.959345] lr : tmc_enable_etr_sink+0x134/0x210 snip.. 167.038545] Call trace: [ 167.040982] tmc_etr_enable_hw+0xb0/0xc8 [ 167.044897] tmc_enable_etr_sink+0x134/0x210 [ 167.049160] coresight_enable_path+0x160/0x278 [ 167.053596] coresight_enable+0xd4/0x298 [ 167.057510] enable_source_store+0x54/0xa0 [ 167.061598] dev_attr_store+0x20/0x40 [ 167.065254] sysfs_kf_write+0x4c/0x68 [ 167.068909] kernfs_fop_write_iter+0x128/0x200 [ 167.073345] vfs_write+0x1ac/0x2f8 [ 167.076739] ksys_write+0x74/0x110 [ 167.080132] __arm64_sys_write+0x24/0x38 [ 167.084045] invoke_syscall.constprop.0+0x58/0xf8 [ 167.088744] do_el0_svc+0x60/0x160 [ 167.092137] el0_svc+0x40/0x170 [ 167.095273] el0t_64_sync_handler+0x100/0x130 [ 167.099621] el0t_64_sync+0x190/0x198 [ 167.103277] ---[ end trace 0000000000000000 ]--- -bash: echo: write error: Device or resource busy Fixes: 296b01fd106e ("coresight: Refactor out buffer allocation function for ETR") Signed-off-by: Linu Cherian <lcherian(a)marvell.com> --- .../hwtracing/coresight/coresight-tmc-etr.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 766325de0e29..6a79c4dc09f2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1172,16 +1172,6 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) goto out; } - /* - * In sysFS mode we can have multiple writers per sink. Since this - * sink is already enabled no memory is needed and the HW need not be - * touched, even if the buffer size has changed. - */ - if (drvdata->mode == CS_MODE_SYSFS) { - atomic_inc(&csdev->refcnt); - goto out; - } - /* * If we don't have a buffer or it doesn't match the requested size, * use the buffer allocated above. Otherwise reuse the existing buffer. @@ -1203,7 +1193,7 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) { - int ret; + int ret = 0; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etr_buf *sysfs_buf = tmc_etr_get_sysfs_buffer(csdev); @@ -1212,12 +1202,24 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) return PTR_ERR(sysfs_buf); spin_lock_irqsave(&drvdata->spinlock, flags); + + /* + * In sysFS mode we can have multiple writers per sink. Since this + * sink is already enabled no memory is needed and the HW need not be + * touched, even if the buffer size has changed. + */ + if (drvdata->mode == CS_MODE_SYSFS) { + atomic_inc(&csdev->refcnt); + goto out; + } + ret = tmc_etr_enable_hw(drvdata, sysfs_buf); if (!ret) { drvdata->mode = CS_MODE_SYSFS; atomic_inc(&csdev->refcnt); } +out: spin_unlock_irqrestore(&drvdata->spinlock, flags); if (!ret) -- 2.41.0

1 year

[PATCH v2 0/2] coresight: Allow guests to be traced when FEAT_TRF and VHE are present

by James Clark

FEAT_TRF is a Coresight feature that allows trace capture to be completely filtered at different exception levels, unlike the existing TRCVICTLR controls which may still emit target addresses of branches, even if the following trace is filtered. Without FEAT_TRF, it was possible to start a trace session on a host and also collect trace from the guest as TRCVICTLR was never programmed to exclude guests (and it could still emit target addresses even if it was). Now when FEAT_TRF is present, because we don't write to TRFCR_EL1, guest trace will be completely disabled. This change fixes this issue, and also adds the ability to control it with the Perf exclude_host and exclude_guest flags. The first commit moves the register to sysreg because I add the EL12 version in the second commit. The test results have some single spurious EL2 addresses, but I don't think this is an issue with this patchset because it happens in the host-userspace case which maintains the existing programming of TRFCR. It's likely an issue with the model but I will follow it up separately. The corresponding change for nVHE is here [1]. With nVHE the behaviour is reversed, currently guest trace is always generated because the host already writes to TRFCR_EL1. This is the same both with and without FEAT_TRF. [1]: https://lore.kernel.org/kvmarm/20230804101317.460697-1-james.clark@arm.com/ --- Changes since v1: * Split new sysreg definitions into TRFCR_EL2 and TRFCR_ELx so that TRFCR_ELx doesn't include CX which TRFCR_EL1 doesn't have. * Mask out TS and CX before writing to TRFCR_EL1 because it doesn't have CX and TS has no effect. * Expand cover letter James Clark (2): arm64/sysreg: Move TRFCR definitions to sysreg coresight: Allow guests to be traced when FEAT_TRF and VHE are present arch/arm64/include/asm/sysreg.h | 12 ----- arch/arm64/tools/sysreg | 40 +++++++++++++++ .../coresight/coresight-etm4x-core.c | 51 ++++++++++++++++--- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 3 ++ 5 files changed, 89 insertions(+), 19 deletions(-) -- 2.34.1

1 year

[PATCH] perf test: Update cs_etm testcase for Arm ETE

by Ruidong Tian

Add ETE as one of the supported device types in perf cs_etm testcase. Signed-off-by: Ruidong Tian <tianruidong(a)linux.alibaba.com> --- tools/perf/tests/shell/test_arm_coresight.sh | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/shell/test_arm_coresight.sh b/tools/perf/tests/shell/test_arm_coresight.sh index f1bf5621160f..fe78c4626e45 100755 --- a/tools/perf/tests/shell/test_arm_coresight.sh +++ b/tools/perf/tests/shell/test_arm_coresight.sh @@ -11,6 +11,19 @@ glb_err=0 +cs_etm_dev_name() { + cs_etm_path=$(find /sys/bus/event_source/devices/cs_etm/ -name cpu* -print -quit) + trcdevarch=$(cat ${cs_etm_path}/mgmt/trcdevarch) + archhver=$((($trcdevarch >> 12) & 0xf)) + archpart=$(($trcdevarch & 0xfff)) + + if [ $archhver -eq 5 -a "$(printf "0x%X\n" $archpart)" = "0xA13" ] ; then + echo "ete" + else + echo "etm" + fi +} + skip_if_no_cs_etm_event() { perf list | grep -q 'cs_etm//' && return 0 @@ -136,7 +149,7 @@ arm_cs_iterate_devices() { arm_cs_etm_traverse_path_test() { # Iterate for every ETM device - for dev in /sys/bus/coresight/devices/etm*; do + for dev in /sys/bus/coresight/devices/$(cs_etm_dev_name)*; do # Find the ETM device belonging to which CPU cpu=`cat $dev/cpu` -- 2.33.1

1 year, 1 month

[PATCH] perf cs-etm: Fix kernel timestamp handling

by Leo Yan

The timestamp can originate from two sources: the kernel timestamp, which is recorded in the event PERF_RECORD_AUX, and the Arm CoreSight hardware trace data. On some Arm platforms, CoreSight trace data fails to support timestamp tracing. This can be due to either a missed connection between the timer counter and Arm CoreSight or the absence of support for the virtual timestamp. If Arm CoreSight fails to support hardware timestamp tracing, we need to fall back on using the kernel timestamp. The current code can support both timestamp sources when synthesizing samples. However, the decoding flow only relies on the hardware timestamp. If the hardware timestamp is zero, it becomes impossible to decode the trace data. Consequently, in this case, the commands below won't output any samples: perf record -e cs_etm// --per-thread --timestamp -- ls perf script To fix this issue, this patch unifies the method of resolving time: 1) It renames cs_etm__resolve_sample_time() to the more general name cs_etm__resolve_time(); 2) It changes the function argument type from 'cs_etm_traceid_queue' to 'cs_etm_packet_queue'; 3) In the end, both the decoding flow and the assignment of timestamps to samples call cs_etm__resolve_time() to obtain timestamp. Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- tools/perf/util/cs-etm.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 9729d006550d..fa88e731933d 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -400,6 +400,17 @@ void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, etmq->pending_timestamp_chan_id = trace_chan_id; } +static u64 cs_etm__resolve_time(struct cs_etm_queue *etmq, + struct cs_etm_packet_queue *packet_queue) +{ + struct cs_etm_auxtrace *etm = etmq->etm; + + if (!etm->timeless_decoding && etm->has_virtual_ts) + return packet_queue->cs_timestamp; + else + return etm->latest_kernel_timestamp; +} + static u64 cs_etm__etmq_get_timestamp(struct cs_etm_queue *etmq, u8 *trace_chan_id) { @@ -419,8 +430,7 @@ static u64 cs_etm__etmq_get_timestamp(struct cs_etm_queue *etmq, /* Acknowledge pending status */ etmq->pending_timestamp_chan_id = 0; - /* See function cs_etm_decoder__do_{hard|soft}_timestamp() */ - return packet_queue->cs_timestamp; + return cs_etm__resolve_time(etmq, packet_queue); } static void cs_etm__clear_packet_queue(struct cs_etm_packet_queue *queue) @@ -1434,18 +1444,6 @@ u64 cs_etm__convert_sample_time(struct cs_etm_queue *etmq, u64 cs_timestamp) return cs_timestamp; } -static inline u64 cs_etm__resolve_sample_time(struct cs_etm_queue *etmq, - struct cs_etm_traceid_queue *tidq) -{ - struct cs_etm_auxtrace *etm = etmq->etm; - struct cs_etm_packet_queue *packet_queue = &tidq->packet_queue; - - if (!etm->timeless_decoding && etm->has_virtual_ts) - return packet_queue->cs_timestamp; - else - return etm->latest_kernel_timestamp; -} - static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, struct cs_etm_traceid_queue *tidq, u64 addr, u64 period) @@ -1454,13 +1452,14 @@ static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, struct cs_etm_auxtrace *etm = etmq->etm; union perf_event *event = tidq->event_buf; struct perf_sample sample = {.ip = 0,}; + struct cs_etm_packet_queue *packet_queue = &tidq->packet_queue; event->sample.header.type = PERF_RECORD_SAMPLE; event->sample.header.misc = cs_etm__cpu_mode(etmq, addr, tidq->el); event->sample.header.size = sizeof(struct perf_event_header); /* Set time field based on etm auxtrace config. */ - sample.time = cs_etm__resolve_sample_time(etmq, tidq); + sample.time = cs_etm__resolve_time(etmq, packet_queue); sample.ip = addr; sample.pid = thread__pid(tidq->thread); @@ -1505,6 +1504,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq, struct cs_etm_auxtrace *etm = etmq->etm; struct perf_sample sample = {.ip = 0,}; union perf_event *event = tidq->event_buf; + struct cs_etm_packet_queue *packet_queue = &tidq->packet_queue; struct dummy_branch_stack { u64 nr; u64 hw_idx; @@ -1520,7 +1520,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq, event->sample.header.size = sizeof(struct perf_event_header); /* Set time field based on etm auxtrace config. */ - sample.time = cs_etm__resolve_sample_time(etmq, tidq); + sample.time = cs_etm__resolve_time(etmq, packet_queue); sample.ip = ip; sample.pid = thread__pid(tidq->prev_packet_thread); -- 2.34.1

1 year, 1 month

[PATCH] coresight: etm4x: Add ACPI id for THEAD YiTian SOC

by Ruidong Tian

From: Jay Chen <jkchen(a)linux.alibaba.com> Add support for detcting ETE device of THEAD YiTian SOC. Signed-off-by: Jay Chen <jkchen(a)linux.alibaba.com> Signed-off-by: Ruidong Tian <tianruidong(a)linux.alibaba.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 77b0271ce6eb..329bb554b168 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2351,6 +2351,7 @@ static const struct of_device_id etm4_sysreg_match[] = { #ifdef CONFIG_ACPI static const struct acpi_device_id etm4x_acpi_ids[] = { {"ARMHC500", 0}, /* ARM CoreSight ETM4x */ + {"BABA6000", 0 }, /* THEAD CoreSight ETE */ {} }; MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids); -- 2.33.1

1 year, 1 month

RE: [EXT] Re: [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property

by Linu Cherian

Hi Rob, > -----Original Message----- > From: Rob Herring <robh(a)kernel.org> > Sent: Monday, September 4, 2023 11:53 AM > To: Linu Cherian <lcherian(a)marvell.com> > Cc: linux-arm-kernel(a)lists.infradead.org; mike.leach(a)linaro.org; Sunil > Kovvuri Goutham <sgoutham(a)marvell.com>; james.clark(a)arm.com; > leo.yan(a)linaro.org; linux-kernel(a)vger.kernel.org; > krzysztof.kozlowski+dt(a)linaro.org; George Cherian > <gcherian(a)marvell.com>; suzuki.poulose(a)arm.com; > coresight(a)lists.linaro.org; devicetree(a)vger.kernel.org; > conor+dt(a)kernel.org; robh+dt(a)kernel.org > Subject: [EXT] Re: [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add > "memory-region" property > > External Email > > ---------------------------------------------------------------------- > > On Mon, 04 Sep 2023 10:35:41 +0530, Linu Cherian wrote: > > memory-region 0: Reserved trace buffer memory > > > > TMC ETR: When available, use this reserved memory region for > > trace data capture. Same region is used for trace data > > retention after a panic or watchdog reset. > > > > TMC ETF: When available, use this reserved memory region for > > trace data retention synced from internal SRAM after a panic or > > watchdog reset. > > > > memory-region 1: Reserved meta data memory > > > > TMC ETR, ETF: When available, use this memory for register > > snapshot retention synced from hardware registers after a panic > > or watchdog reset. > > > > Signed-off-by: Linu Cherian <lcherian(a)marvell.com> > > --- > > .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 13 > > +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m > dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: > [error] syntax error: expected <block end>, but found '<block mapping > start>' (syntax) > ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:105:5: > [warning] wrong indentation: expected 5 but found 4 (indentation) > > dtschema/dtc warnings/errors: > make[2]: *** Deleting file > 'Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts' > Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: did > not find expected key > make[2]: *** [Documentation/devicetree/bindings/Makefile:26: > Documentation/devicetree/bindings/arm/arm,coresight-tmc.example.dts] > Error 1 > make[2]: *** Waiting for unfinished jobs.... > ./Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml:104:4: > did not find expected key > /builds/robherring/dt-review- > ci/linux/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml: > ignoring, error parsing file > make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1500: > dt_binding_check] Error 2 > make: *** [Makefile:234: __sub-make] Error 2 > > doc reference errors (make refcheckdocs): > > See https://urldefense.proofpoint.com/v2/url?u=https- > 3A__patchwork.ozlabs.org_project_devicetree- > 2Dbindings_patch_20230904050548.28047-2D2-2Dlcherian- > 40marvell.com&d=DwIDaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=DI9kird_6lFtBC > VoGa5ogk3dJwsUlHLjLlgu0r46iU4&m=_ay- > WtrQlhIwxRafvVeVQHuS8jVWvIzZWMmn3Kp2yAVpxITz- > rjWiL4cMybMomHi&s=zvUJitULz2sVzal1I78gUQ3sBBTSAZmwDziKSNJbxwM& > e= > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above error(s), > then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your > schema. Ack. Will fix this in next version.

1 year, 1 month

[PATCH v8 00/13] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l drwxr-xr-x 2 root root 0 Jan 1 00:00 connections drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type -rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source --w------- 1 root root 4096 Jan 1 00:00 integration_test drwxr-xr-x 2 root root 0 Jan 1 00:00 power --w------- 1 root root 4096 Jan 1 00:02 reset_dataset lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5 echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2 echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source TPDM_DSB commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v8 https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v8 Changes in V8: 1. Refine the function "tpda_set_element_size" and rename it to "tpda_get_element_size" in the patch#4. -- Suzuki K Poulose 2. Refine the functioin "tpda_enable_port" in the patch#4. -- Suzuki K Poulose 3. Write a helper to check if the TPDM has DSB dataset in the patch#5. -- Suzuki K Poulose 4. Move the function "tpdm_reset_datasets" to "datasets_setup" to call in the patch#5. -- Suzuki K Poulose 5. Refine the comment of DSB in "tpdm_drvdata" in the patch#5. -- Suzuki K Poulose 6. Refine the comments in the documents for this patch series. -- Suzuki K Poulose 7. Adjust the code alignment in this patch series. -- Suzuki K Poulose 8. Combine the mode related functions to one in the patch#8. -- Suzuki K Poulose 9. Refine the R/W functions of "dsb_mode" in the patch#8. -- Suzuki K Poulose 10. Adjust the macros of mode in the TPDM header file in the patch#8. -- Suzuki K Poulose 11. Remove the unused code and fix the warnings in compiling for the patch#9. -- kernel test robot 12. Use the following sysfs nodes to read/set edge control related value in the patch#9. dsb_edge/ \- ctrl_idx -> Set the index number \- ctrl_val -> Set the edge control value \- ctrl_mask -> Set the edge control mask \- edcr0 ... edcr15 -> Read the edge control value \- edcmr0 ... edcmr7 -> Read the edge control mask -- Suzuki K Poulose 13. Use the following sysfs nodes to read/set DSB trigger pattern value and mask in the patch#10. dsb_trig_patt/ \- xpr0 ... xpr15 -> (RW) Set/Get the value \- xpmr0 ... xpmr7 -> (RW) Set/Get the mask -- Suzuki K Poulose 14. Use the following sysfs nodes to read/set DSB pattern value and mask in the patch#11. dsb_patt/ \- tpr0 ... tpr15 -> (RW) Set/Get the value \- tpmr0 ... tpmr7 -> (RW) Set/Get the mask -- Suzuki K Poulose 15. Add "Acked-by" tag to the patch#12. -- Rob Herring 16. Use the following sysfs nodes to read/set DSB MSR in the patch#13. dsb_msr/ \- msr0 ... msr31 -> (RW) Set/Get the value -- Suzuki K Poulose 17. Create the maximal number of DSB MSR sysfs nodes if the TPDM supports DSB MSR. Write the values set by user space to the DSB MSR according to the number of MSR supported by the TPDM. -- Suzuki K Poulose Changes in V7: 1. Since the "One value" limitation on SysFs file usage, add the nodes to read/write the index number for configuring the DSB TPDM. The following index number nodes are added. "dsb_edge_ctrl_idx" in the patch #9 "dsb_trig_patt_idx" in the patch #10 "dsb_patt_idx" in the patch #11 "dsb_msr_idx" in the patch #13 -- Suzuki K Poulose Changes in V6: 1. Align the code to fix the styling issue. -- Suzuki K Poulose Changes in V5: 1. Correct data type for DSB element size in dt-bindings patch. 2. Refine the recursive function "tpda_set_element_size". -- Suzuki K Poulose 3. Get return value of the function "__tpda_enable" in "tpda_enable". -- Suzuki K Poulose 4. Refine the comments on "dsb_esize". -- Suzuki K Poulose 5. Split the chage that introduce the subtype "SUBTYPE_SOURCE_TPDM" to Coresight driver. -- Suzuki K Poulose 6. Inline the trigger type setting to "tpdm_enable_dsb" simply. -- Suzuki K Poulose 7. Split the change that remove the needless CS_{UN,}LOCK in the function "tpdm_datasets_setup". -- Suzuki K Poulose 8. Remove the disablement step in the reset node. -- Suzuki K Poulose 9. Update the kernel version to 6.5 in the sysfs document. -- Suzuki K Poulose 10. Remove the needless check in "tpdm_dsb_is_visible". -- Suzuki K Poulose 11. Change the macro to mask the mode of DSB TPDM. -- Suzuki K Poulose 12. Add a check to make sure "sysfs_emit_at" calling will not cause overflow. -- Suzuki K Poulose 13. Change the macro to get "edge_ctrl" value. -- Suzuki K Poulose 14. Remove the needless comments in the sysfs document. -- Suzuki K Poulose 15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in "dsb_msr_show". -- Suzuki K Poulose 16. Update the check of MSR number in "dsb_msr_store". -- Suzuki K Poulose 17. Write data to the MSR registers in the DSB TPDM enablement function. -- Suzuki K Poulose Changes in V4: 1. Change the range of the property "qcom,dsb-element-size", and change the type to enumeration. -- Suzuki K Poulose, Krzysztof Kozlowski 2. Change dsb_esize from 32 bits to 8 bits. -- Suzuki K Poulose 3. Update the function tpda_set_element_size since James has updated the dependency series. Meanwhile, it will send out a warning if it detects more than one TPDM from the same TPDA input port. -- Suzuki K Poulose 4. Add a source_sub_type for TPDM to distinguish TPDM from the other coresight source. -- Suzuki K Poulose 5. Return error if the element size is not configured on devicetree in TPDA enablement. -- Suzuki K Poulose 6. Move memory allocation from "tpdm_init_datasets" to "tpdm_datasets_setup". Rename "tpdm_init_datasets" as "tpdm_reset_datasets". -- Suzuki K Poulose 7. Replace "coresight_disable" with "coresight_disable_source" to disable the TPDM in resetting. -- Suzuki K Poulose 8. Make sure "drvdata" is not NULL pointer before using it. -- Suzuki K Poulose 9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since cycle accurate mode is not supported on the current targets. It is replaced by test mode. 10. Document the value of "dsb_mode". -- Suzuki K Poulose 11. Macros are used to replace the formulas on dsb edge control nodes. -- Suzuki K Poulose 12. Document the values of "dsb_trig_patt_val" and "dsb_trig_patt_mask". -- Suzuki K Poulose 13. Combine two pattern related loops to one. And move DSB TIER register configurations to the new function "set_dsb_tier". -- Suzuki K Poulose 14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num". -- Suzuki K Poulose, Krzysztof Kozlowski Changes in V3: 1. Move the property "qcom,dsb-element-size" to TPDM devicetree and update the TPDM yaml file for this item. -- Suzuki K Poulose 2. Add the error message when the DSB element size is not set to 32-bit or 64-bit. -- Suzuki K Poulose 3. Add more information to the comments of patch #3 -- Suzuki K Poulose 4. Combine the value updates to the TPDM_DSB_CR for TPDM. -- Suzuki K Poulose 5. Remove the function "tpdm_datasets_alloc", and fold its code to a new function "tpdm_init_datasets". It will complete the initialization of TPDM. -- Suzuki K Poulose 6. Change the method of qualifying input values. -- Suzuki K Poulose 7. Add the documentation of the new sysfs handles. -- Suzuki K Poulose 8. Provide the separate handles for the "mode bits". -- Suzuki K Poulose Changes in V2: 1. Change the name of the property "qcom,dsb-elem-size" to "qcom,dsb-element-size" -- Suzuki K Poulose 2. Update the TPDA yaml file for the item "qcom,dsb-elem-size". -- Krzysztof Kozlowski 3. Add the full name of DSB in the description of the item "qcom,dsb-elem-size". -- Rob Herring Changes in V1: 1. Change the definition of the property "qcom,dsb-elem-size" from "uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski 2. Add the full name of DSB. -- Rob Herring 3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose 4. Divide the function "tpdm_datasets_alloc" into two functions, "tpdm_datasets_setup" and "tpdm_datasets_alloc". 5. Detecte the input string with the conventional semantics automatically, and constrain the size of the input value. -- Suzuki K Poulose 6. Use the hook function "is_visible()" to hide the DSB related knobs if the data sets are missing. -- Suzuki K Poulose 7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values. -- Suzuki K Poulose 8. Update the definition of the macros in TPDM driver. 9. Update the comments of the values for the nodes which are for DSB element creation and onfigure pattern match output. -- Suzuki K Poulose 10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 159 +++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + drivers/hwtracing/coresight/coresight-core.c | 3 + drivers/hwtracing/coresight/coresight-tpda.c | 126 +++- drivers/hwtracing/coresight/coresight-tpda.h | 2 + drivers/hwtracing/coresight/coresight-tpdm.c | 682 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 165 +++++ include/linux/coresight.h | 1 + 8 files changed, 1136 insertions(+), 22 deletions(-) -- 2.7.4

1 year, 1 month

[PATCH v3 0/2] coresight: Allow guests to be traced when FEAT_TRF and VHE are present

by James Clark

FEAT_TRF is a Coresight feature that allows trace capture to be completely filtered at different exception levels, unlike the existing TRCVICTLR controls which may still emit target addresses of branches, even if the following trace is filtered. Without FEAT_TRF, it was possible to start a trace session on a host and also collect trace from the guest as TRCVICTLR was never programmed to exclude guests (and it could still emit target addresses even if it was). Now when FEAT_TRF is present, because we don't write to TRFCR_EL1, guest trace will be completely disabled. This change fixes this issue, and also adds the ability to control it with the Perf exclude_host and exclude_guest flags. The first commit moves the register to sysreg because I add the EL12 version in the second commit. The test results have some single spurious EL2 addresses, but I don't think this is an issue with this patchset because it happens in the host-userspace case which maintains the existing programming of TRFCR. It's likely an issue with the model but I will follow it up separately. The corresponding change for nVHE is here [1]. The nVHE behaviour is is reversed, currently guest trace is always generated because the host already writes to TRFCR_EL1. This is the same both with and without FEAT_TRF. [1]: https://lore.kernel.org/kvmarm/20230804101317.460697-1-james.clark@arm.com/ --- Changes since v2: * E0TRE -> E0HTRE in TRFCR_EL2 to match Arm ARM * Add missing USE_TRFCR_EL1_TS enum value Changes since v1: * Split new sysreg definitions into TRFCR_EL2 and TRFCR_ELx so that TRFCR_ELx doesn't include CX which TRFCR_EL1 doesn't have. * Mask out TS and CX before writing to TRFCR_EL1 because it doesn't have CX and TS has no effect. * Expand cover letter James Clark (2): arm64/sysreg: Move TRFCR definitions to sysreg coresight: Allow guests to be traced when FEAT_TRF and VHE are present arch/arm64/include/asm/sysreg.h | 12 ----- arch/arm64/tools/sysreg | 41 +++++++++++++++ .../coresight/coresight-etm4x-core.c | 51 ++++++++++++++++--- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 3 ++ 5 files changed, 90 insertions(+), 19 deletions(-) -- 2.34.1

1 year, 1 month

[PATCH v1 0/2] perf cs-etm: Improve timestamp tracing

by Leo Yan

This patch series is to improve timestamp handling in per-thread mode. The current code doesn't validate timestamp and always return success for per-thread mode, for a sane implementation, the first patch is to allow validation timestamp tracing in per-thread mode. The second patch is to respect timestamp option "--timestamp" or "-T", when users set this option, the tool will automatically enable hardware timestamp tracing in Arm CoreSight. Leo Yan (2): perf cs-etm: Validate timestamp tracing in per-thread mode perf cs-etm: Respect timestamp option tools/perf/arch/arm/util/cs-etm.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) -- 2.34.1

1 year, 1 month

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CoreSight September 2023