CoreSight November 2024

coresight@lists.linaro.org

7 participants
31 discussions

Re: [PATCH] hwtracing: Switch back to struct platform_driver::remove()

by Suzuki K Poulose

Hi On 11/11/2024 14:12, Alexander Shishkin wrote: > Uwe Kleine-König <u.kleine-koenig(a)baylibre.com> writes: > >> After commit 0edb555a65d1 ("platform: Make platform_driver::remove() >> return void") .remove() is (again) the right callback to implement for >> platform drivers. >> >> Convert all platform drivers below drivers/hwtracing to use .remove(), >> with the eventual goal to drop struct platform_driver::remove_new(). As >> .remove() and .remove_new() have the same prototypes, conversion is done >> by just changing the structure member name in the driver initializer. >> >> Also adapt some whitespace to make indention consistent. >> >> Signed-off-by: Uwe Kleine-König <u.kleine-koenig(a)baylibre.com> > > Acked-by: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> > >> --- >> Hello, >> >> I did a single patch for all of drivers/hwtracing. While I usually >> prefer to do one logical change per patch, this seems to be >> overengineering here as the individual changes are really trivial and >> shouldn't be much in the way for stable backports. But I'll happily >> split the patch if you prefer it split. Maybe split for coresight vs. >> intel_th? Also if you object the indentation stuff, I can rework that. > > I'm fine with it as is. > >> This is based on today's next, if conflicts arise when you apply it at >> some later time and don't want to resolve them, feel free to just drop >> the changes to the conflicting files. I'll notice and followup at a >> later time then. Or ask me for a fixed resend. (Having said that, I >> recommend b4 am -3 + git am -3 which should resolve most conflicts just >> fine.) > > Does anybody want to pick this up or should I? I'm fine either way, but > if there are any conflicts they won't be from my end of things, so it > might make sense to take it via the coresight path. I am happy to take them via coresight tree and queue them for v6.14 Suzuki > > Thanks, > -- > Alex

4 days, 16 hours

[PATCH v7 0/9] coresight: syscfg: Add configuration table load

by Mike Leach

This set extends the configuration management support to allow loading and unloading of configurations as structured tables. The existing coresight configuration configfs API is additionally extended to use this table functionality to load and unload configuration tables as binary files. This allows coresight configurations to be loaded at runtime, and independently of kernel version, without the requirement to re-compile as built in kernel modules. Loading configurations in this way provides a method for atomically programming the trace control elements (e.g. filters and triggers) of multiple connected CoreSight components as a single system for a trace session when selected on the command line both when running trace via perf or running trace via sysfs. All configuration are validated at load time as being compatible with the CoreSight system in use. Additional load and unload attributes are provided in the /config/cs-syscfg subsytem base group to implement the load functionality. Routines to generate configuration tables are supplied in ./tools/coresight. Example generator and reader applications are provided. Tools may be cross compiled or built for use on host system. Documentation is updated to describe feature usage. Changes since v6: 1) Rebased to coresight/next - 6.12-rc4 2) Adjusted patches to split the load/unload API from the configfs attribute declarations 3) As unload order is strictly enforced to ensure dependencies are not broken, unload is now a simple write to attribute to automatically unload the last loaded configuration without need for name of configuration. Changes since v5: 1) Possible memory leak removed. Reported-by: kernel test robot. Reported-by: Dan Carpenter 2) Reuse mechanism for reader code revised. (Christoph) 3) Unload mechnism now by name in standard attribute, rather than entire file 4) Mechanism to check last loaded configuration can be unloaded. 5) Documentation updates. Changes since v4: 1) Update coresight/next - 6.1-rc3 2) Update to lockdep fixes to avoid read lock race in configfs. Changes since v3: 1) Rebase & tested on coresight/next - 5.19-rc3 - which includes the fix patch for earlier configfs works. 2) Lockdep investigations resulted in re-design of some of the code accessing configfs. 3) moved load and unload attributes to root of cs-syscfg. (Mathieu) 4) Additional minor fixes suggested by Mathieu. 5) Memory for configfs loaded and unloaded configurations is now explicitly freed. 6) LOCKDEP nesting fix for configfs base code (fs/configfs/dir.c) Changes since v2: 1) Rebased & tested on coresight/next - 5.18-rc2 2) Moved coresight config generator and reader programs from samples to tools/coresight. Docs updated to match. (suggested by Mathieu) 3) userspace builds now use userspace headers from tools/... 4) Other minor fixes from Mathieu's review. Changes since v1: 1) Rebased to coresight/next - 5.16-rc1 with previous coresight config set applied. 2) Makefile.host fixed to default to all target. Mike Leach (9): coresight: config: Add configuration table processing funtionality coresight: configfs: Update memory allocation / free for configfs elements coresight: config: API to dynamically load / unload config tables coresight: configfs: Add static type for config attributes coresight: configfs: Add attributes for unload operations coresight: configfs: Add attribute to load a configuration table coresight: config: extract shared structures to common header file coresight: tools: Add configuration table test tools Documentation: coresight: Docs for configuration table load .../trace/coresight/coresight-config.rst | 287 ++++++++- MAINTAINERS | 1 + drivers/hwtracing/coresight/Makefile | 3 +- .../coresight/coresight-config-desc.h | 105 ++++ .../coresight/coresight-config-table.c | 431 +++++++++++++ .../coresight/coresight-config-table.h | 151 +++++ .../hwtracing/coresight/coresight-config.h | 98 +-- .../coresight/coresight-syscfg-configfs.c | 577 ++++++++++++++++-- .../hwtracing/coresight/coresight-syscfg.c | 103 +++- .../hwtracing/coresight/coresight-syscfg.h | 19 +- tools/coresight/Makefile | 56 ++ tools/coresight/coresight-cfg-bufw.c | 328 ++++++++++ tools/coresight/coresight-cfg-bufw.h | 26 + tools/coresight/coresight-cfg-example1.c | 62 ++ tools/coresight/coresight-cfg-example2.c | 95 +++ tools/coresight/coresight-cfg-examples.h | 25 + tools/coresight/coresight-cfg-file-gen.c | 58 ++ tools/coresight/coresight-cfg-file-gen.h | 17 + tools/coresight/coresight-cfg-file-read.c | 239 ++++++++ tools/coresight/coresight-config-uapi.h | 105 ++++ 20 files changed, 2644 insertions(+), 142 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-config-desc.h create mode 100644 drivers/hwtracing/coresight/coresight-config-table.c create mode 100644 drivers/hwtracing/coresight/coresight-config-table.h create mode 100644 tools/coresight/Makefile create mode 100644 tools/coresight/coresight-cfg-bufw.c create mode 100644 tools/coresight/coresight-cfg-bufw.h create mode 100644 tools/coresight/coresight-cfg-example1.c create mode 100644 tools/coresight/coresight-cfg-example2.c create mode 100644 tools/coresight/coresight-cfg-examples.h create mode 100644 tools/coresight/coresight-cfg-file-gen.c create mode 100644 tools/coresight/coresight-cfg-file-gen.h create mode 100644 tools/coresight/coresight-cfg-file-read.c create mode 100644 tools/coresight/coresight-config-uapi.h -- 2.25.1

3 weeks, 5 days

[PATCH v2 0/3] Add support to configure TPDM MCMB subunit

by Mao Jinlong

Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB subunit has the same number and usage of registers as CMB subunit. Just like the CMB subunit, the MCMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the MCMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports MCMB subunit. All sysfs files of CMB subunit TPDM are included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will have new sysfs files to select and enable the lane. Changes in V2: 1. Use tdpm_data->cmb instead of (tpdm_has_cmb_dataset(tpdm_data) || tpdm_has_mcmb_dataset(tpdm_data)) for cmb dataset support. 2. Embed mcmb_dataset struct into cmb struct. 3. Update the date and version in sysfs-bus-coresight-devices-tpdm Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM .../testing/sysfs-bus-coresight-devices-tpdm | 15 +++ drivers/hwtracing/coresight/coresight-tpda.c | 7 +- drivers/hwtracing/coresight/coresight-tpdm.c | 124 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 33 +++-- 4 files changed, 158 insertions(+), 21 deletions(-) -- 2.17.1

3 weeks, 6 days

[PATCH v1 0/2] Add Qualcomm extended CTI support

by Mao Jinlong

The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. QCOM extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Mao Jinlong (2): dt-bindings: arm: Add Qualcomm extended CTI coresight: cti: Add Qualcomm extended CTI support .../bindings/arm/arm,coresight-cti.yaml | 14 ++ .../hwtracing/coresight/coresight-cti-core.c | 75 +++++++---- .../coresight/coresight-cti-platform.c | 16 ++- .../hwtracing/coresight/coresight-cti-sysfs.c | 124 ++++++++++++++---- drivers/hwtracing/coresight/coresight-cti.h | 123 +++++++++++------ 5 files changed, 253 insertions(+), 99 deletions(-) -- 2.41.0

3 weeks, 6 days

[PATCH] selftests: arm coresight: sysfsmode testing

by Linu Cherian

Add sysfs mode selftest for ARM Coresight hardware tracer. Signed-off-by: Linu Cherian <lcherian(a)marvell.com> --- .../drivers/hwtracing/coresight/Makefile | 5 + .../hwtracing/coresight/sysfs_test_trace.sh | 144 ++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 tools/testing/selftests/drivers/hwtracing/coresight/Makefile create mode 100755 tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/Makefile b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile new file mode 100644 index 000000000000..7dc68ae1c0a9 --- /dev/null +++ b/tools/testing/selftests/drivers/hwtracing/coresight/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +TEST_PROGS = sysfs_test_trace.sh + +include ../../../lib.mk diff --git a/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh new file mode 100755 index 000000000000..0d6307fff1d2 --- /dev/null +++ b/tools/testing/selftests/drivers/hwtracing/coresight/sysfs_test_trace.sh @@ -0,0 +1,144 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2024 Marvell. + +# Test Arm CoreSight trace capture in sysfs mode +# Based on tools/perf/tests/shell/test_arm_coresight.sh + +glb_err=0 + +arm_cs_report() { + if [ $2 != 0 ]; then + echo "$1: FAIL" + glb_err=$2 + else + echo "$1: PASS" + fi +} + +is_device_sink() { + # If the node of "enable_sink" is existed under the device path, this + # means the device is a sink device. + + if [ -e "$1/enable_sink" ]; then + + return 0 + else + return 1 + fi +} + +# Configure sink for buffer mode +cfg_sink_buf_mode() { + sink_dev=$1 + mode=$2 + # Set buffer mode if supported + if [ -e "$sink_dev/buf_modes_available" ]; then + cat $sink_dev/buf_modes_available | grep -E -q $mode + if [ $? -eq 0 ]; then + echo $mode > $sink_dev/buf_mode_preferred + return 0 + fi + fi + + return 1 +} + +run_app() { + + taskset -c $1 dd if=/dev/urandom of=/dev/null bs=1M count=64 +} + +sysfs_trace() { + src_dev=$1 + sink_dev=$2 + cpu=$3 + + # Enable sink device + echo 1 > $sink_dev/enable_sink + # Enable source device + echo 1 > $src_dev/enable_source + + # Run app to be traced + run_app $cpu + + # Read back trace data + dd if=/dev/$sink_dev_name of=/tmp/tracedata + + # Verify if read is successful + err=$? + + # Disable source device + echo 0 > $src_dev/enable_source + + # Diskable sink device + echo 0 > $sink_dev/enable_sink + + arm_cs_report "CoreSight path testing (CPU$cpu -> $sink_dev_name)" $err +} + +try_sysfs_trace_resrv_buf() { + src_dev=$1 + sink_dev=$2 + cpu=$3 + + # Configure the resrved buffer mode if available + cfg_sink_buf_mode $sink_dev "resrv" + if [ $? -eq 0 ]; then + echo "Running sysfs trace with resrv buf mode" + sysfs_trace $src_dev $sink_dev $cpu + # Restore buffer mode + cfg_sink_buf_mode $sink_dev "auto" + if [ $? -eq 1 ]; then + echo "Failed to restore default buf mode" + fi + fi +} + +arm_cs_iterate_devices() { + src_dev=$1 + cpu=$3 + for cdev in $2/connections/out\:*; do + + # Skip testing if it's not a directory + ! [ -d $cdev ] && continue; + + # Read out its symbol link file name + sink_dev=`readlink -f $cdev` + + # Extract device name from path, e.g. + # sink_dev = '/sys/devices/platform/20010000.etf/tmc_etf0' + # `> sink_dev_name = 'tmc_etf0' + sink_dev_name=$(basename $sink_dev) + + if is_device_sink $sink_dev; then + # Run trace with resrv buf mode (if available) + try_sysfs_trace_resrv_buf $src_dev $sink_dev $cpu + + # Run the default mode + echo "Running sysfs trace with default settings" + sysfs_trace $src_dev $sink_dev $cpu + fi + + arm_cs_iterate_devices $src_dev $cdev $cpu + + done +} + +arm_cs_etm_traverse_path_test() { + # Iterate for every ETM device + for dev in /sys/bus/event_source/devices/cs_etm/cpu*; do + # Canonicalize the path + dev=`readlink -f $dev` + + # Find the ETM device belonging to which CPU + cpu=`cat $dev/cpu` + + # Use depth-first search (DFS) to iterate outputs + arm_cs_iterate_devices $dev $dev $cpu + done +} + +arm_cs_etm_traverse_path_test + +exit $glb_err -- 2.34.1

4 weeks

[PATCH v12 0/8] Coresight for Kernel panic and watchdog reset

by Linu Cherian

This patch series is rebased on coresight-next-v6.12.rc4 * Patches 1 & 2 adds support for allocation of trace buffer pages from reserved RAM * Patches 3 & 4 adds support for saving metadata at the time of kernel panic * Patch 5 adds support for reading trace data captured at the time of panic * Patches 6 & 7 adds support for disabling coresight blocks at the time of panic * Patch 8: Gives the full description about this feature as part of documentation V11 is posted here, https://lore.kernel.org/linux-arm-kernel/20241111124746.2210378-1-lcherian@… Changelog from v11: Convert all commands to literal code blocks, that was missed out in v11. No other code changes. Changelog from v10: * Converted all csdev_access_* to readl functions in tmc_panic_sync_* * Added "tmc" prefix for register snapshots in struct tmc_crash_metadata * Converted dev_info to dev_dbg in panic handlers * Converted dsb to dmb in panic handlers * Fixed marking metadata as invalid when a user is trying to use the reserved buffer. Earlier this was wrongly set at the time of reading reserved trace buffer. * Moved common validation checks to is_tmc_crashdata_valid and minor code rearrangements for efficiency * Got rid of sink specific prepare/unprepare invocations * Got rid of full from struct tmc_resrv_buf * While reading crashdata, size is now calculated from metdata instead of relying on reserved buffer size populated by dtb * Minor documenation fixes Changelog from v9: * Add common helper function of_tmc_get_reserved_resource_by_name for better code reuse * Reserved buffer validity and crashdata validity has been separated to avoid interdependence * New fields added to crash metadata: version, ffcr, ffsr, mode * Version checks added for metadata validation * Special file /dev/crash_tmc_xxx would be available only when crash metadata is valid * Removed READ_CRASHDATA mode meant for special casing crashdata reads. Instead, dedicated read function added for crashdata reads from reserved buffer which is common for both ETR and ETF sinks as well. * Documentation added to Documentation/tracing/coresight/panic.rst Changelog from v8: * Added missing exit path on error in __tmc_probe. * Few whitespace fixes, checkpatch fixes. * With perf sessions honouring stop_on_flush sysfs attribute, removed redundant variable stop_on_flush_en. Changelog from v7: * Fixed breakage on perf test -vvvv "arm coresight". No issues seen with and without "resrv" buffer mode * Moved the crashdev registration into a separate function. * Removed redundant variable in tmc_etr_setup_crashdata_buf * Avoided a redundant memcpy in tmc_panic_sync_etf. * Tested kernel panic with trace session started uisng perf. Please see the title "Perf based testing" below for details. For this, stop_on_flush sysfs attribute is taken into consideration while starting perf sessions as well. Changelog from v6: * Added special device files for reading crashdata, so that read_prevboot mode flag is removed. * Added new sysfs TMC device attribute, stop_on_flush. Stop on flush trigger event is disabled by default. User need to explicitly enable this from sysfs for panic stop to work. * Address parameter for panicstop ETM configuration is chosen as kernel "panic" address by default. * Added missing tmc_wait_for_tmcready during panic handling * Few other misc code rearrangements. Changelog from v5: * Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP * Fixed a memory leak while reading data from /dev/tmc_etrx in READ_PREVBOOT mode * Tested reading trace data from crashdump kernel Changelog from v4: * Device tree binding - Description is made more explicit on the usage of reserved memory region - Mismatch in memory region names in dts binding and driver fixed - Removed "mem" suffix from the memory region names * Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata", since it contains more than register snapshot. Related variables are named accordingly. * Rename struct tmc_drvdata members resrv_buf -> crash_tbuf metadata -> crash_mdata * Size field in metadata refers to RSZ register and hence indicates the size in 32 bit words. ETR metadata follows this convention, the same has been extended to ETF metadata as well. * Added crc32 for more robust metadata and tracedata validation. * Added/modified dev_dbg messages during metadata validation * Fixed a typo in patch 5 commit description Changelog from v3: * Converted the Coresight ETM driver change to a named configuration. RFC tag has been removed with this change. * Fixed yaml issues reported by "make dt_binding_check" * Added names for reserved memory regions 0 and 1 * Added prevalidation checks for metadata processing * Fixed a regression introduced in RFC v3 - TMC Status register was getting saved wrongly * Reverted memremap attribute changes from _WB to _WC to match with the dma map attributes * Introduced reserved buffer mode specific .sync op. This fixes a possible crash when reserved buffer mode was used in normal trace capture, due to unwanted dma maintenance operations. Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support .../bindings/arm/arm,coresight-tmc.yaml | 26 ++ Documentation/trace/coresight/panic.rst | 362 ++++++++++++++++++ drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++ drivers/hwtracing/coresight/coresight-core.c | 42 ++ .../hwtracing/coresight/coresight-tmc-core.c | 326 +++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 92 ++++- .../hwtracing/coresight/coresight-tmc-etr.c | 181 ++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 104 +++++ include/linux/coresight.h | 12 + 12 files changed, 1222 insertions(+), 12 deletions(-) create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c -- 2.34.1

1 month

[PATCH v7 0/3] coresight: Add static trace id support

by Mao Jinlong

Some HW has static trace id which cannot be changed via software programming. For this case, configure the trace id in device tree with "arm,static-trace-id = <xxx>", and call coresight_trace_id_get_static_system_id with the trace id value in device probe function. The id will be reserved for the HW all the time if the device is probed. Changes since V6: 1. Add code to handle a case where the preferred_id is not valid when use static id. 2. Returen busy when static id is not freed. Changes since V5: 1. Remove the warn for staic id not available. 2. Drop the system_id if registering the coresight device fails. 3. Return busy when static id is not available in dummy driver. Changes since V4: 1. Use fwnode_property_read_u32 in fwnode_property_read_u32. 2. Update date and version in sysfs-bus-coresight-devices-dummy-source Changes since V3: 1. Adda new API function int coresight_trace_id_get_system_static_id(int trace_id). 2. Use the term "static trace id" for these devices where the hardware sets a non-programmable trace ID. Changes since V2: 1. Change "trace-id" to "arm,trace-id". 2. Add trace id flag for getting preferred id or ODD id. Changes since V1: 1. Add argument to coresight_trace_id_get_system_id for preferred id instead of adding new function coresight_trace_id_reserve_system_id. 2. Add constraint to trace-id in dt-binding file. Mao Jinlong (3): dt-bindings: arm: Add arm,static-trace-id for coresight dummy source coresight: Add support to get static id for system trace sources coresight: dummy: Add static trace id support for dummy source .../sysfs-bus-coresight-devices-dummy-source | 15 ++++ .../arm/arm,coresight-dummy-source.yaml | 6 ++ drivers/hwtracing/coresight/coresight-dummy.c | 81 ++++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 6 ++ .../hwtracing/coresight/coresight-trace-id.c | 43 +++++++--- .../hwtracing/coresight/coresight-trace-id.h | 9 +++ include/linux/coresight.h | 1 + 7 files changed, 140 insertions(+), 21 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source -- 2.17.1

1 month

[PATCH] coresight: Drop atomics in connection refcounts

by James Clark

These belong to the device being enabled or disabled and are only ever used inside the device's spinlock. Remove the atomics to not imply that there are any other concurrent accesses. If atomics were necessary I don't think they would have been enough anyway. There would be nothing to prevent an enable or disable running concurrently if not for the spinlock. Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/coresight-funnel.c | 6 +++--- drivers/hwtracing/coresight/coresight-replicator.c | 6 +++--- drivers/hwtracing/coresight/coresight-tpda.c | 6 +++--- include/linux/coresight.h | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 5a819c8970fb..bd32f74cbdae 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -86,14 +86,14 @@ static int funnel_enable(struct coresight_device *csdev, bool first_enable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_read(&in->dest_refcnt) == 0) { + if (in->dest_refcnt == 0) { if (drvdata->base) rc = dynamic_funnel_enable_hw(drvdata, in->dest_port); if (!rc) first_enable = true; } if (!rc) - atomic_inc(&in->dest_refcnt); + in->dest_refcnt++; spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) @@ -130,7 +130,7 @@ static void funnel_disable(struct coresight_device *csdev, bool last_disable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_dec_return(&in->dest_refcnt) == 0) { + if (--in->dest_refcnt == 0) { if (drvdata->base) dynamic_funnel_disable_hw(drvdata, in->dest_port); last_disable = true; diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 3e55be9c8418..31322aea19f2 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -126,7 +126,7 @@ static int replicator_enable(struct coresight_device *csdev, bool first_enable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_read(&out->src_refcnt) == 0) { + if (out->src_refcnt == 0) { if (drvdata->base) rc = dynamic_replicator_enable(drvdata, in->dest_port, out->src_port); @@ -134,7 +134,7 @@ static int replicator_enable(struct coresight_device *csdev, first_enable = true; } if (!rc) - atomic_inc(&out->src_refcnt); + out->src_refcnt++; spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) @@ -180,7 +180,7 @@ static void replicator_disable(struct coresight_device *csdev, bool last_disable = false; spin_lock_irqsave(&drvdata->spinlock, flags); - if (atomic_dec_return(&out->src_refcnt) == 0) { + if (--out->src_refcnt == 0) { if (drvdata->base) dynamic_replicator_disable(drvdata, in->dest_port, out->src_port); diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index bfca103f9f84..4ec676bea1ce 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -190,10 +190,10 @@ static int tpda_enable(struct coresight_device *csdev, int ret = 0; spin_lock(&drvdata->spinlock); - if (atomic_read(&in->dest_refcnt) == 0) { + if (in->dest_refcnt == 0) { ret = __tpda_enable(drvdata, in->dest_port); if (!ret) { - atomic_inc(&in->dest_refcnt); + in->dest_refcnt++; csdev->refcnt++; dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", in->dest_port); } @@ -223,7 +223,7 @@ static void tpda_disable(struct coresight_device *csdev, struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); spin_lock(&drvdata->spinlock); - if (atomic_dec_return(&in->dest_refcnt) == 0) { + if (--in->dest_refcnt == 0) { __tpda_disable(drvdata, in->dest_port); csdev->refcnt--; } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index c13342594278..834029cb9ba2 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -200,8 +200,8 @@ struct coresight_connection { struct coresight_device *dest_dev; struct coresight_sysfs_link *link; struct coresight_device *src_dev; - atomic_t src_refcnt; - atomic_t dest_refcnt; + int src_refcnt; + int dest_refcnt; }; /** -- 2.34.1

1 month

[PATCH v6 0/4] source filtering for multi-port output

by Tao Zhang

In our hardware design, by combining a funnel and a replicator, it implement a hardware device with one-to-one correspondence between output ports and input ports. The programming usage on this device is the same as funnel. The software uses a funnel and a static replicator to implement the driver of this device. Since original funnels only support a single output connection and original replicator only support a single input connection, the code needs to be modified to support this new feature. The following is a typical topology diagram of multi-port output mechanism. |----------| |---------| |----------| |---------| | TPDM 0 | | Source0 | | Source 1 | | TPDM 1 | |----------| |---------| |----------| |---------| | | | | | | | | | --------- | | | | | | | | | | | | | | | \-------------/ ---------------------- | \ Funnel 0 / | | ----------- | ------------------------------ | | | | | | \------------------/ \ Funnel 1 / ----| \--------------/ | | |----> Combine a funnel and a | | static replicator /-----------------\ | / replicator 0 \ ----| /---------------------\ | | | | | |-----------| | |---------| | | |TPDM0 |TPDM1 | \-----------------/ | \ TPDA 0 / | \-------------/ | | | | |Source0/1 | \-------------------------------/ \ Funnel 2 / \---------------------------/ Changes in V6: 1. Optimize the prompt content of the warning log when the filter handle is not a trace source. -- Suzuki K Poulose 2. Reset the filter device and fwnode if it is not a trace source. -- Suzuki K Poulose Changes in V5: 1. Replace "filter-src" with "filter-source" in the dt-binding document. -- Suzuki K Poulose 2. Optimize the comments of the patch "coresight: Add support for trace filtering by source" due to bad example. -- Suzuki K Poulose 3. Correct spelling errors in the patch "coresight: Add support for trace filtering by source". -- Suzuki K Poulose 4. Optimize the function "coresight_blocks_source". -- Suzuki K Poulose 5. Add { } in the function "of_coresight_parse_endpoint". -- Suzuki K Poulose 6. Adjust the order of the patches. -- Suzuki K Poulose 7. Adjust the alignment in "coresight-platform.c". -- Suzuki K Poulose Changes in V4: 1. Use "coresight_get_source(path)" in the function "coresight_disable_path_from" instead of explicitly passing the source. -- Suzuki K Poulose 2. Optimize the order of the input parameters for "_coresight_build_path". -- Suzuki K Poulose 3. Reuse the method "coresight_block_source" in "_coresight_build_path". -- Suzuki K Poulose 4. Remove the unnecessary () in "coresight_build_path". -- Suzuki K Poulose 5. Add a helper to check if a device is SOURCE. -- Suzuki K Poulose 6. Adjust the posistion of setting "still_orphan" in "coresight_build_path". -- Suzuki K Poulose Changes in V3: 1. Rename the function "coresight_source_filter" to "coresight_block_source". And refine this function. -- Suzuki K Poulose 2. Rename the parameters of the function "coresight_find_out_connection" to avoid confusion. -- Suzuki K Poulose 3. Get the source of path in "coresight_enable_path" and "coresight_disable_path". -- Suzuki K Poulose 4. Fix filter source device before skip the port in "coresight_orphan_match". -- Suzuki K Poulose 5. Make sure the device still orphan if whter is a filter source firmware node but the filter source device is null. -- Suzuki K Poulose 6. Walk through the entire coresight bus and fixup the "filter_src_dev" if the source is being removed. -- Suzuki K Poulose 7. Refine the commit description of patch#2. -- Suzuki K Poulose 8. Fix the warning reported by kernel test robot. -- kernel test robot. 9. Use the source device directly if the port has a hardcoded filter in "tpda_get_element_size". -- Suzuki K Poulose Changes in V2: 1. Change the reference for endpoint property in dt-binding. -- Krzysztof Kozlowski 2. Change the property name "filter_src" to "filter-src". -- Krzysztof Kozlowski 3. Fix the errors in running 'make dt_binding_check'. -- Rob Herring 4. Pass in the source parameter instead of path. -- Suzuki K Poulose 5. Reset the "filter_src_dev" if the "src" csdev is being removed. -- Suzuki K Poulose 6. Add a warning if the "filter_src_dev" is of not the type DEV_TYPE_SOURCE. -- Suzuki K Poulose 7. Optimize the procedure for handling all possible cases. -- Suzuki K Poulose Changes in V1: 1. Add a static replicator connect to a funnel to implement the correspondence between the output ports and the input ports on funnels. -- Suzuki K Poulose 2. Add filter_src_dev and filter_src_dev phandle to "coresight_connection" struct, and populate them if there is one. -- Suzuki K Poulose 3. To look at the phandle and then fixup/remove the filter_src device in fixup/remove connections. -- Suzuki K Poulose 4. When TPDA reads DSB/CMB element size, it is implemented by looking up filter src device in the connections. -- Suzuki K Poulose Tao Zhang (4): dt-bindings: arm: qcom,coresight-static-replicator: Add property for source filtering coresight: Add a helper to check if a device is source coresight: Add support for trace filtering by source coresight-tpda: Optimize the function of reading element size .../arm/arm,coresight-static-replicator.yaml | 19 ++- drivers/hwtracing/coresight/coresight-core.c | 113 +++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 21 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 13 +- include/linux/coresight.h | 12 +- 5 files changed, 155 insertions(+), 23 deletions(-) -- 2.17.1

1 month

Re: [PATCH 0/9] coresight: change some driver' spinlock type to raw_spinlock_t

by James Clark

On 25/11/2024 9:48 am, Yeoreum Yun wrote: > In some coresight drivers, drvdata->spinlock can be held during __schedule() > by perf_event_task_sched_out()/in(). > > Since drvdata->spinlock type is spinlock_t and > perf_event_task_sched_out()/in() is called after acquiring rq_lock, > which is raw_spinlock_t (an unsleepable lock), > this poses an issue in PREEMPT_RT kernel where spinlock_t is sleepable. > > To address this,change type drvdata->spinlock in some coresight drivers, > which can be called by perf_event_task_sched_out()/in(), > from spinlock_t to raw_spinlock_t. > > Levi Yun (9): > coresight: change coresight_device lock type to raw_spinlock_t > coresight-etm4x: change etmv4_drvdata spinlock type to raw_spinlock_t > coresight: change coresight_trace_id_map's lock type to raw_spinlock_t > coresight-cti: change cti_drvdata spinlock's type to raw_spinlock_t > coresight-etb10: change etb_drvdata spinlock's type to raw_spinlock_t > coresight-funnel: change funnel_drvdata spinlock's type to > raw_spinlock_t > coresight-replicator: change replicator_drvdata spinlock's type to > raw_spinlock_t > coresight-tmc: change tmc_drvdata spinlock's type to raw_spinlock_t > coresight/ultrasoc: change cti_drvdata spinlock's type to > raw_spinlock_t > > .../hwtracing/coresight/coresight-config.c | 21 +- > .../hwtracing/coresight/coresight-config.h | 2 +- > drivers/hwtracing/coresight/coresight-core.c | 2 +- > .../hwtracing/coresight/coresight-cti-core.c | 65 +- > .../hwtracing/coresight/coresight-cti-sysfs.c | 135 +++-- > drivers/hwtracing/coresight/coresight-cti.h | 2 +- > drivers/hwtracing/coresight/coresight-etb10.c | 62 +- > .../coresight/coresight-etm4x-core.c | 71 ++- > .../coresight/coresight-etm4x-sysfs.c | 566 +++++++++--------- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- > .../hwtracing/coresight/coresight-funnel.c | 34 +- > .../coresight/coresight-replicator.c | 36 +- > .../hwtracing/coresight/coresight-syscfg.c | 75 ++- > .../hwtracing/coresight/coresight-tmc-core.c | 9 +- > .../hwtracing/coresight/coresight-tmc-etf.c | 195 +++--- > .../hwtracing/coresight/coresight-tmc-etr.c | 199 +++--- > drivers/hwtracing/coresight/coresight-tmc.h | 2 +- > .../hwtracing/coresight/coresight-trace-id.c | 93 ++- > drivers/hwtracing/coresight/ultrasoc-smb.c | 12 +- > drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- > include/linux/coresight.h | 4 +- > 21 files changed, 751 insertions(+), 838 deletions(-) > > -- > LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} > Can TPIU be used as a sink with Perf? If so that one is missing the update. Makes me wonder if something like a "perf_component" flag in coresight_device or a #define would make sense. Then the lock type gets auto picked. Seems like in a few years we will have completely forgotten why some of the coresight locks are raw and others aren't.

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CoreSight November 2024