CoreSight August 2025

coresight@lists.linaro.org

7 participants
42 discussions

Re: [PATCH v2 0/3] coresight-tnoc: Add support for Interconnect TNOC

by yuanfang zhang

On 8/19/2025 7:30 PM, Krzysztof Kozlowski wrote: > On 19/08/2025 12:27, Yuanfang Zhang wrote: >> This patch series adds support for the Qualcomm CoreSight Interconnect TNOC >> (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding >> trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, >> this block does not support aggregation or ATID assignment. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> Changes in v2: >> - Refactor the dt-binding file. > > Everything is rafactor. What changed specifically? > > Or you just ignored prevous feedback and did other changes? > The feedback has not been ignored, i will update the detail in next patch. > > > Best regards, > Krzysztof

1 month, 1 week

Re: [PATCH v2 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

by yuanfang zhang

On 8/20/2025 3:45 AM, Rob Herring wrote: > On Tue, Aug 19, 2025 at 03:27:43AM -0700, Yuanfang Zhang wrote: >> Add device tree binding for Qualcomm Coresight Interconnect Trace >> Network On Chip (ITNOC). This TNOC acts as a CoreSight >> graph link that forwards trace data from a subsystem to the >> Aggregator TNOC, without aggregation or ATID functionality. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> .../bindings/arm/qcom,coresight-itnoc.yaml | 96 ++++++++++++++++++++++ >> 1 file changed, 96 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..a3b5f2b949f69617a014d0ae2831c9c767178f8c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> @@ -0,0 +1,96 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Interconnect Trace Network On Chip - ITNOC >> + >> +maintainers: >> + - Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> + >> +description: >> + The Interconnect TNOC is a CoreSight graph link that forwards trace data >> + from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it >> + does not have aggregation and ATID functionality. >> + >> +properties: >> + $nodename: >> + pattern: "^itnoc(@[0-9a-f]+)?$" >> + >> + compatible: >> + const: qcom,coresight-itnoc >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: apb >> + >> + in-ports: >> + $ref: /schemas/graph.yaml#/properties/ports > >> + properties: >> + '#address-cells': >> + const: 1 >> + '#size-cells': >> + const: 0 > > Drop these. Already defined by the above ref. > sure, will update. >> + >> + patternProperties: >> + '^port(@[0-9a-f]{1,2})?$': >> + description: Input connections from CoreSight Trace Bus >> + $ref: /schemas/graph.yaml#/properties/port >> + >> + out-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + additionalProperties: false >> + >> + properties: >> + port: >> + description: out connections to aggregator TNOC >> + $ref: /schemas/graph.yaml#/properties/port >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - in-ports >> + - out-ports >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + itnoc@109ac000 { >> + compatible = "qcom,coresight-itnoc"; >> + reg = <0x109ac000 0x1000>; >> + >> + clocks = <&aoss_qmp>; >> + clock-names = "apb"; >> + >> + in-ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + port@0 { >> + reg = <0>; >> + tn_ic_in_tpdm_dcc: endpoint { >> + remote-endpoint = <&tpdm_dcc_out_tn_ic>; >> + }; >> + }; >> + }; >> + >> + out-ports { >> + port { >> + tn_ic_out_tnoc_aggr: endpoint { >> + /* to Aggregator TNOC input */ >> + remote-endpoint = <&tn_ag_in_tn_ic>; >> + }; >> + }; >> + }; >> + }; >> +... >> >> -- >> 2.34.1 >>

1 month, 1 week

Re: [PATCH v2 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

by yuanfang zhang

On 8/19/2025 8:32 PM, Rob Herring (Arm) wrote: > > On Tue, 19 Aug 2025 03:27:43 -0700, Yuanfang Zhang wrote: >> Add device tree binding for Qualcomm Coresight Interconnect Trace >> Network On Chip (ITNOC). This TNOC acts as a CoreSight >> graph link that forwards trace data from a subsystem to the >> Aggregator TNOC, without aggregation or ATID functionality. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> .../bindings/arm/qcom,coresight-itnoc.yaml | 96 ++++++++++++++++++++++ >> 1 file changed, 96 insertions(+) >> > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250819-itn… > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. > Below is my dtschema and yamllint version, They should already be the latest version. Name: dtschema Version: 2025.8 Name: yamllint Version: 1.37.1 I ran below 'make dt_binding_check', don't get any error/warnings. make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml

1 month, 1 week

[PATCH v2 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Changes in v2: - Refactor the dt-binding file. - Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device. - Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 96 ++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 147 ++++++++++++++++++--- 2 files changed, 226 insertions(+), 17 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

1 month, 2 weeks

[PATCH 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 108 +++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 179 +++++++++++++++------ 2 files changed, 240 insertions(+), 47 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

1 month, 2 weeks

Re: [PATCH 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

by yuanfang zhang

On 8/16/2025 4:33 PM, Krzysztof Kozlowski wrote: > On 15/08/2025 15:18, Yuanfang Zhang wrote: >> Add device tree binding for Qualcomm Coresight Interconnect Trace >> Netwrok On Chip (ITNOC). This TNOC acts as a CoreSight >> graph link that forwards trace data from a subsystem to the >> Aggregator TNOC, without aggregation or ATID functionality. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> .../bindings/arm/qcom,coresight-itnoc.yaml | 108 +++++++++++++++++++++ >> 1 file changed, 108 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..fd224e07ce68918b453210763aacda585d5a5ca2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> @@ -0,0 +1,108 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Interconnect Trace Network On Chip - ITNOC >> + >> +maintainers: >> + - Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> + >> +description: | > Do not need '|' unless you need to preserve formatting. sure, will remove it. >> + The Interconnect TNOC is a CoreSight graph link that forwards trace data >> + from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it >> + does not have aggregation and ATID functionality. >> + >> +select: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,coresight-itnoc >> + required: >> + - compatible > Why all this? Drop sure. >> + >> +properties: >> + $nodename: >> + pattern: "^tnoc(@[0-9a-f]+)?$" > Why are you requiring a non-generic name? will update the name. >> + >> + compatible: >> + items: > No need for items sure, will remove it. >> + - const: qcom,coresight-itnoc >> + >> + reg: >> + maxItems: 1 >> + description: Base address and size of the ITNOC registers. > Drop, redundant sure, will remove it. >> + >> + clock-names: >> + items: >> + - const: apb > Drop clock-names, obvious. Also, odd order - names are never before > actual property. sure, will update the order. >> + >> + clocks: >> + maxItems: 1 >> + >> + in-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + >> + properties: >> + '#address-cells': >> + const: 1 >> + '#size-cells': >> + const: 0 >> + >> + patternProperties: >> + '^port(@[0-9a-f]{1,2})?$': > Why do you have here 255 ports? It supports a maximum of 256 input ports, so it is limited to 0-255. >> + description: Input connections from CoreSight Trace Bus >> + $ref: /schemas/graph.yaml#/properties/port >> + additionalProperties: false > This goes after $ref sure, will update. >> + >> + out-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + >> + properties: >> + port: >> + description: out connections to aggregator TNOC >> + $ref: /schemas/graph.yaml#/properties/port >> + additionalProperties: false > This goes after ref sure, will update. >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names > And here different order... Be consistent. See also DTS coding style. sure, will update the order. >> + - in-ports >> + - out-ports >> + >> +additionalProperties: false >> + > > > Best regards, > Krzysztof

1 month, 2 weeks

Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 12/08/2025 9:24 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") This tag isn't right. Although this is where the register accesses were last touched, the root issue was present from the introduction of the driver. > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > Changes in v2: > - Add fixes tag. > - Replace "if (drvdata->nrseqstate)" with "if (drvdata->numextinsel)" > - Link to v1: https://lore.kernel.org/r/20250811-trcextinselr_issue-v1-1-ed78f3215502@oss… > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..4e411427303981104d11720d3c73af91030f8df3 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->numextinsel) > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards,

1 month, 2 weeks

Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 12/08/2025 9:24 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > Changes in v2: > - Add fixes tag. > - Replace "if (drvdata->nrseqstate)" with "if (drvdata->numextinsel)" > - Link to v1: https://lore.kernel.org/r/20250811-trcextinselr_issue-v1-1-ed78f3215502@oss… > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..4e411427303981104d11720d3c73af91030f8df3 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->numextinsel) > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards, Reviewed-by: James Clark <james.clark(a)linaro.org>

1 month, 2 weeks

Re: [PATCH] coresight-etm4x: Conditionally access register TRCEXTINSELR

by James Clark

On 11/08/2025 10:57 am, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > Looks like this should have a fixes: tag. > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 ++++++++--- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 42e5d37403addc6ec81f2e3184522d67d1677c04..8a9c4caceff0165e4fce7ac4250f3e16ccc1d34e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -528,7 +528,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); > etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); > @@ -1423,6 +1424,7 @@ static void etm4_init_arch_data(void *info) > etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); > /* NUMEXTIN, bits[8:0] number of external inputs implemented */ > drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); > + drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); > /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ > drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); > /* ATBTRIG, bit[22] implementation can support ATB triggers? */ > @@ -1852,7 +1854,9 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > - state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > + > + if (drvdata->nrseqstate) Shouldn't this be "if (drvdata->numextinsel)"? Or it needs a comment saying why it's different to the others. Otherwise looks ok. > + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); > @@ -1984,7 +1988,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > - etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > + if (drvdata->numextinsel) > + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); > > for (i = 0; i < drvdata->nr_cntr; i++) { > etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index ac649515054d905fa365203bd35f1d839b03292f..823914fefa90a36a328b652b0dc3828b9bddd990 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -162,6 +162,7 @@ > #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) > > #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) > +#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9) > #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) > #define TRCIDR5_ATBTRIG BIT(22) > #define TRCIDR5_LPOVERRIDE BIT(23) > @@ -999,6 +1000,7 @@ struct etmv4_drvdata { > u8 nr_cntr; > u8 nr_ext_inp; > u8 numcidc; > + u8 numextinsel; > u8 numvmidc; > u8 nrseqstate; > u8 nr_event; > > --- > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 > change-id: 20250811-trcextinselr_issue-f267afa0e5ed > > Best regards,

1 month, 3 weeks

Re: [PATCH v1] coresight: tpda: fix the logic to setup the element size

by James Clark

On 06/08/2025 9:09 am, Jie Gan wrote: > Some TPDM devices support both CMB and DSB datasets, requiring > the system to enable the port with both corresponding element sizes. > > Currently, the logic treats tpdm_read_element_size as successful if > the CMB element size is retrieved correctly, regardless of whether > the DSB element size is obtained. This behavior causes issues > when parsing data from TPDM devices that depend on both element sizes. > > To address this, the function should explicitly fail if the DSB > element size cannot be read correctly. > > Fixes: e6d7f5252f73 ("coresight-tpda: Add support to configure CMB element") > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 0633f04beb24..333b3cb23685 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -71,6 +71,8 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > if (tpdm_data->dsb) { > rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), > "qcom,dsb-element-bits", &drvdata->dsb_esize); > + if (rc) > + goto out; > } > > if (tpdm_data->cmb) { > @@ -78,6 +80,7 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > "qcom,cmb-element-bits", &drvdata->cmb_esize); > } > > +out: > if (rc) > dev_warn_once(&csdev->dev, > "Failed to read TPDM Element size: %d\n", rc); Reviewed-by: James Clark <james.clark(a)linaro.org>

1 month, 3 weeks

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CoreSight August 2025