Hi Mathieu, thanks for joining the thread.
So far this isn't something we had to deal with - all the platforms we worked with had the timestamp generator enabled. I see in your initial email you're already using the keywork "timestamp" on the perf command line. That does the trick on Juno and the 410c. As Al pointed out it is likely you will have to add support for TSGEN block.
I see. Actually, if I understand the datasheet correctly, timestamp generator should be enabled by default on US+ as well. Perhaps it's the firmware who turns it off? I remember a post on this mailing list, that a firmware update on Juno fixed a similar empty timestamps problem on that platform. Fortunately, Xilinx's forks of U-Boot and ATF are public, so I'll inspect them for such operations.
If that's the case, do you think it would be beneficial to add separate bindings for TSGEN? Perhaps just another reg pair and reg-name value to ETM node, similarly to what's already done for stimulus base in STM. ETM driver could look for reg-name 'timestamp', get the corresponding pair from reg, check if TSGEN is disabled and enable it if necessary. If I understand correctly, that part should be generic, as TSGEN is a standard CS component. It's just a random idea, but I'd appreciate your comment on that.
If you have the base physical address of the timestamp control registers (you may have two regions, one for control registers and one for read registers - you want the control registers), the enable bit is bit 0 of word 0. You can read it like this:
Looks like a nice and quick way to prove it. Thanks Al, I'll give it a try as soon as I have the board back on my desk.
Best regards, Wojciech