Query regarding AXI Write Burst Length in ETR driver

Hi All,

The AXI write burst length is set to 0xF in TMC_AXICTL register in the TMC ETR driver.

Definition in coresight-tmc.h #define TMC_AXICTL_WR_BURST_16 0xF00

Marvell CN10K chip uses Coresight SoC-600 IP. Since write burst length field is implementation defined, the maximum value supported by our chip is 0x7.

We could not find a way to figure out the maximum supported value through any of the ETR registers. So can you please recommend a way to choose the value 0x7 without affecting other silicons ?

With Regards, Tanmay