On 1/14/21 2:07 PM, Rob Herring wrote:
On Wed, Jan 13, 2021 at 09:48:18AM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose suzuki.poulose@arm.com
Document the device tree bindings for Trace Buffer Extension (TRBE).
Cc: Anshuman Khandual anshuman.khandual@arm.com Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
Documentation/devicetree/bindings/arm/trbe.yaml | 46 +++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml new file mode 100644 index 0000000..2258595 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/trbe.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/trbe.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+title: ARM Trace Buffer Extensions
+maintainers:
- Anshuman Khandual anshuman.khandual@arm.com
+description: |
- Description of TRBE hw
Huh?
Doh ! That was due to a miscommunication between us. This should be :
description: | Arm Trace Buffer Extension (TRBE) is a per CPU component for storing trace generated on the CPU to memory. It is accessed via CPU system registers. The software can verify if it is permitted to use the component by checking the TRBIDR register.
+properties:
- $nodename:
- pattern: "trbe"
const: trbe
- compatible:
- items:
- const: arm,trace-buffer-extensionAny versioning to this? Or is that discoverable?
It must be discoverable via ID_AA64DFR0_EL1.TraceBuffer. The IP is entirely accessed by the CPU system registers. So, any further changes can be interpreted from the system registers (including if the access is blocked by a higher exception level).
- interrupts:
- description: |
Exactly 1 PPI must be listed. For heterogeneous systems whereTRBE is only supported on a subset of the CPUs, please consultthe arm,gic-v3 binding for details on describing a PPI partition.- maxItems: 1
+required:
- compatible
- interrupts
+additionalProperties: false
Extra blank line.
Removed.
Cheers
Suzuki