On Thu, Jun 05, 2025 at 02:50:41PM +0100, James Clark wrote:
[...]
Hi Leo,
I ran this stress test on Juno by enabling and disabling concurrently with no sleeps:
# echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink # while true; do \ echo 0 > /sys/devices/system/cpu/cpu2/online; \ echo 1 > /sys/devices/system/cpu/cpu2/online; \ done &
# while true; do \ echo 1 > /sys/bus/coresight/devices/etm2/enable_source; \ echo 0 > /sys/bus/coresight/devices/etm2/enable_source; \ done &
I get lots of these:
coresight tmc_etr0: timeout while waiting for TMC to be Ready coresight tmc_etr0: Failed to enable : TMC not ready
And then even after disabling the source and sink the Perf tests don't pass anymore:
# perf test -F -vvv "arm coresight trace" --- start --- Recording trace (only user mode) with path: CPU0 => tmc_etf0 Looking at perf.data file for dumping branch samples: CoreSight path testing (CPU0 -> tmc_etf0): FAIL
I suppose it's possible this isn't entirely related to your changes, and I know we've seen some of those timeout issues before. But it's probably worth investigating.
Thanks a lot for testing! I will look into the issue.
Leo