Re: Reference platform

8 Apr 2022

      Hi Hugh,
I have asked around here. Our teams putting support for ELA600 into ARM-DS
did so using internal FPGA builds accessed from a remote site.
At present we are not aware of any ARM development platform that has ELA600
- nor as far as I can gather is there an ARM developed platform (such as
Juno / N1-SDP) being worked on that will have ir.
I looked into the models available able too - these do have some
peripherals - but omit CoreSight related technologies.
Regards
Mike
On Thu, 7 Apr 2022 at 15:01, Al Grant Al.Grant@arm.com wrote:
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Hi Hugh, sorry no, I don't know of any. As far as I know, any integration
work we did at our end for either of these features, used FPGA targets.
Al
*From:* Hugh O'Keeffe hugh.okeeffe@ashling.com
*Sent:* 06 April 2022 14:23
*To:* Mike Leach mike.leach@linaro.org; Al Grant Al.Grant@arm.com
*Cc:* coresight@lists.linaro.org
*Subject:* Reference platform
Hi Mike and Al,
Any suggestions for a reference platform that we could start some OpenCSD
and CSAL investigative engineering working on?
Ideally:

Multi-core with SoC-600 and ELA-600 CoreSight

SoC-600 trace streaming interface between host and target using USB3.1

(i.e. no debug probe necessary)

Linux/Android

Would appreciate your inputs
Thanks
Hugh
-----Original Message-----
From: Al Grant Al.Grant@arm.com
Sent: Monday 28 March 2022 16:25
To: Mike Leach mike.leach@linaro.org; Hugh O'Keeffe <
hugh.okeeffe@ashling.com>
Cc: coresight@lists.linaro.org
Subject: RE: CoreSight ELA-600 Embedded Logic Analyzer
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-----Original Message-----
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From: Mike Leach mike.leach@linaro.org
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Sent: 28 March 2022 12:44
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To: Hugh O'Keeffe hugh.okeeffe@ashling.com
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Cc: Al Grant Al.Grant@arm.com; coresight@lists.linaro.org
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Subject: Re: CoreSight ELA-600 Embedded Logic Analyzer
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Hi Hugh,
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On Mon, 28 Mar 2022 at 11:41, Hugh O'Keeffe hugh.okeeffe@ashling.com
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wrote:
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Hi Al and Mike,
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Appreciate your response.  It seems that OpenCSD and CSAL are very
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similar. Are they two different approaches to solving the same problem
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OR in fact are they inherently different? I note that OpenCSD appears
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to actually decode trace as well  (which CSAL does not appear to
support).
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CSAL primarily configures and programs CoreSight components using the
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memory interface. Either bare metal, or under linux if the correct
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memory access is allowed by the kernel configuration. It also has a
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bunch of example programs demonstrating usage of the library, and
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extracting trace on certain platforms.
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OpenCSD decodes any collected trace. It does not do any configuration
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but requires certain trace configuration values to be provided in

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order to do the decode - alongside memory images if full CPU
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instruction trace decode is required.
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It does not do any data presentation or correlation - that is for any
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client application to do - though it does have packet printing
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routines that will give a human readable version of the decoded packets.
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OpenCSD is used by perf in linux to do all the decode for this tool.
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OpenCSD does come with its own standalone test program trc_pkt_lister
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which will decode trace snapshots and output packets in the readable

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format mentioned above. These snapshots consist of trace data buffers
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a set of .ini type files that contain the configuration of the

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hardware, and the memory images needed for full decode. If packet
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decode only is required then the memory images can be omitted. The
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specification for trace snapshots is provided in the OpenCSD github
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repository, and example snapshots are also in the repository.
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There is no current ELA600 driver in the kernel - and I am unsure if
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there is one in development.
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If your ELA600 is configured to output to the Coresight trace bus -
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then configuring using CSAL / decoding using OpenCSD would be a possible
path.
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If it is configured to use its own internal RAMs then OpenCSD will not
help.
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As Al mentions, the actual format of any given ELA data is SoC
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specific - so interpretation will have to be customized.
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Assuming you configure and get the device to trace into an ETR / ETF
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then this data will be multiplexed into the CoreSight frame format -
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on an ATID basis.
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OpenCSD could help here in that the front end will demultiplex the
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data to produce a byte stream input for a decoder based on the ATID.
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OpenCSD contains an API that allows custom decoders to be registered
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with the library.
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Thus an ELA decoder can be registered, then an instance attached to
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the ATID being used for the ELA600 and the library would feed the
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demultiplexed stream to the decoder. Alternatively, it should be
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relatively easy to write a simple program using the library demux
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components to take in a formatted buffer and output a binary file of raw
data for a given ATID.
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Regards
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Mike
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Would appreciate any pointers or comments as to how they compare and
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what would be my best starting point.
Further to Mike's excellent summary, CSAL is really a few different things:

a pure C library for CoreSight configuration, suitable for embedding in

firmware, RTOS, boot code etc. It can run over Linux /dev/mem, but this is
more for general testing than expectation anyone would want to run it this
way, especially now that Linux has its own drivers for ETM. In theory this
could be combined with OpenCSD, i.e. use CSAL to configure a trace device
and OpenCSD to decode it. I don't know that anyone has done that as CSAL's
really designed for more limited targets where you’d likely decode the
trace offline.

in coresight-tools (csscan.py and some kernel modules): tools for

CoreSight device and topology discovery, and status reporting.
The discovery phase is usally something that you'd only do once when you
get a new target, as it may leave the target in odd states. Status
reporting is harmless though and may be useful when diagnosing issues with
kernel drivers, or even external debug. These Python tools can write to the
CoreSight devices. This is required for topology discovery, but any kind of
programming is possible if you know the register offsets and values.

for testing, there's a daemon (devmemd) which can run on a target to do

the low-level register access, allowing all the complicated stuff done by
CSAL and csscan.py to be run on your development machine where it may be
easier to experiment with it.
We also have some Python modules for decoding trace but these currentlly
aren't upstream - you wouldn't want to use these for a production tool (you
should use OpenCSD) but they may be useful when experimenting - I will look
at getting them upstream.
Al
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Thanks
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Hugh
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-----Original Message-----
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From: Al Grant Al.Grant@arm.com
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Sent: Friday 25 March 2022 09:49
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To: Mike Leach mike.leach@linaro.org; Hugh O'Keeffe
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hugh.okeeffe@ashling.com
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Cc: coresight@lists.linaro.org
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Subject: RE: CoreSight ELA-600 Embedded Logic Analyzer
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On Thu, 24 Mar 2022 at 17:47, Hugh O'Keeffe
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hugh.okeeffe@ashling.com
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wrote:
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Hi All,
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Couple of questions:
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Does anyone know of any other software options other than

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DS-5 for
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configuring, capturing and viewing data using the ELA-600 ?
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In https://github.com/ARM-software/CSAL, the csscan.py script has
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some
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basic support for reading the ELA config and dumping its SRAM buffer.
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No support for decoding ELA capture out of a CoreSight trace stream
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though, as it was only tested on ELA-500.
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The assignment of input signals may be SoC-specific and there may
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also be
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SoC-specific obfuscation applied to the data - this is one of those
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"ask your SoC vendor" situations. The scripts that have gone upstream
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don't reveal anything that is not already public.
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Al
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I could roll my own but I don't think OpenCSD has support for

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the
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ELA-
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Correct ?

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As I maintain OpenCSD I can answer this second question....
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No - there is not an ELA specific decoder in OpenCSD. Nor are
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there plans to add one at present.
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That said the the OpenCSD infrastucture should allow a new decode
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module to be added easily.
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Regards
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Mike
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Thanks in advance
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Hugh
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-----Original Message-----
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From: coresight-request@lists.linaro.org
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coresight-request@lists.linaro.org
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Sent: Thursday 24 March 2022 17:36
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To: Hugh O'Keeffe hugh.okeeffe@ashling.com
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Subject: Welcome to the "CoreSight" mailing list
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--
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Mike Leach
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Principal Engineer, ARM Ltd.
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Manchester Design Centre. UK
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Mike Leach
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Principal Engineer, ARM Ltd.
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Manchester Design Centre. UK

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-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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Re: Reference platform