Hi Rob, Mathieu,
On Mon, Oct 08, 2018 at 12:16:02PM +0100, Robert Walker wrote:
This patch adds support for generating instruction samples from trace of AArch32 programs using the A32 and T32 instruction sets.
T32 has variable 2 or 4 byte instruction size, so the conversion between addresses and instruction counts requires extra information from the trace decoder, requiring version 0.9.4 of OpenCSD. A check for the new struct member has been added to the feature check for OpenCSD.
As I mentioned in another offline email, OpenCSD seems will have no version 0.9.4 and will directly jump to 0.1.0 version.
I did several verifications with this patch and with Mike's OpenCSD patches [1]:
- Tested with A64 binary, the decoding is same between with and without this patch; - Passed - Tested with A32/T32 instructions with static linkage; - Passed - Tested with A32/T32 instructions with dynamic linkage;
For this case you could see below minor issue I observed:
--- Disassembly --- 00000440 printf@plt: 440: e28fc600 add ip, pc, #0, 12 444: e28cca10 add ip, ip, #16, 20 ; 0x10000 448: e5bcfbc8 ldr pc, [ip, #3016]! ; 0xbc8
--- Decoding --- main 8451 1 branches: f7c0e414 coresight_test1+0x2c (/root/coresight_test/libcstest.so) => 41159e main+0x12 (/root/coresight_test/main) main 8451 1 branches: 4115a8 main+0x1c (/root/coresight_test/main) => 411440 printf@plt+0x0 (/root/coresight_test/main) main 8451 1 branches: 411442 printf@plt+0x2 (/root/coresight_test/main) => f7b4e21c printf+0x0 (/usr/lib/arm-linux-gnueabihf/libc-2.27.so)
So you could see the decoding says it will jump to "411440 printf@plt+0x0", this is right if we connect with printf@plt disassembly code, but in the next decoding log it says the branch instruction is at "411442 printf@plt+0x2", this is not correct. We should expect the branch is taken at "448" rather than "442".
I also enclosed decoding and disassembly logs for your checking, please let me know if need me to provide more detailed info for testing case and testing commands for this.
[...]
Thanks, Leo Yan
[1] https://lists.linaro.org/pipermail/coresight/2018-October/001835.html