Thanks Mike, Do you have a demo video or something which shows how it's done from beginning to trace decode ? Just want to make sure it's done correctly.
Ajith K Issac Broadcom DCSG
On Wed, Jul 29, 2020 at 10:20 AM Mike Leach mike.leach@linaro.org wrote:
Hi,
On Wed, 29 Jul 2020 at 16:15, Andrew Hadley andrew.hadley@broadcom.com wrote:
So I'm not exactly sure how or what I'm setting up, but the only things that appear to have values is cpu_0.ini and device_1.ini.
MegaRAID provided an initial sample dump, I pulled up their ini files and made modifications to match our app.axf. I added only a few regions (that I felt were applicable) in the app.axf. (Comments in *bold red*).
The rest of the ini files are just references to configuring the names of the ini.
When I run the trc_pkt_lister I don't see any difference to my output (from before I made the changes).
Did you add the -decode option to the command line?
*cpu_0.ini* [device] name=cpu_0 class=core type=Cortex-A15
*ajh - There are 17 sections in the app.axf, but only a few regions that contain code. I just copied 3 of those sections into the dump regions. Do I need more? Also, this seems like it can be pulled from the axf using the fromelf app. Do I need to write a script to do this or does something already exist?*
Hard to say if these areas will completely cover the area traced - however, the decoder will output partial trace range packets when the addresses match the dump files. If trace goes out of range for the memory dumps then NACC packets will be output for the unknown addresses. I would start with these and see how far the decoder gets. Looking at a few of the addresses in the dump file they do seem to be in the range of the dump files you specify.
[dump0] file=app.axf address=0x70004194 length=0x3077d4 offset=0x41c8
[dump1] file=app.axf address=0x7f100000 length=0x8e0 offset=0x34
[dump2] file=app.axf address=0x7f1008e0 length=0x4a0 offset=0x914
*ajh - I don't know what to provide in regs? What is this needed for and what registers are pertinent?* [regs] R15=0 CPSR=0x4000003F
For trace - these regs are not needed. They are used if loading the snapshot into other tools.
*device_1.ini* *ajh - I didn't make any changes to this file, are these the coresight registers at 0x06180_0000 (Avengers CPU0 coresight block).*
Can't comment on your specific system but these are the CoreSight PFT registers as defined in the PFT specification.
[device] name=PTM_0 class=trace_source type=PTM1.1
[regs] ETMCR(0x0)=0x3000D400
This value indicates that cycle accurate trace is being generated - if this does not match your system then this could explain the strange cycle counts. Also return stack and timestamp tracing are active & a 32 bit context ID are being traced.
All these parameters affect how the decoder interprets the trace packets. This value must reflect the value of this register at the time trace was collected.
Regards
Mike
ETMIDR(0x79)=0x411CF314 ETMCCER(0x7A)=0x34C01AC2 ETMTRACEIDR(0x80)=0x0000001A
On Wed, Jul 29, 2020 at 9:03 AM Ajith Kurian Issac < ajith-kurian.issac@broadcom.com> wrote:
Thanks Mike, We will fix our snapshot files. Thanks for your quick repsonse.
Ajith K Issac Broadcom DCSG
On Wed, Jul 29, 2020 at 4:58 AM Mike Leach mike.leach@linaro.org wrote:
Hi,
Looking at the file, and the end portion you mention, I would say that the configuration for the decoder is not correctly set up. The very high cycle numbers between E atoms and the errors such as invalid header and bad async would suggest this. trc_pkt_lister works off a snapshot directory which I am assuming you have found out. The contents of this directory set up the decode parameters for the program - so ensure that all the accompanying .ini files match your system correctly.
To get full decode you need to add in the -decode command line option., This also requires providing the program images / memory dumps containing the executed code so that the decode can take place. The process for decode takes the waypoint addresses in the PTM data and reads the instructions from the memory image from that address, The output will be executed instruction ranges - not disassembly - see the example below. This - from one of the shipped examples with the library - shows a decode output from an a15 running PTM. The memory images loaded for decode are listed as well.
The lines from the example: Idx:25; ID:0; [0xd0 ]; ATOM : Atom packet; ENEEE; Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000504:[0x80000518] num_i(5) last_sz(4) (ISA=A32) E BR b+link ) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x800004d8:[0x800004ec] num_i(5) last_sz(4) (ISA=A32) N BR <cond>) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x800004ec:[0x800004f4] num_i(2) last_sz(4) (ISA=A32) E BR <cond>) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000500:[0x80000504] num_i(1) last_sz(4) (ISA=A32) E iBR V7:impl ret) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000518:[0x80000528] num_i(4) last_sz(4) (ISA=A32) E BR b+link )
shows a packet with 5 atoms, and the decode of each of those atoms into instruction executed ranges. This is achieved by walking the memory images looking for the relevant waypoint instructions corresponding to the atoms. This OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000504:[0x80000518] num_i(5) last_sz(4) (ISA=A32) E BR b+link ) instruction range format is the final output from the library. It is up to the client of the OpenCSD library to convert these ranges into whatever the desired output is (disassmbly / statistical analysis etc.)
You can get more information on this from the library documentation - explaining the snapshot format and the operation of the library.
Regards
Mike
e.g. ** Library Version : 0.14.2
Test Command Line:- ./bin/linux64/rel/trc_pkt_lister -ss_dir ./snapshots/trace_cov_a15 -decode -logfilename ./results/trace_cov_a15.ppl
Trace Packet Lister : reading snapshot from path ./snapshots/trace_cov_a15 Using PTM_0_2 as trace source Trace Packet Lister : Protocol printer PTM on Trace ID 0x0 Trace Packet Lister : Set trace element decode printer Gen_Info : Mapped Memory Accessors Gen_Info : FileAcc; Range::0x80000000:80000277; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_0_VECTORS.bin Gen_Info : FileAcc; Range::0x80000278:80001c27; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_1_RO_CODE.bin Gen_Info : FileAcc; Range::0x80001c28:80001d57; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_2_RO_DATA.bin Gen_Info : FileAcc; Range::0x80001d58:80001d67; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_3_RW_DATA.bin Gen_Info : FileAcc; Range::0x80001d68:80001fa7; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_4_ZI_DATA.bin Gen_Info : FileAcc; Range::0x80040000:8007ffff; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_5_ARM_LIB_HEAP.bin Gen_Info : FileAcc; Range::0x80080000:8008ffff; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_6_ARM_LIB_STACK.bin Gen_Info : FileAcc; Range::0x80090000:8009ffff; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_7_IRQ_STACK.bin Gen_Info : FileAcc; Range::0x80100000:80103fff; Mem Space::Any Filename=./snapshots/trace_cov_a15/mem_Cortex-A15_0_8_TTB.bin Gen_Info : ======================== Idx:0; ID:0; [0x00 0x00 0x00 0x00 0x00 0x80 ]; ASYNC : Alignment Synchronisation Packet; Idx:0; ID:2; OCSD_GEN_TRC_ELEM_NO_SYNC( [init-decoder]) Idx:6; ID:0; [0x08 0x58 0x05 0x00 0x80 0x61 ]; ISYNC : Instruction Synchronisation packet; (Debug Exit); Addr=0x80000558; S; ISA=ARM(32); Idx:6; ID:2; OCSD_GEN_TRC_ELEM_TRACE_ON( [debug restart]) Idx:6; ID:2; OCSD_GEN_TRC_ELEM_PE_CONTEXT((ISA=A32) S; 32-bit; ) Idx:12; ID:0; [0x84 ]; ATOM : Atom packet; E; Idx:12; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000558:[0x8000055c] num_i(1) last_sz(4) (ISA=A32) E BR b+link ) Idx:13; ID:0; [0x81 0x80 0x80 0x80 0x48 0x02 ]; BRANCH_ADDRESS : Branch address packet; Addr=0x00000000 ~[0x0]; S; Excep=Debug Halt [01]; Idx:13; ID:2; OCSD_GEN_TRC_ELEM_EXCEPTION(pref ret addr:0x80000504; excep num (0x01) ) Idx:19; ID:0; [0x08 0x04 0x05 0x00 0x80 0x61 ]; ISYNC : Instruction Synchronisation packet; (Debug Exit); Addr=0x80000504; S; ISA=ARM(32); Idx:19; ID:2; OCSD_GEN_TRC_ELEM_TRACE_ON( [debug restart]) Idx:25; ID:0; [0xd0 ]; ATOM : Atom packet; ENEEE; Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000504:[0x80000518] num_i(5) last_sz(4) (ISA=A32) E BR b+link ) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x800004d8:[0x800004ec] num_i(5) last_sz(4) (ISA=A32) N BR <cond>) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x800004ec:[0x800004f4] num_i(2) last_sz(4) (ISA=A32) E BR <cond>) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000500:[0x80000504] num_i(1) last_sz(4) (ISA=A32) E iBR V7:impl ret) Idx:25; ID:2; OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x80000518:[0x80000528] num_i(4) last_sz(4) (ISA=A32) E BR b+link )
On Tue, 28 Jul 2020 at 20:22, Ajith Kurian Issac < ajith-kurian.issac@broadcom.com> wrote:
Hi Mike, We are trying to make open CSD working in our silicon sample. It is very much required for our debug as we cannot attach DS5 early enough. We were able to generate the trace.bin and generate the trace decode file(attached) I have few questions [image: image.png] The end portion of teh trace looks something like this.
I know PTM only takes the branch address. Is there any way we can make it more readable by filling the missing instructions between branches? or is this the final output.
Also can you check the attached file and see if anything else is missing in our setup?
Ajith K Issac Broadcom DCSG
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
