On Tue, 19 Feb 2019 at 13:05, Al Grant Al.Grant@arm.com wrote:
Looks like I'm lucky indeed - the US+ datasheet mentions there's a TSGEN block in the memory map. Could you please elaborate on how the CS framework can enable it? I would suspect there are some coresight-timestamp-like bindings, but I can't see anything related. How can I tell the driver where the timestamp generator is mapped?
So far this isn't something we had to deal with - all the platforms we worked with had the timestamp generator enabled. I see in your initial email you're already using the keywork "timestamp" on the perf command line. That does the trick on Juno and the 410c. As Al pointed out it is likely you will have to add support for TSGEN block.
Mathieu
I'm not sure you can, at any rate I can't see the code for it in the upstream source. But it's something the framework is meant to do. You'd have to modify the framework to read the timestamp generator address from the DTS and then enable/disable it under control of a reference count.
If you have the base physical address of the timestamp control registers (you may have two regions, one for control registers and one for read registers - you want the control registers), the enable bit is bit 0 of word 0. You can read it like this:
busybox devmem xxxxxx 32where xxxxx is the base address. You might see either 0x00000000 or 0x00000002. If the bottom bit is set then the timestamp is already enabled. Otherwise enable it by writing back e.g.
busybox devmem xxxxxx 32 1I'm only guessing that that's the issue here - it could be something different, but it's worth a try.
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