Waiting for status bits

Tor, Mike and all,

Here is something i'd like your opinion on...

Before programming the ETMv3/PTM, ETMCR:10 needs to be set to one and when enabling the tracer, the bit needs to be cleared. Each time the status of ETMSR:1 needs to be probed before moving on, something that is quite costly. Is there a official limit of time for this operation to be carried out?

The same question applies for ETB's FFCR:6 and FFSR:1.

At this time the driver wait for 100 usec before complaining - from your experience, this this too short or it may need more time?

Thanks, Mathieu