On Wed, 19 Feb 2020 at 03:55, Poonam Aggrwal poonam.aggrwal@nxp.com wrote:
Hello Mathieu
-----Original Message----- From: Mathieu Poirier mathieu.poirier@linaro.org Sent: Friday, February 14, 2020 10:37 PM To: Era Tiwari era.tiwari@nxp.com Cc: Poonam Aggrwal poonam.aggrwal@nxp.com; Coresight ML coresight@lists.linaro.org Subject: Re: [EXT] Re: Coresight enablement on NXP ARMv8 device
On Fri, 14 Feb 2020 at 02:00, Era Tiwari era.tiwari@nxp.com wrote:
Thanks so much for all the useful pointers, with lot of instrumentation the drivers probes are getting called ow. And I an see sysfs entries in /sys/bus/Coresight/devices for Coresight funnel, ETM4 and ETF. This is so cool!
Indeed
root@s32g275bringup:/sys/bus/coresight/devices# ls 51009000.funnel 5100f000.funnel 51014000.etf 51440000.etm
Only 1 ETM is showing and as such I assume only 1 CPU is up and running. I suspect there is information missing here.
And what code base are you working with? I'm asking because the above listing is using the "old" notation that displays the DT memory mapped address. With a recent kernel you should get:
funnel0 funnel1 tmc_etf0 etmX
The funnel configuration seems good, I checked with the hardware documentation as well. As first step I want to read the ETM traces from ETF (16KB). Can I do this? Using sysfs.
You sure can.
Referring to the documentation at: Documemtation/trace/coresight.txt,
I tried to enable the source and sink as below: root@s32g275bringup:/sys/bus/coresight/devices# echo 1 > 51014000.etf/enable_sink root@s32g275bringup:/sys/bus/coresight/devices# echo 1 > 51440000.etm/enable_source [ 147.538256] tmc_enable_etf_sink_sysfs, called [ 147.542804] tmc_etb_enable_hw [ 147.546123] coresight-tmc 51014000.etf: TMC-ETB/ETF enabled [ 147.551671] funnel_enable_hw functl=701. address of functl=8895000 [ 147.557911] funnel_enable_hw functl=0 address of funnelpri=8895004 [ 147.564164] coresight-funnel 51009000.funnel: FUNNEL inport 0 enabled [ 147.570578] CS link enabled [ 147.573721] coresight-etm4x 51440000.etm: ETM tracing enabled [ 147.579422] coresight source enabled [ 147.583323] CSD dev enabled
This looks all good.
But I cannot read anything like mentioned as in etb/status, and the write pointer. Is this expected? Should I also expect an entry for ETB?
Disabled the source to stop the tracing. root@s32g275bringup:/sys/bus/coresight/devices# echo 0 > 51440000.etm/enable_source root@s32g275bringup:~# dd if=/dev/51014000.etf of=/test/trace_19feb [ 369.632730] tmc_open [ 369.635049] tmc_read_prepare drvdata->config_type=2 [ 369.865055] coresight-tmc 51014000.etf: TMC read end 32+0 records in 32+0 records out #
This usually happens when tracers get enabled but have nothing to trace. From where I stand things are working properly so far. As per my comment above a single ETM has been enabled and as such it is possible that nothing is currently running on that CPU, hence no trace.
The trace file we get, I tried to decode using ptmtohuman application on a Linux machine.
I strongly advise not using this tool unless you are very familiar with coresight. Work on enabling trace acquisition and decoding using perf, it will be time well invested.
Thanks, Mathieu
Some snips below. (seems something is grossly wrong : () Mispredict ERROR: Cannot recognize a packet header 0x08 ERROR: Proceed on guesswork ERROR: Cannot recognize a packet header 0x08 ERROR: Proceed on guesswork Context - Context ID = 0x0, VMID = 0x0, Exception level = EL0, Security = NS, 32-bit instruction
Commit - 1 ATOM - E Commit - 1 ATOM - E Commit - 1 ATOM - E Commit - 1 ATOM - E Commit - 1 Exception - exception type IRQ, address 0x0000ff800809cf04 Conditional flush Commit - 1 Address - Instruction address 0x0000ff800809ce20, Instruction set Aarch32 (Thumb ) Address - Instruction address 0x0000ff8008081a80, Instruction set Aarch32 (Thumb ) Complete decode of the trace stream
Will need your kind guidance here.
Regards Poonam