When looking at the required registers (once again, please refer to Mike's document, section 4.3.1 to 4.3.3) a lot of them are RO:
ETMv3/PTM: ETMIDR ETMv4: TRCIDR[0, ..., 13], TRCAUTHSTATUS
Some are RW but can easily be made RO when using the CS framework from Perf:
ETMv3/PTM: ETMTRACEID ETMv4: TRCTRACEIDR
In fact I remember having this conversation with Mike in San Francisco and nobody would cry if we were to let the framework decide the traceIDs configured on the tracers.
Anything that is RO can still be retrieved using the current sysFS driven method since their values don't change. That leaves us with the other RW registers:
ETMv3/PTM: ETMCR, ETMCCR ETMv4: TRCCONFIGR
The question is, what information is needed from these registers in order to do trace decoding?
I believe it was all there in cs-decode.pdf (attached for those who haven't seen it). Any omissions, please let me know.
I don't believe ETMCCR is a RW register.
Is there anything in there that is coming from the HW that can't be deduced otherwise?
There are no changes coming from the HW that haven't been programmed in at some point by SW (or by extneral debug but that's a separate issue). So your problem is limited to
- one-time discovery of the configuration
- tracking software updates to the registers where these are not also tracked by sync packets.
So for perf you would want to emit some kind of "configuration changed" event if you notice a configuration change that isn't discoverable through sync packets. The good news is in ETMv4 much more of the changes are tracked in sync packets. You can probably emit that at the end of the trace stream since the trace configuration isn't going to change mid-stream. The key thing is to have the perf subsystem emit that event before it allows any more changes to the configuration for that core, not wait for the user tool to (ages later) query the configuration via sysfs.
Al
From what I understand we are talking about user configurable options that could be communicated to the trace decoding library using other means than conveying the whole registers. Using a bitmap is the first option that comes to mind, i.e, if cycle accurate tracing is configured, bit X is set.
With the above in mind I need you guys to help me identify the mandatory information in those tracer registers that is needed for trace decoding. Once again we can discuss this further in our meeting tomorrow.
Thanks, Mathieu _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
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