Friends,
I'm reading section 3.3.4 (RAM Read Pointer Register) of the "CoreSight Trace Memory Controller Technical Reference Manual", revision r0p1 and I'm puzzled.
The second paragraph of the "Purpose" section reads as follow:
"The value written to this register must be a byte-address aligned to the width of the trace memory databus and to a frame boundary. For example, for 64-bit wide trace memory and 128-bit wide trace memory, the four LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must be 0s..."
So for 64 bit wide memory RRP can be set to values like 0, 8, 16, 24... for 128 bit 0, 16, 32, 48... and for 256 bit 0, 32, 64...
What is perplexing is the statement about the LSBs. Things work for 256 bit and 128 bit with 5 and 4 LSBs respectively but for 64 bit, it should be 3 and not 4 as mentioned.
Am I missing something here? Can someone double check me?
Thanks, Mathieu