Re: Timestamps always 0x0 on Xilinx Zynq Ultrascale+

Hi Al,

If you're lucky, the timestamp block is mapped into the memory space in the same way as the ETMs are, and the CoreSight driver framework could enable it. If you're unlucky, the timestamp block is hidden away in a secure debug area and can only be enabled by vendor firmware or JTAG debug.

Looks like I'm lucky indeed - the US+ datasheet mentions there's a TSGEN block in the memory map. Could you please elaborate on how the CS framework can enable it? I would suspect there are some coresight-timestamp-like bindings, but I can't see anything related. How can I tell the driver where the timestamp generator is mapped?

I appreciate your help! Regards, Wojciech