The existing mechanism to assign Trace ID values to sources is limited and does not scale for larger multicore / multi trace source systems.

The API introduces functions that reserve IDs based on availabilty represented by a coresight_trace_id_map structure. This records the used and free IDs in a bitmap.

CPU bound sources such as ETMs use the coresight_trace_id_get_cpu_id coresight_trace_id_put_cpu_id pair of functions. The API will record the ID associated with the CPU. This ensures that the same ID will be re-used while perf events are active on the CPU. The put_cpu_id function will pend release of the ID until all perf cs_etm sessions are complete.

For backward compatibility the functions will attempt to use the same CPU IDs as the legacy system would have used if these are still available.

Non-cpu sources, such as the STM can use coresight_trace_id_get_system_id / coresight_trace_id_put_system_id.

Signed-off-by: Mike Leach mike.leach@linaro.org --- drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 4 + .../hwtracing/coresight/coresight-trace-id.c | 225 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 154 ++++++++++++ include/linux/coresight-pmu.h | 10 + 5 files changed, 394 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h

diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..329a0c704b87 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ coresight-cfg-preload.o coresight-cfg-afdo.o \ - coresight-syscfg-configfs.o + coresight-syscfg-configfs.o coresight-trace-id.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f3068175ca9d..554a18039e10 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h"

static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); @@ -1804,6 +1805,9 @@ static int __init coresight_init(void) if (ret) goto exit_bus_unregister;

+ /* initialise the trace ID allocator */ + coresight_trace_id_init(); + /* initialise the coresight syscfg API */ ret = cscfg_init(); if (!ret) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c new file mode 100644 index 000000000000..8e05a244c9d6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Linaro Limited, All rights reserved. + * Author: Mike Leach mike.leach@linaro.org + */ +#include <linux/coresight-pmu.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +#include "coresight-trace-id.h" + +/* default trace ID map. Used for systems that do not require per sink mappings */ +static struct coresight_trace_id_map id_map_default; + +/* maintain a record of the current mapping of cpu IDs and pending releases per cpu */ +static DEFINE_PER_CPU(atomic_t, cpu_id); +static DECLARE_BITMAP(cpu_id_release_pending, NR_CPUS); + +/* perf session active counter */ +static atomic_t perf_cs_etm_session_active = ATOMIC_INIT(0); + +/* lock to protect id_map and cpu data */ +static DEFINE_SPINLOCK(id_map_lock); + +/* + * allocate new ID and set in use + * if @preferred_id is a valid id then try to use that value if available. + */ +static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *id_map, + int preferred_id) +{ + int id; + + /* for backwards compatibility reasons, cpu Ids may have a preferred value */ + if (IS_VALID_ID(preferred_id) && !test_bit(preferred_id, id_map->used_ids)) + id = preferred_id; + else { + /* skip reserved bit 0, look from bit 1 to CORESIGHT_TRACE_ID_RES_TOP */ + id = find_next_zero_bit(id_map->used_ids, 1, CORESIGHT_TRACE_ID_RES_TOP); + if (id >= CORESIGHT_TRACE_ID_RES_TOP) + return -EINVAL; + } + + /* mark as used */ + set_bit(id, id_map->used_ids); + return id; +} + +static void coresight_trace_id_free(int id, struct coresight_trace_id_map *id_map) +{ + if (WARN(!IS_VALID_ID(id), "%s: Invalid Trace ID %d\n", __func__, id)) + return; + if (WARN(!test_bit(id, id_map->used_ids), + "%s: Freeing unused ID %d\n", __func__, id)) + return; + clear_bit(id, id_map->used_ids); +} + +static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_map *id_map) +{ + if (WARN(!IS_VALID_ID(id), "%s: Invalid Trace ID %d\n", __func__, id)) + return; + set_bit(id, id_map->pend_rel_ids); +} + +/* release all pending IDs for all current maps & clear CPU associations */ +static void coresight_trace_id_release_all_pending(void) +{ + struct coresight_trace_id_map *id_map = &id_map_default; + unsigned long flags; + int cpu, bit; + + spin_lock_irqsave(&id_map_lock, flags); + for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_ID_RES_TOP) { + clear_bit(bit, id_map->used_ids); + clear_bit(bit, id_map->pend_rel_ids); + } + for_each_set_bit(cpu, cpu_id_release_pending, NR_CPUS) { + atomic_set(&per_cpu(cpu_id, cpu), 0); + clear_bit(cpu, cpu_id_release_pending); + } + spin_unlock_irqrestore(&id_map_lock, flags); +} + +static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + + /* check for existing allocation for this CPU */ + id = atomic_read(&per_cpu(cpu_id, cpu)); + if (id) + goto get_cpu_id_clr_pend; + + /* + * Find a new ID. + * + * Use legacy values where possible in the dynamic trace ID allocator to + * allow older tools to continue working if they are not upgraded at the same + * time as the kernel drivers. + * + * If the generated legacy ID is invalid, or not available then the next + * available dynamic ID will be used. + */ + id = coresight_trace_id_alloc_new_id(id_map, CORESIGHT_LEGACY_CPU_TRACE_ID(cpu)); + if (!IS_VALID_ID(id)) + goto get_cpu_id_out_unlock; + + /* allocate the new id to the cpu */ + atomic_set(&per_cpu(cpu_id, cpu), id); + +get_cpu_id_clr_pend: + /* we are (re)using this ID - so ensure it is not marked for release */ + clear_bit(cpu, cpu_id_release_pending); + clear_bit(id, id_map->pend_rel_ids); + +get_cpu_id_out_unlock: + spin_unlock_irqrestore(&id_map_lock, flags); + + return id; +} + +static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + /* check for existing allocation for this CPU */ + id = atomic_read(&per_cpu(cpu_id, cpu)); + if (!id) + return; + + spin_lock_irqsave(&id_map_lock, flags); + + if (atomic_read(&perf_cs_etm_session_active)) { + /* set release at pending if perf still active */ + coresight_trace_id_set_pend_rel(id, id_map); + set_bit(cpu, cpu_id_release_pending); + } else { + /* otherwise clear id */ + coresight_trace_id_free(id, id_map); + atomic_set(&per_cpu(cpu_id, cpu), 0); + } + + spin_unlock_irqrestore(&id_map_lock, flags); +} + +static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + id = coresight_trace_id_alloc_new_id(id_map, 0); + spin_unlock_irqrestore(&id_map_lock, flags); + + return id; +} + +static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map *id_map, int id) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + coresight_trace_id_free(id, id_map); + spin_unlock_irqrestore(&id_map_lock, flags); +} + +/* API functions */ + +int coresight_trace_id_get_cpu_id(int cpu) +{ + return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id); + +void coresight_trace_id_put_cpu_id(int cpu) +{ + coresight_trace_id_map_put_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id); + +int coresight_trace_id_read_cpu_id(int cpu) +{ + return atomic_read(&per_cpu(cpu_id, cpu)); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id); + +int coresight_trace_id_get_system_id(void) +{ + return coresight_trace_id_map_get_system_id(&id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id); + +void coresight_trace_id_put_system_id(int id) +{ + coresight_trace_id_map_put_system_id(&id_map_default, id); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); + +void coresight_trace_id_perf_start(void) +{ + atomic_inc(&perf_cs_etm_session_active); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); + +void coresight_trace_id_perf_stop(void) +{ + if (!atomic_dec_return(&perf_cs_etm_session_active)) + coresight_trace_id_release_all_pending(); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop); + +void coresight_trace_id_init(void) +{ + int cpu; + + /* initialise the atomic trace ID values */ + for_each_possible_cpu(cpu) + atomic_set(&per_cpu(cpu_id, cpu), 0); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_init); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h new file mode 100644 index 000000000000..1d27977346b3 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(C) 2022 Linaro Limited. All rights reserved. + * Author: Mike Leach mike.leach@linaro.org + */ + +#ifndef _CORESIGHT_TRACE_ID_H +#define _CORESIGHT_TRACE_ID_H + +/* + * Coresight trace ID allocation API + * + * With multi cpu systems, and more additional trace sources a scalable + * trace ID reservation system is required. + * + * The system will allocate Ids on a demand basis, and allow them to be + * released when done. + * + * In order to ensure that a consistent cpu / ID matching is maintained + * throughout a perf cs_etm event session - a session in progress flag will + * be maintained, and released IDs not cleared until the perf session is + * complete. This allows the same CPU to be re-allocated its prior ID. + * + * + * Trace ID maps will be created and initialised to prevent architecturally + * reserved IDs from being allocated. + * + * API permits multiple maps to be maintained - for large systems where + * different sets of cpus trace into different independent sinks. + */ + +#include <linux/bitops.h> +#include <linux/types.h> + + +/* architecturally we have 128 IDs some of which are reserved */ +#define CORESIGHT_TRACE_IDS_MAX 128 + +/* ID 0 is reserved */ +#define CORESIGHT_TRACE_ID_RES_0 0 + +/* ID 0x70 onwards are reserved */ +#define CORESIGHT_TRACE_ID_RES_TOP 0x70 + +/* check an ID is in the valid range */ +#define IS_VALID_ID(id) \ + ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP)) + +/** + * Trace ID map. + * + * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. + * Initialised so that the reserved IDs are permanently marked as in use. + * @pend_rel_ids: CPU IDs that have been released by the trace source but not yet marked + * as available, to allow re-allocation to the same CPU during a perf session. + */ +struct coresight_trace_id_map { + DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); + DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); +}; + +/* Allocate and release IDs for a single default trace ID map */ + +/** + * Read and optionally allocate a CoreSight trace ID and associate with a CPU. + * + * Function will read the current trace ID for the associated CPU, + * allocating an new ID if one is not currently allocated. + * + * Numeric ID values allocated use legacy allocation algorithm if possible, + * otherwise any available ID is used. + * + * @cpu: The CPU index to allocate for. + * + * return: CoreSight trace ID or -EINVAL if allocation impossible. + */ +int coresight_trace_id_get_cpu_id(int cpu); + +/** + * Release an allocated trace ID associated with the CPU. + * + * This will release the CoreSight trace ID associated with the CPU, + * unless a perf session is in operation. + * + * If a perf session is in operation then the ID will be marked as pending release. + * + * @cpu: The CPU index to release the associated trace ID. + */ +void coresight_trace_id_put_cpu_id(int cpu); + +/** + * Read the current allocated CoreSight Trace ID value for the CPU. + * + * Fast read of the current value that does not allocate if no ID allocated for the CPU. + + * Used in perf context where it is known that the value for the CPU will not be changing, + * when perf starts and event on a core and outputs the Trace ID for the CPU + * as a packet in the data file. IDs cannot change during a perf session. + * + * This function does not take the lock protecting the ID lists, avoiding locking dependency + * issues with perf locks. + * + * @cpu: The CPU index to read. + * + * return: current value, will be 0 if unallocated. + */ +int coresight_trace_id_read_cpu_id(int cpu); + +/** + * Allocate a CoreSight trace ID for a system component. + * + * Unconditionally allocates as Trace ID, without associating the ID with any CPU. + * + * Used to allocate IDs for system trace sources such as STM. + * + * return: Trace ID or -EINVAL if allocation is impossible. + */ +int coresight_trace_id_get_system_id(void); + +/** + * Release an allocated system trace ID. + * + * Unconditionally release a trace ID previously allocated to a system component. + * + * @id: value of trace ID allocated. + */ +void coresight_trace_id_put_system_id(int id); + +/* notifiers for perf session start and stop */ + +/** + * Notify the Trace ID allocator that a perf session is starting. + * + * Increase the perf session reference count - called by perf when setting up + * a trace event. + * + * This reference count is used by the ID allocator to ensure that trace IDs associated with + * a CPU cannot change or be released during a perf session. + */ +void coresight_trace_id_perf_start(void); + +/** + * Notify the ID allocator that a perf session is stopping. + * + * Decrease the perf session reference count. + * if this causes the count to go to zero, then all Trace IDs marked as pending release + * will be released. + */ +void coresight_trace_id_perf_stop(void); + +/* initialisation */ +void coresight_trace_id_init(void); + +#endif /* _CORESIGHT_TRACE_ID_H */ diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 6c2fd6cc5a98..ffff4e6277e5 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -10,6 +10,16 @@ #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10

+/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibility + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools that may not update at the same time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions.

Adds in calls to allocate and release Trace ID for the CPUs in use by the perf session.

Adds in notifier calls to the trace ID allocator that perf events are starting and stopping.

This ensures that Trace IDs associated with CPUs remain the same throughout the perf session, and are only released when all perf sessions are complete.

Signed-off-by: Mike Leach mike.leach@linaro.org --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 43bbd5dc3d3b..6166f716a6ac 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h"

static struct pmu etm_pmu; static bool etm_perf_up; @@ -228,8 +229,12 @@ static void free_event_data(struct work_struct *work) if (!(IS_ERR_OR_NULL(*ppath))) coresight_release_path(*ppath); *ppath = NULL; + coresight_trace_id_put_cpu_id(cpu); }

+ /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(); + free_percpu(event_data->path); kfree(event_data); } @@ -300,6 +305,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, { u32 id, cfg_hash; int cpu = event->cpu; + int trace_id; cpumask_t *mask; struct coresight_device *sink = NULL; struct coresight_device *user_sink = NULL, *last_sink = NULL; @@ -316,6 +322,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); }

+ /* tell the trace ID allocator that a perf event is starting up */ + coresight_trace_id_perf_start(); + /* check if user wants a coresight configuration selected */ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) { @@ -388,6 +397,13 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, continue; }

+ /* ensure we can allocate a trace ID for this CPU */ + trace_id = coresight_trace_id_get_cpu_id(cpu); + if (!IS_VALID_ID(trace_id)) { + cpumask_clear_cpu(cpu, mask); + continue; + } + *etm_event_cpu_path_ptr(event_data, cpu) = path; }

The trace ID API is now used to allocate trace IDs for ETM4.x / ETE devices.

For perf sessions, these will be allocated on enable, and released on disable.

For sysfs sessions, these will be allocated on enable, but only released on reset. This allows the sysfs session to interrogate the Trace ID used after the session is over - maintaining functional consistency with the previous allocation scheme.

The trace ID will also be allocated on read of the mgmt/trctraceid file. This ensures that if perf or sysfs read this before enabling trace, the value will be the one used for the trace session.

Trace ID initialisation is removed from the _probe() function.

Signed-off-by: Mike Leach mike.leach@linaro.org --- .../coresight/coresight-etm4x-core.c | 70 +++++++++++++++++-- .../coresight/coresight-etm4x-sysfs.c | 27 ++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + 3 files changed, 90 insertions(+), 10 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 80fefaba58ee..0e361d35c611 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -42,6 +42,7 @@ #include "coresight-etm4x-cfg.h" #include "coresight-self-hosted-trace.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h"

static int boot_enable; module_param(boot_enable, int, 0444); @@ -234,6 +235,30 @@ static int etm4_trace_id(struct coresight_device *csdev) return drvdata->trcid; }

+int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) +{ + int trace_id; + + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * The trace id function has its own lock + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_ID(trace_id)) + drvdata->trcid = (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return trace_id; +} + +void etm4_release_trace_id(struct etmv4_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu); +} + struct etm4_enable_arg { struct etmv4_drvdata *drvdata; int rc; @@ -717,7 +742,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, static int etm4_enable_perf(struct coresight_device *csdev, struct perf_event *event) { - int ret = 0; + int ret = 0, trace_id; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { @@ -729,6 +754,24 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_parse_event_config(csdev, event); if (ret) goto out; + + /* + * perf allocates cpu ids as part of _setup_aux() - device needs to use + * the allocated ID. This reads the current version without allocation. + * + * This does not use the trace id lock to prevent lock_dep issues + * with perf locks - we know the ID cannot change until perf shuts down + * the session + */ + trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); + if (!IS_VALID_ID(trace_id)) { + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + ret = -EINVAL; + goto out; + } + drvdata->trcid = (u8)trace_id; + /* And enable it */ ret = etm4_enable_hw(drvdata);

@@ -753,6 +796,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev)

spin_lock(&drvdata->spinlock);

+ /* sysfs needs to read and allocate a trace ID */ + ret = etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_sysfs_enable; + /* * Executing etm4_enable_hw on the cpu whose ETM is being enabled * ensures that register writes occur when cpu is powered. @@ -764,6 +812,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) ret = arg.rc; if (!ret) drvdata->sticky_enable = true; + + if (ret) + etm4_release_trace_id(drvdata); + +unlock_sysfs_enable: spin_unlock(&drvdata->spinlock);

if (!ret) @@ -895,6 +948,8 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9));

+ /* perf will release trace ids when _free_aux() is called at the end of the session */ + return 0; }

@@ -920,6 +975,13 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock();

+ /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); }

@@ -1562,11 +1624,6 @@ static int etm4_dying_cpu(unsigned int cpu) return 0; }

-static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) -{ - drvdata->trcid = coresight_get_trace_id(drvdata->cpu); -} - static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret = 0; @@ -1971,7 +2028,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) if (!desc.name) return -ENOMEM;

- etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config);

pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 9cac848cffaf..5e62aa40ecd0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -266,10 +266,11 @@ static ssize_t reset_store(struct device *dev, config->vmid_mask0 = 0x0; config->vmid_mask1 = 0x0;

- drvdata->trcid = drvdata->cpu + 1; - spin_unlock(&drvdata->spinlock);

+ /* for sysfs - only release trace id when resetting */ + etm4_release_trace_id(drvdata); + cscfg_csdev_reset_feats(to_coresight_device(dev));

return size; @@ -2392,6 +2393,26 @@ static struct attribute *coresight_etmv4_attrs[] = { NULL, };

+/* + * Trace ID allocated dynamically on enable - but also allocate on read + * in case sysfs or perf read before enable to ensure consistent metadata + * information for trace decode + */ +static ssize_t trctraceid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int trace_id; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + trace_id = etm4_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; + + return sysfs_emit(buf, "0x%x\n", trace_id); +} +static DEVICE_ATTR_RO(trctraceid); + struct etmv4_reg { struct coresight_device *csdev; u32 offset; @@ -2528,7 +2549,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { coresight_etm4x_reg(trcpidr3, TRCPIDR3), coresight_etm4x_reg(trcoslsr, TRCOSLSR), coresight_etm4x_reg(trcconfig, TRCCONFIGR), - coresight_etm4x_reg(trctraceid, TRCTRACEIDR), + &dev_attr_trctraceid.attr, coresight_etm4x_reg(trcdevarch, TRCDEVARCH), NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4b21bb79f168..434f4e95ee17 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1095,4 +1095,7 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) { return drvdata->arch >= ETM_ARCH_ETE; } + +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); +void etm4_release_trace_id(struct etmv4_drvdata *drvdata); #endif

CoreSight sources provide a callback (.trace_id) in the standard source ops which returns the ID to the core code. This was used to check that sources all had a unique Trace ID.

Uniqueness is now gauranteed by the Trace ID allocation system, and the check code has been removed from the core.

This patch removes the unneeded and unused .trace_id source ops from the ops structure and implementations in etm3x, etm4x and stm.

Signed-off-by: Mike Leach mike.leach@linaro.org Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com --- drivers/hwtracing/coresight/coresight-etm.h | 1 - .../coresight/coresight-etm3x-core.c | 37 ------------------- .../coresight/coresight-etm4x-core.c | 8 ---- drivers/hwtracing/coresight/coresight-stm.c | 8 ---- include/linux/coresight.h | 3 -- 5 files changed, 57 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 3667428d38b6..9a0d08b092ae 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -283,7 +283,6 @@ static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) }

extern const struct attribute_group *coresight_etm_groups[]; -int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 9a7a9e974d41..96b8b86bd436 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -455,42 +455,6 @@ static int etm_cpu_id(struct coresight_device *csdev) return drvdata->cpu; }

-int etm_get_trace_id(struct etm_drvdata *drvdata) -{ - unsigned long flags; - int trace_id = -1; - struct device *etm_dev; - - if (!drvdata) - goto out; - - etm_dev = drvdata->csdev->dev.parent; - if (!local_read(&drvdata->mode)) - return drvdata->traceid; - - pm_runtime_get_sync(etm_dev); - - spin_lock_irqsave(&drvdata->spinlock, flags); - - CS_UNLOCK(drvdata->base); - trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); - CS_LOCK(drvdata->base); - - spin_unlock_irqrestore(&drvdata->spinlock, flags); - pm_runtime_put(etm_dev); - -out: - return trace_id; - -} - -static int etm_trace_id(struct coresight_device *csdev) -{ - struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return etm_get_trace_id(drvdata); -} - int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) { int trace_id; @@ -734,7 +698,6 @@ static void etm_disable(struct coresight_device *csdev,

static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, - .trace_id = etm_trace_id, .enable = etm_enable, .disable = etm_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 0e361d35c611..edce9628916a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -228,13 +228,6 @@ static int etm4_cpu_id(struct coresight_device *csdev) return drvdata->cpu; }

-static int etm4_trace_id(struct coresight_device *csdev) -{ - struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return drvdata->trcid; -} - int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) { int trace_id; @@ -1015,7 +1008,6 @@ static void etm4_disable(struct coresight_device *csdev,

static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, - .trace_id = etm4_trace_id, .enable = etm4_enable, .disable = etm4_disable, }; diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 6af1b996af6f..66a614c5492c 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -281,15 +281,7 @@ static void stm_disable(struct coresight_device *csdev, } }

-static int stm_trace_id(struct coresight_device *csdev) -{ - struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return drvdata->traceid; -} - static const struct coresight_ops_source stm_source_ops = { - .trace_id = stm_trace_id, .enable = stm_enable, .disable = stm_disable, }; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 1554021231f9..e241eb88dfb9 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -314,14 +314,11 @@ struct coresight_ops_link { * Operations available for sources. * @cpu_id: returns the value of the CPU number this component * is associated to. - * @trace_id: returns the value of the component's trace ID as known - * to the HW. * @enable: enables tracing for a source. * @disable: disables tracing for a source. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); - int (*trace_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, u32 mode); void (*disable)(struct coresight_device *csdev,

The information to associate Trace ID and CPU will be changing.

Drivers will start outputting this as a hardware ID packet in the data file which if present will be used in preference to the AUXINFO values.

To prepare for this we provide a helper functions to do the individual ID mapping, and one to extract the IDs from the completed metadata blocks.

Signed-off-by: Mike Leach mike.leach@linaro.org Reviewed-by: James Clark james.clark@arm.com --- tools/include/linux/coresight-pmu.h | 5 ++ tools/perf/util/cs-etm.c | 92 +++++++++++++++++++---------- tools/perf/util/cs-etm.h | 14 ++++- 3 files changed, 77 insertions(+), 34 deletions(-)

diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 6c2fd6cc5a98..db9c7c0abb6a 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -7,9 +7,14 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H

+#include <linux/bits.h> + #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10

+/* CoreSight trace ID is currently the bottom 7 bits of the value */ +#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 16db965ac995..11026c9694a4 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -193,6 +193,30 @@ int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt) return 0; }

+static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata) +{ + struct int_node *inode; + + /* Get an RB node for this CPU */ + inode = intlist__findnew(traceid_list, trace_chan_id); + + /* Something went wrong, no need to continue */ + if (!inode) + return -ENOMEM; + + /* + * The node for that CPU should not be taken. + * Back out if that's the case. + */ + if (inode->priv) + return -EINVAL; + + /* All good, associate the traceID with the metadata pointer */ + inode->priv = cpu_metadata; + + return 0; +} + void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id) { @@ -2881,18 +2905,47 @@ static int cs_etm__queue_aux_records(struct perf_session *session) return 0; }

+/* map trace ids to correct metadata block, from information in metadata */ +static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) +{ + u64 cs_etm_magic; + u8 trace_chan_id; + int i, err; + + for (i = 0; i < num_cpu; i++) { + cs_etm_magic = metadata[i][CS_ETM_MAGIC]; + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + trace_chan_id = (u8)((metadata[i][CS_ETM_ETMTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + trace_chan_id = (u8)((metadata[i][CS_ETMV4_TRCTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + default: + /* unknown magic number */ + return -EINVAL; + } + err = cs_etm__map_trace_id(trace_chan_id, metadata[i]); + if (err) + return err; + } + return 0; +} + int cs_etm__process_auxtrace_info(union perf_event *event, struct perf_session *session) { struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; struct cs_etm_auxtrace *etm = NULL; - struct int_node *inode; unsigned int pmu_type; int event_header_size = sizeof(struct perf_event_header); int info_header_size; int total_size = auxtrace_info->header.size; int priv_size = 0; - int num_cpu, trcidr_idx; + int num_cpu; int err = 0; int i, j; u64 *ptr, *hdr = NULL; @@ -2962,23 +3015,13 @@ int cs_etm__process_auxtrace_info(union perf_event *event, cs_etm__create_meta_blk(ptr, &i, CS_ETM_PRIV_MAX, CS_ETM_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx = CS_ETM_ETMTRACEIDR; - } else if (ptr[i] == __perf_cs_etmv4_magic) { metadata[j] = cs_etm__create_meta_blk(ptr, &i, CS_ETMV4_PRIV_MAX, CS_ETMV4_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx = CS_ETMV4_TRCTRACEIDR; } else if (ptr[i] == __perf_cs_ete_magic) { metadata[j] = cs_etm__create_meta_blk(ptr, &i, CS_ETE_PRIV_MAX, -1); - - /* ETE shares first part of metadata with ETMv4 */ - trcidr_idx = CS_ETMV4_TRCTRACEIDR; } else { ui__error("CS ETM Trace: Unrecognised magic number %#"PRIx64". File could be from a newer version of perf.\n", ptr[i]); @@ -2990,26 +3033,6 @@ int cs_etm__process_auxtrace_info(union perf_event *event, err = -ENOMEM; goto err_free_metadata; } - - /* Get an RB node for this CPU */ - inode = intlist__findnew(traceid_list, metadata[j][trcidr_idx]); - - /* Something went wrong, no need to continue */ - if (!inode) { - err = -ENOMEM; - goto err_free_metadata; - } - - /* - * The node for that CPU should not be taken. - * Back out if that's the case. - */ - if (inode->priv) { - err = -EINVAL; - goto err_free_metadata; - } - /* All good, associate the traceID with the metadata pointer */ - inode->priv = metadata[j]; }

/* @@ -3090,6 +3113,11 @@ int cs_etm__process_auxtrace_info(union perf_event *event, if (err) goto err_delete_thread;

+ /* before aux records are queued, need to map metadata to trace IDs */ + err = cs_etm__map_trace_ids_metadata(num_cpu, metadata); + if (err) + goto err_delete_thread; + err = cs_etm__queue_aux_records(session); if (err) goto err_delete_thread; diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 90c83f932d9a..712a6f855f0e 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -28,13 +28,17 @@ enum { /* * Update the version for new format. * - * New version 1 format adds a param count to the per cpu metadata. + * Version 1: format adds a param count to the per cpu metadata. * This allows easy adding of new metadata parameters. * Requires that new params always added after current ones. * Also allows client reader to handle file versions that are different by * checking the number of params in the file vs the number expected. + * + * Version 2: Drivers will use PERF_RECORD_AUX_OUTPUT_HW_ID to output + * CoreSight Trace ID. ...TRACEIDR metadata will be set to unused ID. */ -#define CS_HEADER_CURRENT_VERSION 1 +#define CS_HEADER_CURRENT_VERSION 2 +#define CS_AUX_HW_ID_VERSION_MIN 2

/* Beginning of header common to both ETMv3 and V4 */ enum { @@ -85,6 +89,12 @@ enum { CS_ETE_PRIV_MAX };

+/* + * Check for valid CoreSight trace ID. If an invalid value is present in the metadata, + * then IDs are present in the hardware ID packet in the data file. + */ +#define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70)) + /* * ETMv3 exception encoding number: * See Embedded Trace Macrocell specification (ARM IHI 0014Q)

CoreSight trace being updated to use the perf_report_aux_output_id() in a similar way to intel-pt.

This function in needs export visibility to allow it to be called from kernel loadable modules, which CoreSight may configured to be built as.

Signed-off-by: Mike Leach mike.leach@linaro.org Acked-by: Suzuki K Poulose suzuki.poulose@arm.com --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/kernel/events/core.c b/kernel/events/core.c index 4ec3717003d5..ad388552f1d5 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -9231,6 +9231,7 @@ void perf_report_aux_output_id(struct perf_event *event, u64 hw_id)

perf_output_end(&handle); } +EXPORT_SYMBOL_GPL(perf_report_aux_output_id);

static int __perf_event_account_interrupt(struct perf_event *event, int throttle)

Use the perf_report_aux_output_id() call to output the CoreSight trace ID and associated CPU as a PERF_RECORD_AUX_OUTPUT_HW_ID record in the perf.data file.

Signed-off-by: Mike Leach mike.leach@linaro.org --- drivers/hwtracing/coresight/coresight-etm-perf.c | 7 +++++++ include/linux/coresight-pmu.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 6166f716a6ac..59a2ad95c1dc 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier mathieu.poirier@linaro.org */

+#include <linux/bitfield.h> #include <linux/coresight.h> #include <linux/coresight-pmu.h> #include <linux/cpumask.h> @@ -448,6 +449,7 @@ static void etm_event_start(struct perf_event *event, int flags) struct perf_output_handle *handle = &ctxt->handle; struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); struct list_head *path; + u64 hw_id;

if (!csdev) goto fail; @@ -493,6 +495,11 @@ static void etm_event_start(struct perf_event *event, int flags) if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path;

+ /* output cpu / trace ID in perf record */ + hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, CS_AUX_HW_ID_CURR_VERSION) | + FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, coresight_trace_id_read_cpu_id(cpu)); + perf_report_aux_output_id(event, hw_id); + out: /* Tell the perf core the event is alive */ event->hw.state = 0; diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 624f4843453e..51ac441a37c3 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -7,6 +7,8 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H

+#include <linux/bits.h> + #define CORESIGHT_ETM_PMU_NAME "cs_etm"

/* @@ -43,4 +45,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15

+/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 + #endif

Hi Mike

On 01/11/2022 16:30, Mike Leach wrote:

The existing mechanism to assign Trace ID values to sources is limited and does not scale for larger multicore / multi trace source systems.

The API introduces functions that reserve IDs based on availabilty represented by a coresight_trace_id_map structure. This records the used and free IDs in a bitmap.

CPU bound sources such as ETMs use the coresight_trace_id_get_cpu_id coresight_trace_id_put_cpu_id pair of functions. The API will record the ID associated with the CPU. This ensures that the same ID will be re-used while perf events are active on the CPU. The put_cpu_id function will pend release of the ID until all perf cs_etm sessions are complete.

For backward compatibility the functions will attempt to use the same CPU IDs as the legacy system would have used if these are still available.

Non-cpu sources, such as the STM can use coresight_trace_id_get_system_id / coresight_trace_id_put_system_id.

Signed-off-by: Mike Leach mike.leach@linaro.org

Thanks for the rework, patch looks good to me. Most of the comments are style related or nits.

The important one is about the allocation of trace id for system components, where a legacy_cpu_id(cpu) could be allocated to a system component. It would be good to skip this (and we can do that with minimal changes, see below).

There are many lines crossing the 80 characters width, please intend them if possible. Not strict about all of them, but some of the function definitions could be split into new lines.

---

drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 4 + .../hwtracing/coresight/coresight-trace-id.c | 225 ++++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 154 ++++++++++++ include/linux/coresight-pmu.h | 10 + 5 files changed, 394 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h

diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..329a0c704b87 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ coresight-cfg-preload.o coresight-cfg-afdo.o \

• coresight-syscfg-configfs.o
  

• coresight-syscfg-configfs.o coresight-trace-id.o
  

  obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f3068175ca9d..554a18039e10 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -22,6 +22,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); @@ -1804,6 +1805,9 @@ static int __init coresight_init(void) if (ret) goto exit_bus_unregister;

• /* initialise the trace ID allocator */
• coresight_trace_id_init();
• /* initialise the coresight syscfg API */ ret = cscfg_init(); if (!ret)

diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c new file mode 100644 index 000000000000..8e05a244c9d6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2022, Linaro Limited, All rights reserved.
• • Author: Mike Leach mike.leach@linaro.org
• */

+#include <linux/coresight-pmu.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/types.h>

+#include "coresight-trace-id.h"

+/* default trace ID map. Used for systems that do not require per sink mappings */ +static struct coresight_trace_id_map id_map_default;

+/* maintain a record of the current mapping of cpu IDs and pending releases per cpu */ +static DEFINE_PER_CPU(atomic_t, cpu_id);

We can statically initialise the cpu_id as below and get rid of the coresight_trace_id_init() altogether.

static DEFINE_PER_CPU(atomic_t, cpu_id) = ATOMIC_INIT(0);

+static DECLARE_BITMAP(cpu_id_release_pending, NR_CPUS);

If you do respin this, please consider switching to a cpumask_t. Apologies, should have said that this last time. Then, we could do :

for_each_cpu(cpu, &cpui_id_release_pending) { .. }

+/* perf session active counter */ +static atomic_t perf_cs_etm_session_active = ATOMIC_INIT(0);

+/* lock to protect id_map and cpu data */ +static DEFINE_SPINLOCK(id_map_lock);

+/*

• • allocate new ID and set in use
• • if @preferred_id is a valid id then try to use that value if available.
• */

+static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *id_map,

• 			   int preferred_id)
  

+{

• int id;
• /* for backwards compatibility reasons, cpu Ids may have a preferred value */
• if (IS_VALID_ID(preferred_id) && !test_bit(preferred_id, id_map->used_ids))

minor nit: line width exceeds 80.

if (IS_VALID_ID(preferred_id) && !test_bit(preferred_id, id_map->used_ids)) {

• id = preferred_id;
  

} else {

• else {

• /* skip reserved bit 0, look from bit 1 to CORESIGHT_TRACE_ID_RES_TOP */
  

• id = find_next_zero_bit(id_map->used_ids, 1, CORESIGHT_TRACE_ID_RES_TOP);
  

• if (id >= CORESIGHT_TRACE_ID_RES_TOP)
  

• 	return -EINVAL;
  

• }
• /* mark as used */
• set_bit(id, id_map->used_ids);
• return id;

+}

+static void coresight_trace_id_free(int id, struct coresight_trace_id_map *id_map) +{

• if (WARN(!IS_VALID_ID(id), "%s: Invalid Trace ID %d\n", __func__, id))

• return;
  

minor nit: __func__ is not be need as the WARN would already give you the file+line number of the warning and also a stack trace. This could simply be:

if (!WARN_ON(!IS_VALID_ID(id)) clear_bit(id, id_map->used_ids);

• if (WARN(!test_bit(id, id_map->used_ids),

•  "%s: Freeing unused ID %d\n", __func__, id))
  

• return;
  

• clear_bit(id, id_map->used_ids);

+}

+static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_map *id_map)

minor nit: exceeds 80

+{

• if (WARN(!IS_VALID_ID(id), "%s: Invalid Trace ID %d\n", __func__, id))

• return;
  

• set_bit(id, id_map->pend_rel_ids);

+}

+/* release all pending IDs for all current maps & clear CPU associations */

Minor nit: This function operates on the "default id map" and as such it may be a good idea to call that out in the comment or even in the function name to make it explicit. Every other function accepts an id_map.

+static void coresight_trace_id_release_all_pending(void) +{

• struct coresight_trace_id_map *id_map = &id_map_default;
• unsigned long flags;
• int cpu, bit;
• spin_lock_irqsave(&id_map_lock, flags);
• for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_ID_RES_TOP) {

• clear_bit(bit, id_map->used_ids);
  

• clear_bit(bit, id_map->pend_rel_ids);
  

• }
• for_each_set_bit(cpu, cpu_id_release_pending, NR_CPUS) {

• atomic_set(&per_cpu(cpu_id, cpu), 0);
  

• clear_bit(cpu, cpu_id_release_pending);
  

• }
• spin_unlock_irqrestore(&id_map_lock, flags);

+}

+static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map)

minor nit: Please split the line

+{

• unsigned long flags;
• int id;
• spin_lock_irqsave(&id_map_lock, flags);

• /* check for existing allocation for this CPU */
• id = atomic_read(&per_cpu(cpu_id, cpu));
• if (id)

Please could we use coresight_trace_id_read_cpu_id() ? i.e Could we keep the code abstracted as much as possible, than open coding at different places ?

i.e.,

id = coresight_trace_id_read_cpu_id()

we could move the definition around. That way, it is easier to fix potential changes in the future.

• goto get_cpu_id_clr_pend;
  

• /*

• * Find a new ID.
  

• *
  

• * Use legacy values where possible in the dynamic trace ID allocator to
  

• * allow older tools to continue working if they are not upgraded at the same
  

• * time as the kernel drivers.
  

• *
  

• * If the generated legacy ID is invalid, or not available then the next
  

• * available dynamic ID will be used.
  

• */
  

Thanks, this will help the legacy perf tools. One question here though. In order to make sure we get the legacy allocated to CPUs, do we need to tweak the "get_system_id" to "prefer" "odd" traceIDs ? e.g., I see that the TPDA requests a trace-id at "probe" time and keeps that forever. If the TPDA gets to the trace-id first and gets the trace-id of CPU0, we may break the legacy id scheme here. We could live with it, but having this sort of a scheme may help to avoid the situation.

e.g., we could use

coresight_trace_id_alloc_preferred(id_map, CORESIGHT_LEGACY_CPU_TRACE_ID(cpu));

where:

coresight_trace_id_alloc_mask(id_map, mask, match) { for_each_clear_bit(id, id_map->used_ids) { if ((id & mask) == match) allocate_id and return id; } }

coresight_trace_id_alloc_new_id(id_map) { return coresight_trace_id_alloc_mask(id_map, 0, 0); }

coresight_trace_id_alloc_preferred(id_map, preferred) { if (prefered is free) { allocate preferred and mark as used; } else { coresight_trace_id_alloc_new_id(id_map); } }

/* Prefer Odd traceid values for system components) */ coresight_trace_id_alloc_mask(id_map, 0x1, 0x1);

Thoughts ?

• id = coresight_trace_id_alloc_new_id(id_map, CORESIGHT_LEGACY_CPU_TRACE_ID(cpu));
• if (!IS_VALID_ID(id))

• goto get_cpu_id_out_unlock;
  

• /* allocate the new id to the cpu */
• atomic_set(&per_cpu(cpu_id, cpu), id);

+get_cpu_id_clr_pend:

• /* we are (re)using this ID - so ensure it is not marked for release */
• clear_bit(cpu, cpu_id_release_pending);
• clear_bit(id, id_map->pend_rel_ids);

+get_cpu_id_out_unlock:

• spin_unlock_irqrestore(&id_map_lock, flags);
• return id;

+}

+static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{

• unsigned long flags;
• int id;
• /* check for existing allocation for this CPU */
• id = atomic_read(&per_cpu(cpu_id, cpu));

same as above, coresight_trace_id_read_cpu_id();

• if (!id)

• return;
  

• spin_lock_irqsave(&id_map_lock, flags);
• if (atomic_read(&perf_cs_etm_session_active)) {

• /* set release at pending if perf still active */
  

• coresight_trace_id_set_pend_rel(id, id_map);
  

• set_bit(cpu, cpu_id_release_pending);
  

• } else {

• /* otherwise clear id */
  

• coresight_trace_id_free(id, id_map);
  

• atomic_set(&per_cpu(cpu_id, cpu), 0);
  

• }
• spin_unlock_irqrestore(&id_map_lock, flags);

+}

+static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map) +{

• unsigned long flags;
• int id;
• spin_lock_irqsave(&id_map_lock, flags);
• id = coresight_trace_id_alloc_new_id(id_map, 0);
• spin_unlock_irqrestore(&id_map_lock, flags);
• return id;

+}

+static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map *id_map, int id) +{

• unsigned long flags;
• spin_lock_irqsave(&id_map_lock, flags);
• coresight_trace_id_free(id, id_map);
• spin_unlock_irqrestore(&id_map_lock, flags);

+}

+/* API functions */

+int coresight_trace_id_get_cpu_id(int cpu) +{

• return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default);

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id);

+void coresight_trace_id_put_cpu_id(int cpu) +{

• coresight_trace_id_map_put_cpu_id(cpu, &id_map_default);

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id);

+int coresight_trace_id_read_cpu_id(int cpu) +{

• return atomic_read(&per_cpu(cpu_id, cpu));

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id);

+int coresight_trace_id_get_system_id(void) +{

• return coresight_trace_id_map_get_system_id(&id_map_default);

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id);

+void coresight_trace_id_put_system_id(int id) +{

• coresight_trace_id_map_put_system_id(&id_map_default, id);

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id);

+void coresight_trace_id_perf_start(void) +{

• atomic_inc(&perf_cs_etm_session_active);

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start);

+void coresight_trace_id_perf_stop(void) +{

• if (!atomic_dec_return(&perf_cs_etm_session_active))

• coresight_trace_id_release_all_pending();
  

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop);

+void coresight_trace_id_init(void) +{

• int cpu;
• /* initialise the atomic trace ID values */
• for_each_possible_cpu(cpu)

• atomic_set(&per_cpu(cpu_id, cpu), 0);
  

+} +EXPORT_SYMBOL_GPL(coresight_trace_id_init);

As mentioned above, we could remove this.

diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h new file mode 100644 index 000000000000..1d27977346b3 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright(C) 2022 Linaro Limited. All rights reserved.
• • Author: Mike Leach mike.leach@linaro.org
• */

+#ifndef _CORESIGHT_TRACE_ID_H +#define _CORESIGHT_TRACE_ID_H

+/*

• • Coresight trace ID allocation API
• • With multi cpu systems, and more additional trace sources a scalable
• • trace ID reservation system is required.
• • The system will allocate Ids on a demand basis, and allow them to be
• • released when done.
• • In order to ensure that a consistent cpu / ID matching is maintained
• • throughout a perf cs_etm event session - a session in progress flag will
• • be maintained, and released IDs not cleared until the perf session is
• • complete. This allows the same CPU to be re-allocated its prior ID.
• • Trace ID maps will be created and initialised to prevent architecturally
• • reserved IDs from being allocated.
• • API permits multiple maps to be maintained - for large systems where
• • different sets of cpus trace into different independent sinks.
• */

+#include <linux/bitops.h> +#include <linux/types.h>

+/* architecturally we have 128 IDs some of which are reserved */ +#define CORESIGHT_TRACE_IDS_MAX 128

+/* ID 0 is reserved */ +#define CORESIGHT_TRACE_ID_RES_0 0

+/* ID 0x70 onwards are reserved */ +#define CORESIGHT_TRACE_ID_RES_TOP 0x70

super minor nit: Could we make this CORESIGHT_TRACE_ID_MAX ?

Rest looks fine to me.

Suzuki

On 01/11/2022 16:30, Mike Leach wrote:

The trace ID API is now used to allocate trace IDs for ETM4.x / ETE devices.

For perf sessions, these will be allocated on enable, and released on disable.

For sysfs sessions, these will be allocated on enable, but only released on reset. This allows the sysfs session to interrogate the Trace ID used after the session is over - maintaining functional consistency with the previous allocation scheme.

The trace ID will also be allocated on read of the mgmt/trctraceid file. This ensures that if perf or sysfs read this before enabling trace, the value will be the one used for the trace session.

Trace ID initialisation is removed from the _probe() function.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../coresight/coresight-etm4x-core.c | 70 +++++++++++++++++-- .../coresight/coresight-etm4x-sysfs.c | 27 ++++++- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + 3 files changed, 90 insertions(+), 10 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 80fefaba58ee..0e361d35c611 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -42,6 +42,7 @@ #include "coresight-etm4x-cfg.h" #include "coresight-self-hosted-trace.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static int boot_enable; module_param(boot_enable, int, 0444); @@ -234,6 +235,30 @@ static int etm4_trace_id(struct coresight_device *csdev) return drvdata->trcid; } +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) +{

• int trace_id;
• /*

• * This will allocate a trace ID to the cpu,
  

• * or return the one currently allocated.
  

• * The trace id function has its own lock
  

• */
  

• trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
• if (IS_VALID_ID(trace_id))

• drvdata->trcid = (u8)trace_id;
  

• else

• dev_err(&drvdata->csdev->dev,
  

• 	"Failed to allocate trace ID for %s on CPU%d\n",
  

• 	dev_name(&drvdata->csdev->dev), drvdata->cpu);
  

• return trace_id;

+}

+void etm4_release_trace_id(struct etmv4_drvdata *drvdata) +{

• coresight_trace_id_put_cpu_id(drvdata->cpu);

+}

• struct etm4_enable_arg { struct etmv4_drvdata *drvdata; int rc;

@@ -717,7 +742,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, static int etm4_enable_perf(struct coresight_device *csdev, struct perf_event *event) {

• int ret = 0;

• int ret = 0, trace_id; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { @@ -729,6 +754,24 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_parse_event_config(csdev, event); if (ret) goto out;

• /*

• * perf allocates cpu ids as part of _setup_aux() - device needs to use
  

• * the allocated ID. This reads the current version without allocation.
  

• *
  

• * This does not use the trace id lock to prevent lock_dep issues
  

• * with perf locks - we know the ID cannot change until perf shuts down
  

• * the session
  

• */
  

• trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu);
• if (!IS_VALID_ID(trace_id)) {

• dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
  

• 	dev_name(&drvdata->csdev->dev), drvdata->cpu);
  

• ret = -EINVAL;
  

• goto out;
  

• }
• drvdata->trcid = (u8)trace_id;
• /* And enable it */ ret = etm4_enable_hw(drvdata);

@@ -753,6 +796,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock);

• /* sysfs needs to read and allocate a trace ID */
• ret = etm4_read_alloc_trace_id(drvdata);
• if (ret < 0)

• goto unlock_sysfs_enable;
  

• /*
  • Executing etm4_enable_hw on the cpu whose ETM is being enabled
  • ensures that register writes occur when cpu is powered.

@@ -764,6 +812,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) ret = arg.rc; if (!ret) drvdata->sticky_enable = true;

• if (ret)

• etm4_release_trace_id(drvdata);
  

+unlock_sysfs_enable: spin_unlock(&drvdata->spinlock); if (!ret) @@ -895,6 +948,8 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9));

• /* perf will release trace ids when _free_aux() is called at the end of the session */

minor nit: Please split this to multi-line.

With that:

Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com

On 01/11/2022 16:31, Mike Leach wrote:

Use the perf_report_aux_output_id() call to output the CoreSight trace ID and associated CPU as a PERF_RECORD_AUX_OUTPUT_HW_ID record in the perf.data file.

Signed-off-by: Mike Leach mike.leach@linaro.org

Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-etm-perf.c | 7 +++++++ include/linux/coresight-pmu.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 6166f716a6ac..59a2ad95c1dc 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -4,6 +4,7 @@

• Author: Mathieu Poirier mathieu.poirier@linaro.org

*/ +#include <linux/bitfield.h> #include <linux/coresight.h> #include <linux/coresight-pmu.h> #include <linux/cpumask.h> @@ -448,6 +449,7 @@ static void etm_event_start(struct perf_event *event, int flags) struct perf_output_handle *handle = &ctxt->handle; struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); struct list_head *path;

• u64 hw_id;

if (!csdev) goto fail; @@ -493,6 +495,11 @@ static void etm_event_start(struct perf_event *event, int flags) if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path;

• /* output cpu / trace ID in perf record */
• hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, CS_AUX_HW_ID_CURR_VERSION) |

• FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, coresight_trace_id_read_cpu_id(cpu));
  

super minor nit: You may split this for better readability.

traceid = coresight_trace_id_read_cpu_id(cpu);

hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, CS_AUX_HW_ID_CURR_VERSION); hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, traceid);

Either ways,

Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com

On 01/11/2022 16:31, Mike Leach wrote:

Adds in a number of pr_debug macros to allow the debugging and test of the trace ID allocation system.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../hwtracing/coresight/coresight-trace-id.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c index 8e05a244c9d6..1588bad60715 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -64,6 +64,27 @@ static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_ma set_bit(id, id_map->pend_rel_ids); } +/* #define TRACE_ID_DEBUG 1 */ +#ifdef TRACE_ID_DEBUG

+static void coresight_trace_id_dump_table(struct coresight_trace_id_map *id_map,

• 			  const char *func_name)
  

+{

• pr_debug("%s id_map::\n", func_name);
• pr_debug("Avial= %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->used_ids);

minor nit: "Avail". Rather, shouldn't it be "Used" ?

Otherwise, the code looks good to me. The only concern is, the code could be stale without actually getting compiled. Could we turn this to may be:

#if defined(TRACE_ID_DEBUG) || defined(CONFIG_COMPILE_TEST)

or even tie this to a CONFIG, so that the code can be tested.

e.g., CONFIG_CORESIGHT_DEBUG_TRACEID depending on the DEBUG_KERNEL

Suzuki

• pr_debug("Pend = %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->pend_rel_ids);

+} +#define DUMP_ID_MAP(map) coresight_trace_id_dump_table(map, __func__) +#define DUMP_ID_CPU(cpu, id) pr_debug("%s called; cpu=%d, id=%d\n", __func__, cpu, id) +#define DUMP_ID(id) pr_debug("%s called; id=%d\n", __func__, id) +#define PERF_SESSION(n) pr_debug("%s perf count %d\n", __func__, n) +#else +#define DUMP_ID_MAP(map) +#define DUMP_ID(id) +#define DUMP_ID_CPU(cpu, id) +#define PERF_SESSION(n) +#endif

• /* release all pending IDs for all current maps & clear CPU associations */ static void coresight_trace_id_release_all_pending(void) {

@@ -81,6 +102,7 @@ static void coresight_trace_id_release_all_pending(void) clear_bit(cpu, cpu_id_release_pending); } spin_unlock_irqrestore(&id_map_lock, flags);

• DUMP_ID_MAP(id_map); }

static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map) @@ -120,6 +142,8 @@ static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_ get_cpu_id_out_unlock: spin_unlock_irqrestore(&id_map_lock, flags);

• DUMP_ID_CPU(cpu, id);
• DUMP_ID_MAP(id_map); return id; }

@@ -146,6 +170,8 @@ static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id } spin_unlock_irqrestore(&id_map_lock, flags);

• DUMP_ID_CPU(cpu, id);
• DUMP_ID_MAP(id_map); }

static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map) @@ -157,6 +183,8 @@ static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *i id = coresight_trace_id_alloc_new_id(id_map, 0); spin_unlock_irqrestore(&id_map_lock, flags);

• DUMP_ID(id);
• DUMP_ID_MAP(id_map); return id; }

@@ -167,6 +195,9 @@ static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map * spin_lock_irqsave(&id_map_lock, flags); coresight_trace_id_free(id, id_map); spin_unlock_irqrestore(&id_map_lock, flags);

• DUMP_ID(id);
• DUMP_ID_MAP(id_map); }

/* API functions */ @@ -204,6 +235,7 @@ EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); void coresight_trace_id_perf_start(void) { atomic_inc(&perf_cs_etm_session_active);

• PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start);

@@ -211,6 +243,7 @@ void coresight_trace_id_perf_stop(void) { if (!atomic_dec_return(&perf_cs_etm_session_active)) coresight_trace_id_release_all_pending();

• PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop);