CoreSight

coresight@lists.linaro.org

6 participants
2339 discussions

[PATCH v2] coresight: tmc: fix failure to disable/enable ETF after reading

by Mao Jinlong

ETF may fail to re-enable after reading, and driver->reading will not be set to false, this will cause failure to enable/disable to ETF. This change set driver->reading to false even if re-enabling fail. Fixes: 669c4614236a ("coresight: tmc: Don't enable TMC when it's not ready.") Co-developed-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d858740001c2..c9e2d95ae295 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -747,7 +747,6 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) char *buf = NULL; enum tmc_mode mode; unsigned long flags; - int rc = 0; /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB && @@ -773,11 +772,7 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) * can't be NULL. */ memset(drvdata->buf, 0, drvdata->size); - rc = __tmc_etb_enable_hw(drvdata); - if (rc) { - raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); - return rc; - } + __tmc_etb_enable_hw(drvdata); } else { /* * The ETB/ETF is not tracing and the buffer was just read. -- 2.25.1

1 hour, 39 minutes

[PATCH v2 0/9] coresight: Fix and improve clock usage

by Leo Yan

This series fixes and improves clock usage in the Arm CoreSight drivers. Based on the DT binding documents, the trace clock (atclk) is defined in some CoreSight modules, but support is absent. In most cases, the issue is hidden because the atclk clock is shared by multiple CoreSight modules and the clock is enabled anyway by other drivers. The first three patches address this issue. The programming clock (pclk) management in CoreSight drivers does not use the devm_XXX() variant APIs, the drivers needs to manually disable and release clocks for errors and for normal module exit. However, the drivers miss to disable clocks during module exit. The atclk may also not be disabled in CoreSight drivers during module exit. By using devm APIs, patches 04 and 05 fix clock disabling issues. Another issue is pclk might be enabled twice in init phase - once by AMBA bus driver, and again by CoreSight drivers. This is fixed in patch 06. Patches 07 to 09 refactor the clock related code. Patch 07 consolidats the clock initialization into a central place. Patch 08 makes the clock enabling sequence consistent. Patch 09 removes redundant condition checks and adds error handling in runtime PM. This series is verified on Arm64 Hikey960 platform. Changes from v1: - Moved the coresight_get_enable_clocks() function into CoreSight core layer (James). - Added comments for clock naming "apb_pclk" and "apb" (James). - Re-ordered patches for easier understanding (Anshuman). - Minor improvement for commit log in patch 01 (Anshuman). Leo Yan (9): coresight: tmc: Support atclk coresight: catu: Support atclk coresight: etm4x: Support atclk coresight: Disable programming clock properly coresight: Disable trace bus clock properly coresight: Avoid enable programming clock duplicately coresight: Consolidate clock enabling coresight: Make clock sequence consistent coresight: Refactor runtime PM drivers/hwtracing/coresight/coresight-catu.c | 53 ++++++++++++++++----------------- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 45 ++++++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-cpu-debug.c | 41 +++++++++----------------- drivers/hwtracing/coresight/coresight-ctcu-core.c | 24 +++++---------- drivers/hwtracing/coresight/coresight-etb10.c | 18 ++++-------- drivers/hwtracing/coresight/coresight-etm3x-core.c | 17 ++++------- drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 ++++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++- drivers/hwtracing/coresight/coresight-funnel.c | 66 +++++++++++++++--------------------------- drivers/hwtracing/coresight/coresight-replicator.c | 63 ++++++++++++++-------------------------- drivers/hwtracing/coresight/coresight-stm.c | 34 +++++++++------------- drivers/hwtracing/coresight/coresight-tmc-core.c | 48 +++++++++++++++--------------- drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ drivers/hwtracing/coresight/coresight-tpiu.c | 36 ++++++++++------------- include/linux/coresight.h | 30 ++----------------- 16 files changed, 225 insertions(+), 289 deletions(-) -- 2.34.1

2 hours, 16 minutes

[PATCH v3 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace form subsystems and transfers to coresight sink. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 ++++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 186 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.h | 34 ++++ 5 files changed, 345 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

3 hours, 50 minutes

[PATCH v2] coresight: Disable MMIO logging for coresight stm driver

by Mao Jinlong

With MMIO logging enabled, the MMIO access are traced and could be sent to an STM device. Thus, an STM driver MMIO access could create circular call chain with MMIO logging. Disable it for STM driver. [] stm_source_write[stm_core]+0xc4 [] stm_ftrace_write[stm_ftrace]+0x40 [] trace_event_buffer_commit+0x238 [] trace_event_raw_event_rwmmio_rw_template+0x8c [] log_post_write_mmio+0xb4 [] writel_relaxed[coresight_stm]+0x80 [] stm_generic_packet[coresight_stm]+0x1a8 [] stm_data_write[stm_core]+0x78 [] stm_source_write[stm_core]+0x7c [] stm_ftrace_write[stm_ftrace]+0x40 [] trace_event_buffer_commit+0x238 [] trace_event_raw_event_rwmmio_read+0x84 [] log_read_mmio+0xac [] readl_relaxed[coresight_tmc]+0x50 Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> Reviewed-by: Leo Yan <leo.yan(a)arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual(a)arm.com> --- Changes in V2: update the commit message drivers/hwtracing/coresight/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b31..f3158266f75e 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -22,6 +22,8 @@ condflags := \ $(call cc-option, -Wstringop-truncation) subdir-ccflags-y += $(condflags) +CFLAGS_coresight-stm.o := -D__DISABLE_TRACE_MMIO__ + obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ -- 2.25.1

20 hours, 57 minutes

[PATCH] coresight: replicator: Fix panic for clearing claim tag

by Leo Yan

On platforms with a static replicator, a kernel panic occurs during boot: [ 4.999406] replicator_probe+0x1f8/0x360 [ 5.003455] replicator_platform_probe+0x64/0xd8 [ 5.008115] platform_probe+0x70/0xf0 [ 5.011812] really_probe+0xc4/0x2a8 [ 5.015417] __driver_probe_device+0x80/0x140 [ 5.019813] driver_probe_device+0xe4/0x170 [ 5.024032] __driver_attach+0x9c/0x1b0 [ 5.027900] bus_for_each_dev+0x7c/0xe8 [ 5.031769] driver_attach+0x2c/0x40 [ 5.035373] bus_add_driver+0xec/0x218 [ 5.039154] driver_register+0x68/0x138 [ 5.043023] __platform_driver_register+0x2c/0x40 [ 5.047771] coresight_init_driver+0x4c/0xe0 [ 5.052079] replicator_init+0x30/0x48 [ 5.055865] do_one_initcall+0x4c/0x280 [ 5.059736] kernel_init_freeable+0x1ec/0x3c8 [ 5.064134] kernel_init+0x28/0x1f0 [ 5.067655] ret_from_fork+0x10/0x20 A static replicator doesn't have registers, so accessing the claim register results in a NULL pointer deference. Fixes the issue by accessing the claim registers only after the I/O resource has been successfully mapped. Fixes: 6f4c6f70575f ("coresight: Clear self hosted claim tag on probe") Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- drivers/hwtracing/coresight/coresight-replicator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index f1d2f764e898..06efd2b01a0f 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -262,6 +262,7 @@ static int replicator_probe(struct device *dev, struct resource *res) drvdata->base = base; desc.groups = replicator_groups; desc.access = CSDEV_ACCESS_IOMEM(base); + coresight_clear_self_claim_tag(&desc.access); } if (fwnode_property_present(dev_fwnode(dev), @@ -284,7 +285,6 @@ static int replicator_probe(struct device *dev, struct resource *res) desc.pdata = dev->platform_data; desc.dev = dev; - coresight_clear_self_claim_tag(&desc.access); drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) { ret = PTR_ERR(drvdata->csdev); -- 2.34.1

21 hours, 11 minutes

[PATCH v4 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace form subsystems and transfers to coresight sink. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 ++++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 191 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.h | 34 ++++ 5 files changed, 350 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

22 hours, 15 minutes

Re: [PATCH v2 1/2] dt-bindings: arm: Add Qualcomm extended CTI

by Jinlong Mao

On 2025/5/2 14:43, Krzysztof Kozlowski wrote: > On Tue, Apr 29, 2025 at 12:18:40AM GMT, Mao Jinlong wrote: >> Add Qualcomm extended CTI support in CTI binding file. Qualcomm >> extended CTI supports up to 128 triggers. >> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> index 2d5545a2b49c..1aa27461f5bc 100644 >> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >> @@ -84,7 +84,9 @@ properties: >> - const: arm,coresight-cti >> - const: arm,primecell >> - items: >> - - const: arm,coresight-cti-v8-arch >> + - enum: >> + - arm,coresight-cti-v8-arch >> + - qcom,coresight-cti-extended > > cpu phandle is not required? Or not even valid? cpu phandle is not required for exteneded CTI. > > Best regards, > Krzysztof >

1 day, 1 hour

Re: [PATCH v3] perf: Allocate non-contiguous AUX pages by default

by Anshuman Khandual

On 5/2/25 23:00, Yabin Cui wrote: > On Fri, May 2, 2025 at 3:51 AM Anshuman Khandual > <anshuman.khandual(a)arm.com> wrote: >> >> On 5/2/25 01:05, Yabin Cui wrote: >>> perf always allocates contiguous AUX pages based on aux_watermark. >>> However, this contiguous allocation doesn't benefit all PMUs. For >>> instance, ARM SPE and TRBE operate with virtual pages, and Coresight >>> ETR allocates a separate buffer. For these PMUs, allocating contiguous >>> AUX pages unnecessarily exacerbates memory fragmentation. This >>> fragmentation can prevent their use on long-running devices. >>> >>> This patch modifies the perf driver to be memory-friendly by default, >>> by allocating non-contiguous AUX pages. For PMUs requiring contiguous >>> pages (Intel BTS and some Intel PT), the existing >>> PERF_PMU_CAP_AUX_NO_SG capability can be used. For PMUs that don't >>> require but can benefit from contiguous pages (some Intel PT), a new >>> capability, PERF_PMU_CAP_AUX_PREFER_LARGE, is added to maintain their >>> existing behavior. >>> >>> Signed-off-by: Yabin Cui <yabinc(a)google.com> >>> --- >>> Changes since v2: >>> Let NO_SG imply PREFER_LARGE. So PMUs don't need to set both flags. >>> Then the only place needing PREFER_LARGE is intel/pt.c. >>> >>> Changes since v1: >>> In v1, default is preferring contiguous pages, and add a flag to >>> allocate non-contiguous pages. In v2, default is allocating >>> non-contiguous pages, and add a flag to prefer contiguous pages. >>> >>> v1 patchset: >>> perf,coresight: Reduce fragmentation with non-contiguous AUX pages for >>> cs_etm >>> >>> arch/x86/events/intel/pt.c | 2 ++ >>> include/linux/perf_event.h | 1 + >>> kernel/events/ring_buffer.c | 20 +++++++++++++------- >>> 3 files changed, 16 insertions(+), 7 deletions(-) >>> >>> diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c >>> index fa37565f6418..25ead919fc48 100644 >>> --- a/arch/x86/events/intel/pt.c >>> +++ b/arch/x86/events/intel/pt.c >>> @@ -1863,6 +1863,8 @@ static __init int pt_init(void) >>> >>> if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) >>> pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG; >>> + else >>> + pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_PREFER_LARGE; >>> >>> pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | >>> PERF_PMU_CAP_ITRACE | >> >> Why this PMU has PERF_PMU_CAP_AUX_PREFER_LARGE fallback option but >> not the other PMU in arch/x86/events/intel/bts.c even though both >> had PERF_PMU_CAP_AUX_NO_SG ? > > Because Intel BTS always use NO_SG, while in some cases Intel PT > doesn't use NO_SG. Makes sense. >> >>> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h >>> index 0069ba6866a4..56d77348c511 100644 >>> --- a/include/linux/perf_event.h >>> +++ b/include/linux/perf_event.h >>> @@ -301,6 +301,7 @@ struct perf_event_pmu_context; >>> #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 >>> #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 >>> #define PERF_PMU_CAP_AUX_PAUSE 0x0200 >>> +#define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 >>> >>> /** >>> * pmu::scope >>> diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c >>> index 5130b119d0ae..4d2f1c95673e 100644 >>> --- a/kernel/events/ring_buffer.c >>> +++ b/kernel/events/ring_buffer.c >>> @@ -679,7 +679,7 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, >>> { >>> bool overwrite = !(flags & RING_BUFFER_WRITABLE); >>> int node = (event->cpu == -1) ? -1 : cpu_to_node(event->cpu); >>> - int ret = -ENOMEM, max_order; >>> + int ret = -ENOMEM, max_order = 0; >> >> 0 order is now the default allocation granularity. This might benefit >> from a comment above explaining that max_order could change only with >> PERF_PMU_CAP_AUX_NO_SG or PERF_PMU_CAP_AUX_PREFER_LARGE PMU flags etc. >> > Will add the comment in the next respin. >>> >>> if (!has_aux(event)) >>> return -EOPNOTSUPP; >>> @@ -689,8 +689,8 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, >>> >>> if (!overwrite) { >>> /* >>> - * Watermark defaults to half the buffer, and so does the >>> - * max_order, to aid PMU drivers in double buffering. >>> + * Watermark defaults to half the buffer, to aid PMU drivers >>> + * in double buffering. >>> */ >>> if (!watermark) >>> watermark = min_t(unsigned long, >>> @@ -698,16 +698,22 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, >>> (unsigned long)nr_pages << (PAGE_SHIFT - 1)); >>> >>> /* >>> - * Use aux_watermark as the basis for chunking to >>> + * For PMUs that need or prefer large contiguous buffers, >>> + * use aux_watermark as the basis for chunking to >>> * help PMU drivers honor the watermark. >>> */ >>> - max_order = get_order(watermark); >>> + if (event->pmu->capabilities & (PERF_PMU_CAP_AUX_NO_SG | >>> + PERF_PMU_CAP_AUX_PREFER_LARGE)) >>> + max_order = get_order(watermark); >>> } else { >>> /* >>> - * We need to start with the max_order that fits in nr_pages, >>> + * For PMUs that need or prefer large contiguous buffers, >>> + * we need to start with the max_order that fits in nr_pages, >>> * not the other way around, hence ilog2() and not get_order. >>> */ >>> - max_order = ilog2(nr_pages); >>> + if (event->pmu->capabilities & (PERF_PMU_CAP_AUX_NO_SG | >>> + PERF_PMU_CAP_AUX_PREFER_LARGE)) >>> + max_order = ilog2(nr_pages); >>> watermark = 0; >>> } >>> >> >> Although not really sure, could event->pmu->capabilities check against the ORed >> PMU flags PERF_PMU_CAP_AUX_NO_SG and PERF_PMU_CAP_AUX_PREFER_LARGE be contained >> in a helper pmu_prefers_cont_alloc(struct *pmu ...) or something similar ? > > Sure, but I feel it's not very worthwhile. Maybe add a local variable > use_contiguous_pages? It can also work as another comment near > max_order. Probably that will be better.

1 day, 3 hours

[PATCH] coresight: Disable MMIO logging for coresight stm driver

by Mao Jinlong

When read/write registers with readl_relaxed and writel_relaxed, log_read_mmio and log_write_mmio will be called. If mmio trace is enabled to STM, STM driver will write the register to send the trace and writel_relaxed will be called again. The circular call like callstack below will happen. Disable mmio logging for stm driver to avoid this issue. [] stm_source_write[stm_core]+0xc4 [] stm_ftrace_write[stm_ftrace]+0x40 [] trace_event_buffer_commit+0x238 [] trace_event_raw_event_rwmmio_rw_template+0x8c [] log_post_write_mmio+0xb4 [] writel_relaxed[coresight_stm]+0x80 [] stm_generic_packet[coresight_stm]+0x1a8 [] stm_data_write[stm_core]+0x78 [] ost_write[stm_p_ost]+0xc8 [] stm_source_write[stm_core]+0x7c [] stm_ftrace_write[stm_ftrace]+0x40 [] trace_event_buffer_commit+0x238 [] trace_event_raw_event_rwmmio_read+0x84 [] log_read_mmio+0xac [] readl_relaxed[coresight_tmc]+0x50 Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4ba478211b31..f3158266f75e 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -22,6 +22,8 @@ condflags := \ $(call cc-option, -Wstringop-truncation) subdir-ccflags-y += $(condflags) +CFLAGS_coresight-stm.o := -D__DISABLE_TRACE_MMIO__ + obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ -- 2.25.1

1 day, 4 hours

Re: [PATCH v3] perf: Allocate non-contiguous AUX pages by default

by Anshuman Khandual

On 5/2/25 01:05, Yabin Cui wrote: > perf always allocates contiguous AUX pages based on aux_watermark. > However, this contiguous allocation doesn't benefit all PMUs. For > instance, ARM SPE and TRBE operate with virtual pages, and Coresight > ETR allocates a separate buffer. For these PMUs, allocating contiguous > AUX pages unnecessarily exacerbates memory fragmentation. This > fragmentation can prevent their use on long-running devices. > > This patch modifies the perf driver to be memory-friendly by default, > by allocating non-contiguous AUX pages. For PMUs requiring contiguous > pages (Intel BTS and some Intel PT), the existing > PERF_PMU_CAP_AUX_NO_SG capability can be used. For PMUs that don't > require but can benefit from contiguous pages (some Intel PT), a new > capability, PERF_PMU_CAP_AUX_PREFER_LARGE, is added to maintain their > existing behavior. > > Signed-off-by: Yabin Cui <yabinc(a)google.com> > --- > Changes since v2: > Let NO_SG imply PREFER_LARGE. So PMUs don't need to set both flags. > Then the only place needing PREFER_LARGE is intel/pt.c. > > Changes since v1: > In v1, default is preferring contiguous pages, and add a flag to > allocate non-contiguous pages. In v2, default is allocating > non-contiguous pages, and add a flag to prefer contiguous pages. > > v1 patchset: > perf,coresight: Reduce fragmentation with non-contiguous AUX pages for > cs_etm > > arch/x86/events/intel/pt.c | 2 ++ > include/linux/perf_event.h | 1 + > kernel/events/ring_buffer.c | 20 +++++++++++++------- > 3 files changed, 16 insertions(+), 7 deletions(-) > > diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c > index fa37565f6418..25ead919fc48 100644 > --- a/arch/x86/events/intel/pt.c > +++ b/arch/x86/events/intel/pt.c > @@ -1863,6 +1863,8 @@ static __init int pt_init(void) > > if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) > pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG; > + else > + pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_PREFER_LARGE; > > pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | > PERF_PMU_CAP_ITRACE | Why this PMU has PERF_PMU_CAP_AUX_PREFER_LARGE fallback option but not the other PMU in arch/x86/events/intel/bts.c even though both had PERF_PMU_CAP_AUX_NO_SG ? > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h > index 0069ba6866a4..56d77348c511 100644 > --- a/include/linux/perf_event.h > +++ b/include/linux/perf_event.h > @@ -301,6 +301,7 @@ struct perf_event_pmu_context; > #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 > #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 > #define PERF_PMU_CAP_AUX_PAUSE 0x0200 > +#define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 > > /** > * pmu::scope > diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c > index 5130b119d0ae..4d2f1c95673e 100644 > --- a/kernel/events/ring_buffer.c > +++ b/kernel/events/ring_buffer.c > @@ -679,7 +679,7 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, > { > bool overwrite = !(flags & RING_BUFFER_WRITABLE); > int node = (event->cpu == -1) ? -1 : cpu_to_node(event->cpu); > - int ret = -ENOMEM, max_order; > + int ret = -ENOMEM, max_order = 0; 0 order is now the default allocation granularity. This might benefit from a comment above explaining that max_order could change only with PERF_PMU_CAP_AUX_NO_SG or PERF_PMU_CAP_AUX_PREFER_LARGE PMU flags etc. > > if (!has_aux(event)) > return -EOPNOTSUPP; > @@ -689,8 +689,8 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, > > if (!overwrite) { > /* > - * Watermark defaults to half the buffer, and so does the > - * max_order, to aid PMU drivers in double buffering. > + * Watermark defaults to half the buffer, to aid PMU drivers > + * in double buffering. > */ > if (!watermark) > watermark = min_t(unsigned long, > @@ -698,16 +698,22 @@ int rb_alloc_aux(struct perf_buffer *rb, struct perf_event *event, > (unsigned long)nr_pages << (PAGE_SHIFT - 1)); > > /* > - * Use aux_watermark as the basis for chunking to > + * For PMUs that need or prefer large contiguous buffers, > + * use aux_watermark as the basis for chunking to > * help PMU drivers honor the watermark. > */ > - max_order = get_order(watermark); > + if (event->pmu->capabilities & (PERF_PMU_CAP_AUX_NO_SG | > + PERF_PMU_CAP_AUX_PREFER_LARGE)) > + max_order = get_order(watermark); > } else { > /* > - * We need to start with the max_order that fits in nr_pages, > + * For PMUs that need or prefer large contiguous buffers, > + * we need to start with the max_order that fits in nr_pages, > * not the other way around, hence ilog2() and not get_order. > */ > - max_order = ilog2(nr_pages); > + if (event->pmu->capabilities & (PERF_PMU_CAP_AUX_NO_SG | > + PERF_PMU_CAP_AUX_PREFER_LARGE)) > + max_order = ilog2(nr_pages); > watermark = 0; > } > Although not really sure, could event->pmu->capabilities check against the ORed PMU flags PERF_PMU_CAP_AUX_NO_SG and PERF_PMU_CAP_AUX_PREFER_LARGE be contained in a helper pmu_prefers_cont_alloc(struct *pmu ...) or something similar ?

4 days, 21 hours

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight