CoreSight

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2637 discussions

[PATCH v2 0/8] coresight: cti: Miscellaneous fixes and CPU PM cleanup

by Leo Yan

The CPU power management issue in the CTI driver was first observed in series [1]; this series resolves that issue. It fixes bugs and removes CPU PM operations from the CoreSight CTI driver, the goal is to use the CoreSight core layer as the central place for CPU power management. Removing CPU PM from CTI driver can avoid conflicts with the core layer. This series can be divided into: Patches 01 ~ 02: Fix spinlock with irqsave and register read with CS lock. Patches 03 ~ 08: Access ASICCTL condintioanlly, remove CPU PM code, and refactor register access in sysfs knob. This series is based on coresight-next branch and has been validated on Juno r2 platforms, pass normal sysfs and perf test, as well as CPU PM stress testing. [1] https://lore.kernel.org/all/20250915-arm_coresight_power_management_fix-v3-… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Rebased on coresight-next branch (v7.1). - Kept read/write cache value in sysfs knob (Mike). - Link to v1: https://lore.kernel.org/r/20260209-arm_coresight_cti_refactor_v1-v1-0-db71a… --- Leo Yan (8): coresight: cti: Make spinlock usage consistent coresight: cti: Fix register reads coresight: cti: Access ASICCTL only when implemented coresight: cti: Remove CPU power management code coresight: cti: Rename cti_active() to cti_is_active() coresight: cti: Remove hw_powered flag coresight: cti: Remove hw_enabled flag coresight: cti: Properly handle negative offsets in cti_reg32_{show|store}() drivers/hwtracing/coresight/coresight-cti-core.c | 278 ++++------------------ drivers/hwtracing/coresight/coresight-cti-sysfs.c | 171 ++++++------- drivers/hwtracing/coresight/coresight-cti.h | 13 +- 3 files changed, 137 insertions(+), 325 deletions(-) --- base-commit: eef33a7cce239783d0422526a4d786289a936f1b change-id: 20251223-arm_coresight_cti_refactor_v1-76e1bda8b716 Best regards, -- Leo Yan <leo.yan(a)arm.com>

2 days, 1 hour

Re: [PATCH v3 0/3] Enable CTCU and ETR devices for multiple QCOM platforms

by Suzuki K Poulose

Hello, On 04/02/2026 02:22, Jie Gan wrote: > The DT‑binding patch adds platform‑specific compatibles for the > CTCU device, and the following Qualcomm platforms are included: > Kaanapali > Pakala(sm8750) > Hamoa(x1e80100) > Glymur Given this is predominantly DTS changes, and there is very low chances of a conflict with the binding yaml change, I would recommend this to go via soc or the qcom platform tree. For the series: Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Since the base Coresight DT patches for the Kaanapali and Glymur > platforms have not yet been applied, I created DT patches only > for the Pakala and Hamoa platforms. I will submit the Kaanapali > and Glymur patches once their corresponding base Coresight DT patches > are merged. > > The Hamoa‑related patches were posted in a separate email, and I > have included them in the current patch series. > > Link to the previous Hamoa patch series: > https://lore.kernel.org/all/20251106-enable-etr-and-ctcu-for-hamoa-v2-0-cdb… > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > Changes in v3: > - change back to the numeric compatible from hamoa to x1e80100. > - Link to v2: https://lore.kernel.org/r/20260203-enable-ctcu-and-etr-v2-0-aacc7bd7eccb@os… > > Changes in v2: > - change back to the numeric compatible from pakala to sm8750. > - Link to v1: https://lore.kernel.org/r/20260203-enable-ctcu-and-etr-v1-0-a5371a2ec2b8@os… > > --- > Jie Gan (3): > dt-binding: document QCOM platforms for CTCU device > arm64: dts: qcom: hamoa: enable ETR and CTCU devices > arm64: dts: qcom: sm8750: enable ETR and CTCU devices > > .../bindings/arm/qcom,coresight-ctcu.yaml | 4 + > arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 ++++++++++++++++++- > arch/arm64/boot/dts/qcom/sm8750.dtsi | 177 +++++++++++++++++++++ > 3 files changed, 340 insertions(+), 1 deletion(-) > --- > base-commit: 193579fe01389bc21aff0051d13f24e8ea95b47d > change-id: 20260203-enable-ctcu-and-etr-31f9e9d1088d > > Best regards,

2 days, 2 hours

[PATCH v2] MAINTAINERS: Change e-mail address for reviewer

by Mike Leach

From: Mike Leach <mike.leach(a)linaro.org> My e-mail address for linux work is changing to mike.leach(a)arm.com from 1st Jan 2026. Update MAINTAINERS file accordingly Updated .mailmap file accordingly. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Mike Leach <mike.leach(a)arm.com> --- Changes since v1: Add sign off in new email & change .mailmap (Suzuki) --- .mailmap | 1 + MAINTAINERS | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index c124a1306d26..064c00568d20 100644 --- a/.mailmap +++ b/.mailmap @@ -566,6 +566,7 @@ Michel Lespinasse <michel(a)lespinasse.org> <walken(a)google.com> Michel Lespinasse <michel(a)lespinasse.org> <walken(a)zoy.org> Mickaël Salaün <mic(a)digikod.net> <mic(a)linux.microsoft.com> Miguel Ojeda <ojeda(a)kernel.org> <miguel.ojeda.sandonis(a)gmail.com> +Mike Leach <mike.leach(a)arm.com> <mike.leach(a)linaro.org> Mike Rapoport <rppt(a)kernel.org> <mike(a)compulab.co.il> Mike Rapoport <rppt(a)kernel.org> <mike.rapoport(a)gmail.com> Mike Rapoport <rppt(a)kernel.org> <rppt(a)linux.ibm.com> diff --git a/MAINTAINERS b/MAINTAINERS index 4d879f6a7b51..257d2fcb9651 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2719,7 +2719,7 @@ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Suzuki K Poulose <suzuki.poulose(a)arm.com> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: James Clark <james.clark(a)linaro.org> L: coresight(a)lists.linaro.org (moderated for non-subscribers) L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) @@ -20725,7 +20725,7 @@ PERFORMANCE EVENTS TOOLING ARM64 R: John Garry <john.g.garry(a)oracle.com> R: Will Deacon <will(a)kernel.org> R: James Clark <james.clark(a)linaro.org> -R: Mike Leach <mike.leach(a)linaro.org> +R: Mike Leach <mike.leach(a)arm.com> R: Leo Yan <leo.yan(a)linux.dev> L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) S: Supported -- 2.43.0

2 days, 21 hours

Re: [PATCH v6 01/12] dt-bindings: document access-controllers property for coresight peripherals

by Suzuki K Poulose

On 26/02/2026 10:54, Gatien CHEVALLIER wrote: > > > On 2/26/26 11:46, Suzuki K Poulose wrote: >> Hi >> >> On 26/02/2026 10:30, Gatien Chevallier wrote: >>> Document the access-controllers for coresight peripherals in case some >>> access checks need to be performed to use them. >>> >>> Signed-off-by: Gatien Chevallier <gatien.chevallier(a)foss.st.com> >>> Reviewed-by: Rob Herring (Arm) <robh(a)kernel.org> >>> --- >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> cti.yaml | 3 +++ >>> .../devicetree/bindings/arm/arm,coresight-dynamic- >>> funnel.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> etm.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> stm.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> tmc.yaml | 3 +++ >>> Documentation/devicetree/bindings/arm/arm,coresight- >>> tpiu.yaml | 3 +++ >> >> Are you sure, you are not missing "replicator" in the list ? >> >> Otherwise, looks good to me. >> >> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> > > The replicator is not present on the Linux side on stm32mp1x platforms > (Only present for the Cortex M4 co-processor on stm32mp15x platforms). > On stm32mp2x platforms, it will be necessary so it will be added in the > related P-R because we'll need the same debug access check mechanism. Fair enough. It looked a bit odd to me with TMC and TPIU both in the list without a Replicator. Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > >> >> >>> 6 files changed, 18 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>> index 2a91670ccb8c..949444aba1f8 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml >>> @@ -128,6 +128,9 @@ properties: >>> "#address-cells": >>> const: 1 >>> + access-controllers: >>> + maxItems: 1 >>> + >>> patternProperties: >>> '^trig-conns@([0-9]+)$': >>> type: object >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/ >>> arm,coresight-dynamic-funnel.yaml >>> index b74db15e5f8a..b0693cd46d27 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic- >>> funnel.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic- >>> funnel.yaml >>> @@ -78,6 +78,9 @@ properties: >>> description: Output connection to CoreSight Trace bus >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml >>> index 71f2e1ed27e5..10ebbbeadf93 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml >>> @@ -118,6 +118,9 @@ properties: >>> description: Output connection from the ETM to CoreSight >>> Trace bus. >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - clocks >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml >>> index 378380c3f5aa..f243e76f597f 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml >>> @@ -73,6 +73,9 @@ properties: >>> description: Output connection to the CoreSight Trace bus. >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml >>> index 96dd5b5f771a..9dc096698c65 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml >>> @@ -128,6 +128,9 @@ properties: >>> - const: tracedata >>> - const: metadata >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight- >>> tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight- >>> tpiu.yaml >>> index a207f6899e67..29bbc3961fdf 100644 >>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml >>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml >>> @@ -70,6 +70,9 @@ properties: >>> description: Input connection from the CoreSight Trace bus. >>> $ref: /schemas/graph.yaml#/properties/port >>> + access-controllers: >>> + maxItems: 1 >>> + >>> required: >>> - compatible >>> - reg >>> >> >

3 days, 1 hour

Re: [PATCH v6 01/12] dt-bindings: document access-controllers property for coresight peripherals

by Suzuki K Poulose

Hi On 26/02/2026 10:30, Gatien Chevallier wrote: > Document the access-controllers for coresight peripherals in case some > access checks need to be performed to use them. > > Signed-off-by: Gatien Chevallier <gatien.chevallier(a)foss.st.com> > Reviewed-by: Rob Herring (Arm) <robh(a)kernel.org> > --- > Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml | 3 +++ > .../devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml | 3 +++ > Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml | 3 +++ Are you sure, you are not missing "replicator" in the list ? Otherwise, looks good to me. Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > 6 files changed, 18 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml > index 2a91670ccb8c..949444aba1f8 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml > @@ -128,6 +128,9 @@ properties: > "#address-cells": > const: 1 > > + access-controllers: > + maxItems: 1 > + > patternProperties: > '^trig-conns@([0-9]+)$': > type: object > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > index b74db15e5f8a..b0693cd46d27 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > @@ -78,6 +78,9 @@ properties: > description: Output connection to CoreSight Trace bus > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > index 71f2e1ed27e5..10ebbbeadf93 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml > @@ -118,6 +118,9 @@ properties: > description: Output connection from the ETM to CoreSight Trace bus. > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - clocks > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > index 378380c3f5aa..f243e76f597f 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml > @@ -73,6 +73,9 @@ properties: > description: Output connection to the CoreSight Trace bus. > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > index 96dd5b5f771a..9dc096698c65 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > @@ -128,6 +128,9 @@ properties: > - const: tracedata > - const: metadata > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > index a207f6899e67..29bbc3961fdf 100644 > --- a/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml > @@ -70,6 +70,9 @@ properties: > description: Input connection from the CoreSight Trace bus. > $ref: /schemas/graph.yaml#/properties/port > > + access-controllers: > + maxItems: 1 > + > required: > - compatible > - reg >

3 days, 1 hour

Re: [PATCH] coresight: ctcu: fix the spin_bug

by Suzuki K Poulose

On Thu, 19 Feb 2026 22:46:57 +0800, Jie Gan wrote: > Acquiring an uninitialized raw_spin_lock is invalid and may trigger > unexpected behavior or spin_bug. > > Applied, thanks! [1/1] coresight: ctcu: fix the spin_bug https://git.kernel.org/coresight/c/36ffbbc2b387 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 days, 2 hours

[PATCH 0/8] coresight: cti: Miscellaneous fixes and CPU PM cleanup

by Leo Yan

The CPU power management issue in the CTI driver was first observed in series [1]; this series resolves that issue. It fixes bugs and removes CPU PM operations from the CoreSight CTI driver, the goal is to use the CoreSight core layer as the central place for CPU power management. Removing CPU PM from CTI driver can avoid conflicts with the core layer. Based on review of the Arm ARM, ASICCTL is the only CTI register that could potentially reside in the CPU power domain. However, this is considered highly unlikely for the following reasons: - Standard Arm CTIs place the ASICCTL register in the debug power domain; - ASICCTL is implemented only when CTIDEVID.EXTMUXNUM is non-zero, which is rare for CPU CTIs. As a result, it is safe to remove the CPU PM code as done in this series. In addition, avoiding support local CPU access (via SMP calls) to ASICCTL significantly reduces driver complexity. If a future hardware implements ASICCTL in the CPU power domain, we can consider adding a property to describe that characteristic. That said, from a software point of view, keeping all CTI registers in the same power domain is preferable, as it makes the driver implementation much simpler. This series can be divided into: Patches 01 ~ 02: Fix spinlock with irqsave and register read with CS lock. Patches 03 ~ 08: Access ASICCTL condintioanlly, remove CPU PM code, and refactor register access in sysfs knob. This series is based on coresight-next branch and has been validated on Juno r1 and r2 platforms, pass normal sysfs and perf test, as well as CPU PM stress testing. [1] https://lore.kernel.org/all/20250915-arm_coresight_power_management_fix-v3-… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (8): coresight: cti: Make spinlock usage consistent coresight: cti: Fix register reads coresight: cti: Access ASICCTL only when implemented coresight: cti: Remove CPU power management code coresight: cti: Rename cti_active() to cti_is_active() coresight: cti: Remove hw_powered flag coresight: cti: Remove hw_enabled flag coresight: cti: Refactor cti_reg32_{show|store}() drivers/hwtracing/coresight/coresight-cti-core.c | 278 ++++------------------ drivers/hwtracing/coresight/coresight-cti-sysfs.c | 168 ++++++------- drivers/hwtracing/coresight/coresight-cti.h | 13 +- 3 files changed, 134 insertions(+), 325 deletions(-) --- base-commit: eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d change-id: 20251223-arm_coresight_cti_refactor_v1-76e1bda8b716 Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 days, 20 hours

[PATCH v4 0/8] coresight: Fix device registration and unregistration

by Leo Yan

This series is to fix and refactor CoreSight device registration and unregistration, it can be divided into three small parts: Patches 01-03: Three fixes for memory leak, device reference and mutex protection. Patches 04-05: Move connection cleanup operations into coresight_remove_conns(). Patches 06-08: Refactor error handling in coresight_register(). This series is verified on Juno board. --- Changes in v4: - Applied James' review tags on patches 01-07. - Kept the "registered" flag to use central place for mutex release (James / Suzuki). - Link to v3: https://lore.kernel.org/r/20260202-arm_coresight_refactor_dev_register-v3-0… Changes in v3: - Updated patch 01 to use coesight core layer for device index list (Suzuki). - Link to v2: https://lore.kernel.org/r/20260126-arm_coresight_refactor_dev_register-v2-0… Changes in v2: - Refined the commit log in patch 06 (Suzuki). - Unified to call coresight_unregister() for error handling (Suzuki). - Refactor connection and sysfs group release. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250512154108.23920-1-leo.yan@arm… To: Suzuki K Poulose <suzuki.poulose(a)arm.com> To: Mike Leach <mike.leach(a)arm.com> To: James Clark <james.clark(a)linaro.org> To: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> To: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> To: Mathieu Poirier <mathieu.poirier(a)linaro.org> To: Mao Jinlong <quic_jinlmao(a)quicinc.com> Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (8): coresight: Fix memory leak in coresight_alloc_device_name() coresight: Get parent device reference after sink ID map allocation coresight: Protect unregistration with mutex coresight: Refactor output connection sysfs link cleanup coresight: Refactor sysfs connection group cleanup coresight: Move sink validation into etm_perf_add_symlink_sink() coresight: Do not mix success path with failure handling coresight: Unify bus unregistration via coresight_unregister() drivers/hwtracing/coresight/coresight-catu.c | 4 +- drivers/hwtracing/coresight/coresight-core.c | 214 +++++++++++++-------- drivers/hwtracing/coresight/coresight-ctcu-core.c | 4 +- drivers/hwtracing/coresight/coresight-cti-core.c | 19 +- drivers/hwtracing/coresight/coresight-dummy.c | 7 +- drivers/hwtracing/coresight/coresight-etb10.c | 4 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 5 +- drivers/hwtracing/coresight/coresight-funnel.c | 4 +- drivers/hwtracing/coresight/coresight-platform.c | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 3 +- drivers/hwtracing/coresight/coresight-replicator.c | 4 +- drivers/hwtracing/coresight/coresight-stm.c | 4 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 12 +- drivers/hwtracing/coresight/coresight-tnoc.c | 4 +- drivers/hwtracing/coresight/coresight-tpda.c | 4 +- drivers/hwtracing/coresight/coresight-tpdm.c | 4 +- drivers/hwtracing/coresight/coresight-tpiu.c | 4 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 4 +- include/linux/coresight.h | 14 +- 19 files changed, 167 insertions(+), 153 deletions(-) --- base-commit: eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d change-id: 20260120-arm_coresight_refactor_dev_register-f16c069db41d Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 days, 22 hours

[PATCH] coresight: cti: Move resource release to cti_remove()

by Leo Yan

Currently, CTI driver releases resource by deferring cti_device_release() to the device unregistration: cti_remove() `> coresight_unregister() `> cti_remove_assoc_from_csdev() `> device_unregister() `> cti_device_release() `> mutex_lock(&ect_mutex) `> release CTI resource `> mutex_unlock(&ect_mutex) In the above flow, two different CTI release callbacks are involved: cti_remove_assoc_from_csdev() and cti_device_release(). The former is used by a CoreSight device to unbind its associated CTI helper device, while the latter releases resources for the CTI device itself. Since there is no dependency between them, it is unnecessary to defer the CTI resource release until device unregistration. This commit releases the resources directly in cti_remove() and remove the injected release callback. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- drivers/hwtracing/coresight/coresight-cti-core.c | 24 +++--------------------- drivers/hwtracing/coresight/coresight-cti.h | 2 -- 2 files changed, 3 insertions(+), 23 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index bfbc365bb2ef2744efab11c056b8450472957005..7a8f1ef6b94e8ab3363ea62db95b0bc302292cd7 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -823,16 +823,13 @@ static const struct coresight_ops cti_ops = { .helper_ops = &cti_ops_ect, }; -/* - * Free up CTI specific resources - * called by dev->release, need to call down to underlying csdev release. - */ -static void cti_device_release(struct device *dev) +static void cti_remove(struct amba_device *adev) { - struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct cti_drvdata *drvdata = dev_get_drvdata(&adev->dev); struct cti_drvdata *ect_item, *ect_tmp; mutex_lock(&ect_mutex); + cti_remove_conn_xrefs(drvdata); cti_pm_release(drvdata); /* remove from the list */ @@ -844,17 +841,6 @@ static void cti_device_release(struct device *dev) } mutex_unlock(&ect_mutex); - if (drvdata->csdev_release) - drvdata->csdev_release(dev); -} -static void cti_remove(struct amba_device *adev) -{ - struct cti_drvdata *drvdata = dev_get_drvdata(&adev->dev); - - mutex_lock(&ect_mutex); - cti_remove_conn_xrefs(drvdata); - mutex_unlock(&ect_mutex); - coresight_unregister(drvdata->csdev); } @@ -947,10 +933,6 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) cti_update_conn_xrefs(drvdata); mutex_unlock(&ect_mutex); - /* set up release chain */ - drvdata->csdev_release = drvdata->csdev->dev.release; - drvdata->csdev->dev.release = cti_device_release; - /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "CTI initialized\n"); diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 4f89091ee93f5fb046d93b97a4085051fca6b39d..daff9e32a6daca90f4d5f4726f163fdd9106191c 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -170,7 +170,6 @@ struct cti_config { * @spinlock: Control data access to one at a time. * @config: Configuration data for this CTI device. * @node: List entry of this device in the list of CTI devices. - * @csdev_release: release function for underlying coresight_device. */ struct cti_drvdata { void __iomem *base; @@ -179,7 +178,6 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; - void (*csdev_release)(struct device *dev); }; /* --- base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f change-id: 20260224-arm_coresight_refactor_cti_resource_release-24d9bde4f13c Best regards, -- Leo Yan <leo.yan(a)arm.com>

4 days, 1 hour

[PATCH] coresight: tmc: Fix overflow when calculating is bigger than 2GiB

by Leo Yan

When specifying a 2GB AUX buffer, the ETR driver ends up allocating only a 1MB buffer instead: # echo 'file coresight-tmc-etr.c +p' > \ /sys/kernel/debug/dynamic_debug/control # perf record -e cs_etm/@tmc_etr0,timestamp=0/u -C 0 -m ,2G -- test coresight tmc_etr0: allocated buffer of size 1024KB in mode 0 The page index is an 'int' type, and shifting it by PAGE_SHIFT overflows when the resulting value exceeds 2GB. This produces a negative value, causing the driver to fall back to the minimum buffer size (1MB). Cast the page index to a wider type to accommodate large buffer sizes. Also fix a similar issue in the buffer offset calculation. Reported-by: Michiel van Tol <michiel.vantol(a)arm.com> Fixes: 99443ea19e8b ("coresight: Add generic TMC sg table framework") Fixes: eebe8dbd8630 ("coresight: tmc: Decouple the perf buffer allocation from sysfs mode") Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index cee82e52c4ea96b035f1db71b2d9a006bfc1c51e..990bbb721e1d712d7b93f1e36087fdaf9d3baa3b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -154,7 +154,7 @@ tmc_pages_get_offset(struct tmc_pages *tmc_pages, dma_addr_t addr) for (i = 0; i < tmc_pages->nr_pages; i++) { page_start = tmc_pages->daddrs[i]; if (addr >= page_start && addr < (page_start + PAGE_SIZE)) - return i * PAGE_SIZE + (addr - page_start); + return (long)i * PAGE_SIZE + (addr - page_start); } return -EINVAL; @@ -1381,7 +1381,7 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); /* Use the minimum limit if the required size is smaller */ - size = nr_pages << PAGE_SHIFT; + size = (ssize_t)nr_pages << PAGE_SHIFT; size = max_t(ssize_t, size, TMC_ETR_PERF_MIN_BUF_SIZE); /* --- base-commit: eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d change-id: 20260217-arm_coresight_fix_big_buffer_size-a8a41298369d Best regards, -- Leo Yan <leo.yan(a)arm.com>

6 days, 2 hours

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