CoreSight

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[PATCH v2 00/11] coresight: trbe: Refactor buffer handling and add trigger support

by Leo Yan

TRBE currently stops trace collection at each buffer limit, so interrupt latency can cause trace loss. This series adds trigger-based maintenance and WRAP mode to reduce these gaps, while protecting unconsumed data and retaining limit-based handling where required by errata. The perf changes preserve decoder state across contiguous indexed AUX fragments, with resets when continuity cannot be established. Thread stacks still flush at each data block boundary. For normal recording, a quarter-buffer watermark wakes userspace earlier. The 11 patches cover: Patches 01-02: Next-buffer computation cleanup and refactoring. Patches 03-07: Trigger support, headroom, save/restore, and KUnit tests. Patches 08-11: Decoder continuity and earlier userspace wakeups. This series is based on coresight-next and requires "coresight: trbe: Refactor buffer and IRQ handling" [1] to be applied first. This series has been tested on the Orion6 board with TRBE and the Juno-r2 board with ETR using the following commands: perf record -e cs_etm// -a -- bash -c 'for i in {1..5}; do timeout 0.1 yes > /dev/null; sleep 0.1; done' perf script --itrace=i1000iTZ [1] https://lore.kernel.org/linux-arm-kernel/20261016-trbe_enable_disable_irq_h… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Changes in v2: - Split the enable/disable, perf-handle lifecycle, and IRQ handling fixes into the separate prerequisite series, leaving 11 patches here. - Restrict KUnit buffer and padding stubs to the synthetic test handle, preserving normal buffer lookup and AUX accounting for real perf IRQs. - Centralize decoder-reset decisions in cs_etm__get_trace(), while retaining thread-stack flushing at every data block boundary. - Reset per-thread decoders for unknown or changed CPUs, preserve CPU metadata on all split pieces, and retain resets through empty fragments. - Reset the decoder on logical AUX offset discontinuities, including clipped snapshots and missing AUX records, while preserving continuity across internal buffer splits. - Link to v1: https://lore.kernel.org/r/20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076… --- Leo Yan (11): coresight: trbe: Remove misleading comment coresight: trbe: Refactor next buffer computation coresight: trbe: Track trigger count support per CPU coresight: trbe: Use trigger mode for buffer maintenance coresight: trbe: Leave headroom for stop-on-trigger mode coresight: trbe: Save and restore trigger counter coresight: trbe: Add KUnit tests for compute normal buffer perf cs-etm: Reset decoder on COLLISION flag perf cs-etm: Reset per-thread decoder on CPU migration perf cs-etm: Reset decoder on AUX offset discontinuity perf cs-etm: Set watermark for AUX trace drivers/hwtracing/coresight/Kconfig | 15 + .../coresight/coresight-trbe-kunit-tests.c | 644 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.c | 342 ++++++++--- drivers/hwtracing/coresight/coresight-trbe.h | 18 + tools/perf/arch/arm/util/cs-etm.c | 15 + tools/perf/util/auxtrace.h | 2 + tools/perf/util/cs-etm.c | 92 ++- 7 files changed, 1029 insertions(+), 99 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20260617-trbe_buffer_refactor_v2-8813e33fde8b prerequisite-message-id: <20261016-trbe_enable_disable_irq_handle_refactor-v2-0-3f57cf3199b1(a)arm.com> prerequisite-patch-id: 295f75af9986fc6193b0f3ec0f144096c1194efd prerequisite-patch-id: 60541bcf6bd25acf076fca2dd2e62ea382541fd5 prerequisite-patch-id: 0a6dbd3a69611c9bdca8ad61ea943d6577251fb8 prerequisite-patch-id: 0f4dc971d1375cd5672a63cd148b6e7f6dfdd9b3 prerequisite-patch-id: b42114d2185bbd15c9095191417aad34137cc5e9 prerequisite-patch-id: fdcdce0d19c611de475c6e9737ef544a9fb19153 prerequisite-patch-id: 948b6aa1254adfc9f89a5aba3ef45e41d891debe prerequisite-patch-id: ba1cc65a72bcfef9e22fea14f52eeaeeb2c551d3 prerequisite-patch-id: d0efcfbe7d1f7886aaa5c34655c14a979bf55863 prerequisite-patch-id: af045abf5718e35f16a5b98ec7c04213cf24d426 prerequisite-patch-id: d0af1d9f5551622858815d148de5dc3c94cdf564 prerequisite-patch-id: 9d02a95ecafda17debf728ef1098b98030019a10 prerequisite-patch-id: c6251f03223c3bd4bcf43abc292907dd93cad527 prerequisite-patch-id: 690af6c1769b93d8712aa73b322bb4e5f0acdc66 prerequisite-patch-id: 21c3d8dacd550b977ae549a1865e43523ed64f98 prerequisite-patch-id: 0b5666068c0fed73e6906473b38861556881e5b0 prerequisite-patch-id: f5c97c9acc3e691b3612999eae97c3366acf3d97 prerequisite-patch-id: 55846a3b80ca3196062d06522af768ac83751d97 prerequisite-patch-id: 5f5be1d1c925a9c0d945eba516a9075153045292 prerequisite-patch-id: 8e39271308702e557abc4e4e79fc96d0157844a7 prerequisite-patch-id: b99199a58c4a87408c4c2b0b39ee4861f5cd9d80 prerequisite-patch-id: 1bdbfe0417a4a98984b2fbe8d664738657de3032 prerequisite-patch-id: aeab33675e29539d239c8ffdf4bbd4cf861972c6 Best regards, -- Leo Yan <leo.yan(a)arm.com>

14 hours, 14 minutes

[PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling

by Leo Yan

This series follows the earlier TRBE buffer refactoring posting [1]. The work is now split into two parts. This first part contains fixes and refactoring in preparation for wrap and trigger mode support. Support for those modes will be sent separately. The patches are grouped as follows for easier review: Patches 1-5: Minor fixes Add register definitions, fix the watermark range check, and improve erratum checks and perf handle validation. Patches 6-11: Enable/disable lifecycle fixes Clean up session setup, status clearing and IRQ handle ownership. Patches 12-17: Refine status classification Decode stop reasons, report truncation on errors and improve trace-size accounting. Patches 18-23: Improve IRQ and overflow handling Keep the handle in per-CPU data, stabilize status reads, and improve AUX restarts and trace-gap reporting. A race also remains between TRBE interrupt handling and AUX pause/resume from a sampling NMI. This should be resolved as part of the state machine refactoring in the CoreSight AUX sampling series [2]. [1] https://lore.kernel.org/linux-arm-kernel/20251201-trbe_buffer_refactor_v1-1… [2] https://lore.kernel.org/linux-arm-kernel/20260915-arm_cs_support_aux_sample… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (23): arm64/sysreg: Define TRBSR_EL1.EC event classes coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset() coresight: trbe: Use helpers for checking errata coresight: trbe: Check the buffer association before IRQ validation coresight: trbe: Validate perf handle before using sink data coresight: trbe: Drop redundant disable from enable path coresight: trbe: Publish the session after successful enable coresight: trbe: Clear stale external abort status coresight: trbe: Clear TRBSR status at stop sites coresight: trbe: Drop redundant disables coresight: trbe: Assign the perf handle in enable and disable coresight: trbe: Decode TRBSR status codes coresight: trbe: Simplify wrap status handling coresight: trbe: Treat access not allowed stops as fatal coresight: trbe: Report truncated trace on buffer update errors coresight: trbe: Always classify TRBSR when updating buffer coresight: trbe: Calculate trace size across buffer wrap coresight: trbe: Keep the perf handle in per-CPU data coresight: trbe: Reload the AUX buffer on overflow restart coresight: trbe: Add fault action argument to trbe_handle_overflow() coresight: trbe: Read TRBSR after prohibiting and flushing trace coresight: trbe: Restart trace source for stopped buffers coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION arch/arm64/include/asm/sysreg.h | 6 + arch/arm64/tools/sysreg | 8 +- drivers/hwtracing/coresight/coresight-trbe.c | 481 ++++++++++++++++++--------- drivers/hwtracing/coresight/coresight-trbe.h | 8 - 4 files changed, 345 insertions(+), 158 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20261016-trbe_enable_disable_irq_handle_refactor-0a3450f03473 Best regards, -- Leo Yan <leo.yan(a)arm.com>

18 hours, 30 minutes

[PATCH 00/25] CoreSight / perf: Support AUX sampling

by Leo Yan

This series adds AUX sampling support to Arm CoreSight. A PMU sample can carry a window of recent AUX trace, which perf generates callchain and branch stack for the sampled thread. This provides execution history for context-based profiling. The series can be divided into four parts: 1. Patches 01 ~ 03 for event core: The perf event core changes warn on non-positive AUX snapshot returns before checking alignment padding. Space for a non-zero AUX payload has already been reserved, so a zero return leaves that payload unwritten. CoreSight fills unavailable trace with zeros and returns the requested size. It also prevents AUX sampling and pause/resume from nesting through an NMI. A driver guard alone can leave perf's pause state (aux_paused) inconsistent with the hardware state. The event core ensures only one AUX callback is exclusively invoked. Export the output copy helpers so CoreSight can fill sample payloads when the driver is built as a module. 2. Patches 04 ~ 09 for ETM perf: The ETM perf changes separate the lifetime of the published CoreSight context from that of the AUX output handle. Centralize buffer updates, and end AUX output when throttling stops an event without PERF_EF_UPDATE so a later restart can acquire a fresh handle. Make hardware-state transitions reflect completed operations. 3. Patches 10 ~ 13 for TRBE driver: TRBE snapshot buffers need padding to meet the CPU's alignment and wrap constraints. Use circular buffer mode for overwrite snapshots, retaining Fill mode on CPUs that require the write out-of-range workaround. TRBE faults can still raise interrupts in circular mode. Track when the sink is handling an interrupt so an AUX sampling NMI can skip a snapshot while the interrupted handler is updating the buffer. Make repeated sink disable safe for deferred cleanup after a snapshot failure. 4. Patches 14 ~ 25 for AUX sampling and decoding: Shared atomic STOP and AUX action bits prevent an NMI stop from tearing down the context while pause, resume or snapshot accesses it. The AUX operation finishes and then completes the deferred stop, publishing the stopped state only after hardware teardown. Add snapshot_aux() to the CoreSight driver to pause the source, update the sink buffer, disable the path, copy the recent trace into the PMU sample, and then re-enable the path and resume the source. Patch 17 fixes history collection for zero-IP PMU samples. Perf clears the IP when a user-only sampling interrupt skids into the kernel, but the timestamp and TID remain valid for matching the trace history. In perf, decode each embedded payload as an independent trace window, selecting the decoder with the sampled CPU and using the sample's PID/TID and traced context IDs to attribute history to the sampled thread. Refactor common timeless decoding and history collection, and drain pending OpenCSD output so buffered history is not lost. Attach reconstructed callchains and branch stacks to the original PMU samples, preserving histories already present in the samples. Add a test, and document the recording and decoding workflow and its limitations. The initial support targets unformatted trace from per-CPU sinks such as TRBE. Shared formatted sinks such as ETR can mix trace from multiple CPUs, consuming the limited sample window with execution unrelated to the sampled thread. This series is based on Amir's series "perf: Add CoreSight branch history to existing samples" [1] for perf tool's branch / callchain generating. [1] https://lore.kernel.org/linux-perf-users/cover.1787005265.git.aaupov@fb.com/ Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (25): perf/core: Reject non-positive AUX snapshot sizes perf/core: Prevent AUX sampling from racing with pause/resume perf/core: Export output copy helpers for CoreSight coresight: perf: End AUX output when an event is throttled coresight: perf: Extract AUX buffer update helper coresight: perf: Simplify flow for CPUs without a path coresight: perf: Validate the live context through its path coresight: perf: Validate context before resuming trace coresight: perf: Improve hardware state transitions coresight: trbe: Pad snapshot buffers coresight: trbe: Use circular buffer mode for snapshots coresight: trbe: Track per-CPU sink interrupt handling coresight: trbe: Handle an already disabled sink coresight: perf: Look up the trace path in etm_event_pause() coresight: perf: Serialize AUX pause and resume with event stops coresight: perf: Support AUX sampling with per-CPU sinks perf cs-etm: Allow history collection for samples with zero IP perf cs-etm: Unify timeless buffer decoding perf cs-etm: Propagate errors from trace queue flushing perf cs-etm: Drain pending packets before finishing trace blocks perf cs-etm: Complete packet draining with end of trace perf cs-etm: Centralize sample history collection perf cs-etm: Decode AUX samples into callchains and branch stacks perf test: Add CoreSight AUX sample decoding test Documentation: coresight: Document AUX sample decoding Documentation/trace/coresight/coresight-perf.rst | 39 ++ drivers/hwtracing/coresight/coresight-etm-perf.c | 396 +++++++++++++----- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 + drivers/hwtracing/coresight/coresight-trbe.c | 122 ++++-- include/linux/coresight.h | 2 + kernel/events/core.c | 26 +- kernel/events/ring_buffer.c | 2 + tools/perf/arch/arm/util/cs-etm.c | 6 + tools/perf/tests/shell/coresight/aux_sample.sh | 189 +++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 39 ++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 7 + tools/perf/util/cs-etm.c | 491 ++++++++++++++++------- 12 files changed, 1040 insertions(+), 281 deletions(-) --- base-commit: 134e1295eedfc9a3c6e4e63d8ef45dc63749449b change-id: 20260826-arm_cs_support_aux_sample-275664545588 Best regards, -- Leo Yan <leo.yan(a)arm.com>

21 hours, 26 minutes

[PATCH v4 00/10] coresight: Prevent per-thread events from sharing a sink

by James Clark

Concurrent per-thread events results in a WARN on N1SDP which leads to the realization that per-thread events shouldn't have been sharing sinks in the first place. This slips through because different per-thread events will have the same PID if owned by the same process, and we only check the PID and nothing else. That results in unexpected WARNs because it looks like we assumed it couldn't happen (although exclusive PMU rules allow it). But even if it was supported it would result in trace from the wrong thread in another event's per-thread buffer, so we should disallow it. Fix it by determining if sharing can happen at setup time. Then remove everywhere the same PID checking logic was copy pasted in each sink. The first three patches fix configuration initialization, AUX cleanup and topology locking. The remaining patches enforce the sharing rules and simplify the sink drivers. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v4: - Count CPU sources in the registered topology and retain each sink's sharing classification until its last AUX session ends. - Serialize AUX topology access and provide locked and locking path release functions. - Reject unexpected path setup errors while retaining silent skips for missing ETMs and unreachable sinks. - Prevent all problematic sharing cases at aux setup rather than at runtime. (Leo) - Drop "coresight: tmc-etr: Don't stop Perf cleanup for active sysfs reads". It was a pre-existing bug and is even more unrelated now with the new model. - Remove workqueue rather than fix the lifecycle, its no longer needed. (Leo) - Add a getter for the config manager, cscfg_get_state(). (Leo) - Link to v3: https://lore.kernel.org/r/20260728-james-cs-multiple-per-threads-v3-0-6aee7… Changes in v3: - Storing and accessing event owners at runtime causes problems due to various scenarios of: events (and sibling events) exiting, children inheriting event FDs, PID reuse, CPU affine events that also have a target process set but different inherit settings. Fix it by creating a session ID in etm_setup_aux() and holding the references in it for the duration of the whole session. (Leo) - Make the ETR buffer allocator consistent with sink sharing rules by not doing numeric PID comparisons there either. - Fix up some Sashiko reports that it sees after interacting with cscfg and taking extra references to tasks and PIDs. - Link to v2: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v2-0-10ac7… Changes in v2: - Fix inherited events by following event->parent - Link to v1: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v1-0-d384e… --- James Clark (10): coresight: configfs: Don't assume active until cscfg_mgr is set coresight: etm-perf: Remove workqueue for freeing AUX data coresight: etm-perf: Serialize AUX topology access coresight: etm-perf: Reject event if building path fails coresight: etm-perf: Prevent sink sharing at setup time coresight: tmc-etr: Reflect new sharing rules in allocator coresight: tmc-etr: Remove sharing guards from ETR coresight: tmc-etf: Remove sharing guards from ETF coresight: etb10: Remove sharing guards from ETB10 coresight: ultrasoc-smb: Remove sharing guards from SMB drivers/hwtracing/coresight/coresight-core.c | 104 +++++++++++++++-- drivers/hwtracing/coresight/coresight-etb10.c | 28 +---- drivers/hwtracing/coresight/coresight-etm-perf.c | 119 ++++++++++--------- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 - drivers/hwtracing/coresight/coresight-priv.h | 4 +- drivers/hwtracing/coresight/coresight-syscfg.c | 11 +- drivers/hwtracing/coresight/coresight-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 6 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 22 +--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 142 +++++++---------------- drivers/hwtracing/coresight/coresight-tmc.h | 16 +-- drivers/hwtracing/coresight/coresight-trace-id.c | 97 ++++++++++++++-- drivers/hwtracing/coresight/coresight-trace-id.h | 26 +++-- drivers/hwtracing/coresight/ultrasoc-smb.c | 20 +--- drivers/hwtracing/coresight/ultrasoc-smb.h | 3 - include/linux/coresight.h | 26 ++++- 16 files changed, 346 insertions(+), 284 deletions(-) --- base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842 change-id: 20260708-james-cs-multiple-per-threads-ed1d25ed1734 Best regards, -- James Clark <james.clark(a)linaro.org>

1 day

[PATCH 0/2] perf: Order SPE and TRBE padding before publishing AUX head

by Leo Yan

SPE and TRBE write padding into their AUX buffers before advancing aux_head. Add the missing write barriers so that a userspace reader on another CPU cannot observe the new head before the padding stores become visible. AUX producers must make their data visible before publishing aux_head. The required synchronization depends on the trace hardware and CPU memory model, so the barriers belong in the drivers rather than in perf_aux_output_skip() or perf_aux_output_end(). The TRBE change also covers padding inserted by the overwrite erratum workaround before perf_aux_output_end(). Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (2): perf: arm_spe: Order padding before publishing AUX head coresight: trbe: Order padding before publishing AUX head drivers/hwtracing/coresight/coresight-trbe.c | 2 ++ drivers/perf/arm_spe_pmu.c | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) --- base-commit: 0fcb05b72344f40806cbe810de8872f1698bf053 change-id: 20261015-add_barriers_for_perf_aux_output_skip-70356815b2bd Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 day, 1 hour

Re: [PATCH 1/5] dt-bindings: arm: coresight: Limit static replicator to atclk

by Leo Yan

On Tue, Oct 13, 2026 at 07:53:20AM +0200, Michal Simek wrote: > > > On 10/12/26 18:28, Leo Yan wrote: > > On Mon, Oct 12, 2026 at 02:35:37PM +0200, Michal Simek wrote: > > > > > > > > > On 10/2/26 17:07, Leo Yan wrote: > > > > Static replicators have no programmable registers and need no APB > > > > programming clock. > > > > > > > > The Zynq clock controller registers dbg_trc and dbg_apb and calls > > > > clk_prepare_enable() for each gate the bootloader left on. > > > > > > That's one bootloader behavior. If there is another bootloader that clocks > > > can be simply disabled. I don't think there is any reason to depends on > > > bootloader behavior. If there are clocks which has to be ON I can't see any > > > reason not to drive them. > > > > My reference to zynq_clk_setup() was to explain that this patch leaves > > the existing management of dbg_trc and dbg_apb unchanged. > > > > The CoreSight drivers do not request clocks named "dbg_trc" or "dbg_apb". > > And this is the point. DT binding is not describing what Linux driver handles. > Binding describes HW itself. I agreed that "Binding describes HW itself". The question is which hardware clock connections the DT properties describe. Arm DDI 0314H, Table B-1 [1], lists ATCLK for the replicator, and ATCLK and PCLKDBG for the trace funnel. The static modules have no APB programming interface. > And for proper functionality these 2 clocks need to be handled. Please point to the Zynq TRM section or clock diagram showing how dbg_trc and dbg_apb supply the replicator and funnel. > That Linux driver is not doing it that's different issue. My understanding is the CoreSight drivers have already followed spec to support clocks. [1] https://support.arm.com/documentation/ddi0314/h/CoreSight-Components-and-Cl…

1 day, 1 hour

Re: [PATCH 1/5] dt-bindings: arm: coresight: Limit static replicator to atclk

by Leo Yan

On Mon, Oct 12, 2026 at 02:35:37PM +0200, Michal Simek wrote: > > > On 10/2/26 17:07, Leo Yan wrote: > > Static replicators have no programmable registers and need no APB > > programming clock. > > > > The Zynq clock controller registers dbg_trc and dbg_apb and calls > > clk_prepare_enable() for each gate the bootloader left on. > > That's one bootloader behavior. If there is another bootloader that clocks > can be simply disabled. I don't think there is any reason to depends on > bootloader behavior. If there are clocks which has to be ON I can't see any > reason not to drive them. My reference to zynq_clk_setup() was to explain that this patch leaves the existing management of dbg_trc and dbg_apb unchanged. The CoreSight drivers do not request clocks named "dbg_trc" or "dbg_apb". And removing those unused clock properties introduces no additional dependence on the bootloader. Could you clarify how retaining these entries addresses the bootloader concern? > TRM page 741 > > Trace Port Clock The trace port clock is used to clock the TPIU and trace > buffer when the MIO interface is chosen and must be twice the frequency of > the desired TPIU clock. The TPIU clock frequency must be chosen to be fast > enough to allow the trace port to keep up with the amount of data being > traced, but slow enough to meet the dynamic characteristics of the data > output buffers of the TPIU. The quoted paragraph establishes a trace-clock requirement for the TPIU and trace buffer, how does it identify the clock inputs of the funnel and replicator? Thanks, Leo

4 days, 18 hours

[GIT PULL] coresight: Update for linux v7.4

by Suzuki K Poulose

Hi Greg Please find the updates for coresight self hosted tracing subsystem targeting Linux v7.4. Apologies for the delay! Kindly pull. Suzuki The following changes since commit df2908090cda368b01ff43709f51890076c56157: Linux 7.3-rc2 (2026-09-06 15:07:20 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v7.4 for you to fetch changes up to 343cfcbb3ecfdb80aa576a428cfa3b65ad783842: coresight: tnoc: Constify amba_id table (2026-10-09 11:32:08 +0100) ---------------------------------------------------------------- coresight: updates for Linux v7.4 CoreSight selfhosted tracing subsystem updates for Linux v7.4, includes: - Separating the ETM configurations for sysfs and perf to avoid corrupting each other while in use - Hide sysfs control for TRBE as it is not supported - Constify Amba device table for tnoc Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- James Clark (1): coresight: trbe: Hide enable_sink sysfs file Krzysztof Kozlowski (1): coresight: tnoc: Constify amba_id table Yeoreum Yun (14): coresight: etm4x: Prohibit TRCSEQSTR modifications while tracing enabled coresight: etm4x: prohibit modifying cntr_val while session is enabled coresight: etm3x: Prohibit modifying cntr_val while session is enabled coresight: etm4x: fix inconsistencies with sysfs configuration coresight: etm3x: fix inconsistencies with sysfs configuration coresight: etm3x: remove redundant cpu online check on etm_enable_sysfs() coresight: etm4x: introduce struct etm4_caps coresight: etm4x: exclude ss_status from drvdata->config coresight: etm4x: remove s_ex_level from config coresight: etm4x: rename local config as curr_config referring drvdata->curr_config coresight: etm4x: rename drvdata->config to sysfs_config coresight: etm3x: introduce struct etm_caps coresight: etm3x: rename local config as curr_config referring drvdata->curr_config coresight: etm3x: rename drvdata->config to sysfs_config drivers/hwtracing/coresight/coresight-config.c | 18 +- drivers/hwtracing/coresight/coresight-config.h | 22 + drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-etm.h | 48 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 196 +++-- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 461 +++++----- drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 14 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 561 ++++++------ .../hwtracing/coresight/coresight-etm4x-sysfs.c | 961 +++++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 199 +++-- drivers/hwtracing/coresight/coresight-sysfs.c | 15 +- drivers/hwtracing/coresight/coresight-tnoc.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 7 + include/linux/coresight.h | 4 + 14 files changed, 1359 insertions(+), 1150 deletions(-)

5 days, 1 hour

Re: [PATCH] coresight: tnoc: Constify amba_id table

by Suzuki K Poulose

On Sun, 05 Jul 2026 19:19:35 +0200, Krzysztof Kozlowski wrote: > Static 'struct amba_id' table is not modified so can be changed to const > for more safety. > > Applied, thanks! [1/1] coresight: tnoc: Constify amba_id table https://git.kernel.org/coresight/c/343cfcbb3ecf Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

5 days, 1 hour

[PATCH v3 0/8] coresight: Prevent per-thread events from sharing a sink

by James Clark

Concurrent per-thread events results in a WARN on N1SDP which leads to the realization that per-thread events shouldn't have been sharing sinks in the first place. This slips through because different per-thread events will have the same PID if owned by the same process, and we only check the PID and nothing else. That results in unexpected WARNs because it looks like we assumed it couldn't happen (although exclusive PMU rules allow it). But even if it was supported it would result in trace from the wrong thread in another event's per-thread buffer, so we should disallow it. Fix it everywhere the same PID checking logic was copy pasted. Then the PIDs can be dropped from a few structs as they are now unused. Signed-off-by: James Clark <james.clark(a)linaro.org> --- Changes in v3: - Storing and accessing event owners at runtime causes problems due to various scenarios of: events (and sibling events) exiting, children inheriting event FDs, PID reuse, CPU affine events that also have a target process set but different inherit settings. Fix it by creating a session ID in etm_setup_aux() and holding the references in it for the duration of the whole session. (Leo) - Make the ETR buffer allocator consistent with sink sharing rules by not doing numeric PID comparisons there either. - Fix up some Sashiko reports that it sees after interacting with cscfg and taking extra references to tasks and PIDs. - Link to v2: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v2-0-10ac7… Changes in v2: - Fix inherited events by following event->parent - Link to v1: https://lore.kernel.org/r/20260709-james-cs-multiple-per-threads-v1-0-d384e… --- James Clark (8): coresight: tmc-etr: Don't stop Perf cleanup for active sysfs reads coresight: configfs: Don't assume active until cscfg_mgr is set coresight: etm-perf: Flush workqueue before unloading module coresight: tmc-etr: Prevent per-thread events from sharing a sink coresight: tmc-etr: Use session ID for buffer ownership coresight: tmc-etf: Prevent per-thread events from sharing a sink coresight: etb10: Prevent per-thread events from sharing a sink coresight: ultrasoc-smb: Prevent per-thread events from sharing a sink drivers/hwtracing/coresight/coresight-core.c | 28 +-- drivers/hwtracing/coresight/coresight-etb10.c | 33 ++-- drivers/hwtracing/coresight/coresight-etm-perf.c | 79 ++++++++- drivers/hwtracing/coresight/coresight-etm-perf.h | 15 ++ drivers/hwtracing/coresight/coresight-priv.h | 2 - drivers/hwtracing/coresight/coresight-syscfg.c | 6 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 6 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 44 ++--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 207 +++++++++++++---------- drivers/hwtracing/coresight/coresight-tmc.h | 30 ++-- drivers/hwtracing/coresight/coresight-trbe.c | 3 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 25 +-- drivers/hwtracing/coresight/ultrasoc-smb.h | 6 +- include/linux/coresight.h | 5 +- 14 files changed, 294 insertions(+), 195 deletions(-) --- base-commit: 98495b5a4d77dd22e106f462b76e1093a55b29a7 change-id: 20260708-james-cs-multiple-per-threads-ed1d25ed1734 Best regards, -- James Clark <james.clark(a)linaro.org>

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