I've gotten stuck a few times with unusable Coresight after a warm boot
due to lingering claim tags, especially when testing the Coresight
panic patchsets.
This change does some tidy ups, adds some debug messages and clears the
self hosted claim tag on probe. The last two commits are unrelated
tidyups but they touch some of the same functions so to avoid extra
conflicts I'm including them here.
This gets as far as fixing the claim tag issue, but there is some other
state not being cleared on probe that results in the following error.
This can be fixed up as a later change:
coresight tmc_etf0: timeout while waiting for TMC to be Ready
coresight tmc_etf0: Failed to enable : TMC is not ready
James Clark (7):
coresight: Rename coresight_{set,clear}_claim_tags()
coresight: Convert disclaim functions to take a struct cs_access
coresight: Only check bottom two claim bits
coresight: Add claim tag warnings and debug messages
coresight: Clear self hosted claim tag on probe
coresight: Remove inlines from static function definitions
coresight: Remove extern from function declarations
drivers/hwtracing/coresight/coresight-catu.c | 14 +-
drivers/hwtracing/coresight/coresight-core.c | 132 +++++++++++-------
.../hwtracing/coresight/coresight-cti-core.c | 8 +-
drivers/hwtracing/coresight/coresight-etb10.c | 6 +-
drivers/hwtracing/coresight/coresight-etm.h | 6 +-
.../coresight/coresight-etm3x-core.c | 32 ++---
.../coresight/coresight-etm3x-sysfs.c | 8 +-
.../coresight/coresight-etm4x-core.c | 12 +-
.../coresight/coresight-etm4x-sysfs.c | 4 +-
.../hwtracing/coresight/coresight-funnel.c | 4 +-
.../hwtracing/coresight/coresight-platform.c | 26 ++--
drivers/hwtracing/coresight/coresight-priv.h | 20 +--
.../coresight/coresight-replicator.c | 7 +-
drivers/hwtracing/coresight/coresight-stm.c | 6 +-
.../coresight/coresight-syscfg-configfs.c | 2 +-
.../hwtracing/coresight/coresight-tmc-core.c | 9 +-
.../hwtracing/coresight/coresight-tmc-etf.c | 8 +-
.../hwtracing/coresight/coresight-tmc-etr.c | 20 ++-
drivers/hwtracing/coresight/coresight-trbe.c | 18 +--
include/linux/coresight.h | 32 ++---
20 files changed, 209 insertions(+), 165 deletions(-)
--
2.34.1
This patch series is rebased on coresight-next-v6.13.rc2
* Patches 1 & 2 adds support for allocation of trace buffer pages from
reserved RAM
* Patches 3 & 4 adds support for saving metadata at the time of kernel panic
* Patch 5 adds support for reading trace data captured at the time of panic
* Patches 6 & 7 adds support for disabling coresight blocks at the time of
panic
* Patch 8: Gives the full description about this feature as part of
documentation
v13 is posted here,
https://lore.kernel.org/linux-arm-kernel/20241216053014.3427909-1-lcherian@…
Changelog from v13:
* Changed the log levels of crc error check failure prints from dev_dbg to
dev_err as suggested by Suzuki
* Add metadata valid flag checks for successfully opening crashdata files,
as suggested by Suzuki
* Report to the user during probe if valid crash tracedata is found,
as suggested by Suzuki
* Added CRC recalculation upon barrier packet insertion for overflow
cases, this fixes crc check failures upon subsequent boots
* Few other trivial cleanups suggested by Suzuki
Changelog from v12:
* Fixed wrong buffer pointer passed to coresigh_insert_barrier_packet
* tmc_read_prepare/unprepare_crashdata need to be called only once and
hence removed from read path and added to tmc_probe
* tmc_read_prepare_crashdata renamed to tmc_prepare_crashdata and
avoid taking locks as its moved to probe function.
* Introduced read status flag, "reading" specific to reserved buffer to keep the
reserved buffer reading independent of the regular buffer.
* open/release ops for reserved buffer has to take care only about the
set/unset the "reading" status flag as the reserved buffer is prepared
during the probe time itself.
* Few other trivial changes
Changelog from v11:
Convert all commands to literal code blocks, that was missed out in v11.
No other code changes.
Changelog from v10:
* Converted all csdev_access_* to readl functions in tmc_panic_sync_*
* Added "tmc" prefix for register snapshots in struct tmc_crash_metadata
* Converted dev_info to dev_dbg in panic handlers
* Converted dsb to dmb in panic handlers
* Fixed marking metadata as invalid when a user is trying to use the
reserved buffer. Earlier this was wrongly set at the time of reading
reserved trace buffer.
* Moved common validation checks to is_tmc_crashdata_valid and minor
code rearrangements for efficiency
* Got rid of sink specific prepare/unprepare invocations
* Got rid of full from struct tmc_resrv_buf
* While reading crashdata, size is now calculated from metadata instead
of relying on reserved buffer size populated by dtb
* Minor documenation fixes
Changelog from v9:
* Add common helper function of_tmc_get_reserved_resource_by_name
for better code reuse
* Reserved buffer validity and crashdata validity has been separated to
avoid interdependence
* New fields added to crash metadata: version, ffcr, ffsr, mode
* Version checks added for metadata validation
* Special file /dev/crash_tmc_xxx would be available only when
crash metadata is valid
* Removed READ_CRASHDATA mode meant for special casing crashdata reads.
Instead, dedicated read function added for crashdata reads from reserved
buffer which is common for both ETR and ETF sinks as well.
* Documentation added to Documentation/tracing/coresight/panic.rst
Changelog from v8:
* Added missing exit path on error in __tmc_probe.
* Few whitespace fixes, checkpatch fixes.
* With perf sessions honouring stop_on_flush sysfs attribute,
removed redundant variable stop_on_flush_en.
Changelog from v7:
* Fixed breakage on perf test -vvvv "arm coresight".
No issues seen with and without "resrv" buffer mode
* Moved the crashdev registration into a separate function.
* Removed redundant variable in tmc_etr_setup_crashdata_buf
* Avoided a redundant memcpy in tmc_panic_sync_etf.
* Tested kernel panic with trace session started uisng perf.
Please see the title "Perf based testing" below for details.
For this, stop_on_flush sysfs attribute is taken into
consideration while starting perf sessions as well.
Changelog from v6:
* Added special device files for reading crashdata, so that
read_prevboot mode flag is removed.
* Added new sysfs TMC device attribute, stop_on_flush.
Stop on flush trigger event is disabled by default.
User need to explicitly enable this from sysfs for panic stop
to work.
* Address parameter for panicstop ETM configuration is
chosen as kernel "panic" address by default.
* Added missing tmc_wait_for_tmcready during panic handling
* Few other misc code rearrangements.
Changelog from v5:
* Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP
* Fixed a memory leak while reading data from /dev/tmc_etrx in
READ_PREVBOOT mode
* Tested reading trace data from crashdump kernel
Changelog from v4:
* Device tree binding
- Description is made more explicit on the usage of reserved memory
region
- Mismatch in memory region names in dts binding and driver fixed
- Removed "mem" suffix from the memory region names
* Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata",
since it contains more than register snapshot.
Related variables are named accordingly.
* Rename struct tmc_drvdata members
resrv_buf -> crash_tbuf
metadata -> crash_mdata
* Size field in metadata refers to RSZ register and hence indicates the
size in 32 bit words. ETR metadata follows this convention, the same
has been extended to ETF metadata as well.
* Added crc32 for more robust metadata and tracedata validation.
* Added/modified dev_dbg messages during metadata validation
* Fixed a typo in patch 5 commit description
Changelog from v3:
* Converted the Coresight ETM driver change to a named configuration.
RFC tag has been removed with this change.
* Fixed yaml issues reported by "make dt_binding_check"
* Added names for reserved memory regions 0 and 1
* Added prevalidation checks for metadata processing
* Fixed a regression introduced in RFC v3
- TMC Status register was getting saved wrongly
* Reverted memremap attribute changes from _WB to _WC to match
with the dma map attributes
* Introduced reserved buffer mode specific .sync op.
This fixes a possible crash when reserved buffer mode was used in
normal trace capture, due to unwanted dma maintenance operations.
Linu Cherian (8):
dt-bindings: arm: coresight-tmc: Add "memory-region" property
coresight: tmc-etr: Add support to use reserved trace memory
coresight: core: Add provision for panic callbacks
coresight: tmc: Enable panic sync handling
coresight: tmc: Add support for reading crash data
coresight: tmc: Stop trace capture on FlIn
coresight: config: Add preloaded configuration
Documentation: coresight: Panic support
.../bindings/arm/arm,coresight-tmc.yaml | 26 ++
Documentation/trace/coresight/panic.rst | 362 ++++++++++++++++++
drivers/hwtracing/coresight/Makefile | 2 +-
.../coresight/coresight-cfg-preload.c | 2 +
.../coresight/coresight-cfg-preload.h | 2 +
.../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++
drivers/hwtracing/coresight/coresight-core.c | 42 ++
.../hwtracing/coresight/coresight-tmc-core.c | 321 +++++++++++++++-
.../hwtracing/coresight/coresight-tmc-etf.c | 92 ++++-
.../hwtracing/coresight/coresight-tmc-etr.c | 184 ++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 105 +++++
include/linux/coresight.h | 12 +
12 files changed, 1221 insertions(+), 12 deletions(-)
create mode 100644 Documentation/trace/coresight/panic.rst
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c
--
2.34.1
Hi Suzuki,
thanks for the reply! The CPUs of the boards I am using are all based on Arm-v8(.2), but I found the components' addresses in the manuals of the SoCs.
I managed to modify the Devicetree by writing my own .dtsi file (see attachment) and finally got the CoreSight devices in /sys/devices/.
However, dmesg shows the following:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.9.253-coresight (user@user-desktop) (gcc version 7.5.0 (Ubuntu/Linaro 7.5.0-3ubuntu1~18.04) ) #1 SMP PREEMPT Wed Jan 1 18:45:04 CET 2025
[ 0.000000] Boot CPU: AArch64 Processor [411fd071]
(omitted 87 lines)
[ 0.212039] DTS File Name: /home/user/Downloads/Linux_for_Tegra/source/public/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0000-p3449-0000-a02.dts
[ 0.212045] DTB Build time: Jan 1 2025 16:04:45
(omitted 35 lines)
[ 0.420616] DTS File Name: /home/user/Downloads/Linux_for_Tegra/source/public/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0000-p3449-0000-a02.dts
[ 0.420622] DTB Build time: Jan 1 2025 16:04:45
(omitted 75 lines)
[ 0.524166] OF: amba_device_add() failed (-19) for /funnel_bccplex@73001000
(omitted 367 lines)
[ 1.330484] OF: graph: no port node found in /etf@72030000
[ 1.330757] OF: graph: no port node found in /etr@72050000
[ 1.330987] OF: graph: no port node found in /funnel_major@72010000
[ 1.331238] OF: graph: no port node found in /ptm0@73440000
[ 1.331451] coresight-etm4x 73440000.ptm0: CPU0: Cortex-A57 ETM v4.0 initialized
[ 1.331482] OF: graph: no port node found in /ptm1@73540000
[ 1.331689] coresight-etm4x 73540000.ptm1: CPU1: Cortex-A57 ETM v4.0 initialized
[ 1.331719] OF: graph: no port node found in /ptm2@73640000
[ 1.331938] coresight-etm4x 73640000.ptm2: CPU2: Cortex-A57 ETM v4.0 initialized
[ 1.331944] extcon-disp-state extcon:disp-state: cable 47 state 0
[ 1.331946] Extcon AUX1(HDMI) disable
[ 1.331976] OF: graph: no port node found in /ptm3@73740000
[ 1.332192] coresight-etm4x 73740000.ptm3: CPU3: Cortex-A57 ETM v4.0 initialized
[ 1.332250] OF: graph: no port node found in /replicator@72040000
[ 1.332305] coresight-replicator-qcom 72040000.replicator: REPLICATOR 1.0 initialized
[ 1.332350] OF: graph: no port node found in /stm@72070000
[ 1.332386] coresight-stm 72070000.stm: stm_register_device failed, probing deffered
(omitted 64 lines)
[ 1.411751] OF: graph: no port node found in /stm@72070000
[ 1.412025] coresight-stm 72070000.stm: STM32 initialized
(omitted 212 lines)
Do you have an idea what I did wrong? In the end, I want to be able to follow the steps described here:
https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-3275/index.html#pa…
Best regards,
Vincent
(P.S. There was a problem sending this email a first time, but it should work now)
Hi,
We are not seeing these problems on other systems with multiple ETMs.
How are you using the system?
Perf will strictly disable sources before sinks - which would mean
that the ETMs will flush before the TMC requests a manual flush on
stop.
For sysfs use, we recommend the same, but even halting the TMC first
should result in all sources being requested to flush at the same time
(subject to propagation through connected trace funnels).
On Fri, 7 Feb 2025 at 07:25, Yuanfang Zhang <quic_yuanfang(a)quicinc.com> wrote:
>
>
>
> On 2/6/2025 6:32 PM, Leo Yan wrote:
> > Hi Yuanfang,
> >
> > On Fri, Jan 03, 2025 at 04:01:54PM +0800, Yuanfang Zhang wrote:
> >>
> >> When multiple ETMs are enabled simultaneously, the time required
> >> to complete a flush in the process of reading the TMC device node
> >> may exceed the default wait time of 100us.
> >
How do you know that it is the ETM flush process that is the issue?
TMC ready can be delayed by issues in the memory system that prevent
write to the memory buffer.
The TMC flush complete will indicate completion of flush for all
connected devices - so if flush complete is indicated by the TMC then
a flush request cannot be the issue.
With multiple ETMs, then the connected trace funnels arbitration will
ensure flush is indicated complete on all connected inputs before
transmitting to the output.
The driver code to stop the TMC will first wait on flush complete
before waiting on TMC ready.
> > Have you tried how long time would be safe to wait for the
> > TMCREADY_BIT bit to be set on your platform?
> yes, 400000us.
This is a huge amount of latency for a coresight system. This
suggests some sort of contention issue.
> >
> >> If the TMC capture is stopped while any ETM has not completed its
> >> flush, it can cause the corresponding CPU to hang.
> >>
There is nothing in the ETMv4 hardware specification /design that
should cause an CPU to hang. There is an implementation dependent
stall mechanism that if implemented can stall a PE when the ETM fifo
approaches overflow, but this is switch off on the drivers, if
implemented on the hardware.
The flush process for the ETM is a purely internal process of clearing
out all trace currently in the ETM, and is not dependent on the PE.
> >> Fix the by checking the TMCReady bit after the flush. If TMCReady
> >> bit is set, TraceCaptEn bit can be clear; otherwise, return directly
> >> and stop the TMC read.
> >
> > When a timeout for TMC flush and stop is detected, if the driver
> > arbitrarily bails out without disabling TMC, this would leave the
> > hardware always on.
> >
I agree that this is not an acceptable solution - we cannot leave the
TMC in an indeterminate state.
Where clients such as perf are using the hardware there is no
mechanism for re-trying if halt fails.
The functions you have changed seem to relate to reading the buffer
via sysfs. Do you see similar problems using perf to collect trace
data?
> > I would like first know if a longer timeout can fix the issue.
> >
> > Thanks,
> > Leo
> >
> yes, longer timeout can fix this issue.
>
I think that a longer timeout will mask some underlying contention
issue, but it should be possible to make the coresight driver timeout
configurable, and set the value appropriately for your system.
There is a new TMC logging patchset here:
https://lists.linaro.org/archives/list/coresight@lists.linaro.org/thread/7Y…
which improves the error reporting around timeouts. This might help
establish if the error is in waiting for flush complete, or TMC ready.
This API could be extended to add a timeout value parameter, that can
be configured from the TMC driver, set via sysfs for the TMC in the
initial case to further debugging of this issue on your system
Regards
Mike
> >> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
> >> ---
> >> drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++++++++++++++--
> >> drivers/hwtracing/coresight/coresight-tmc-etr.c | 22 +++++++++++++++++-----
> >> 2 files changed, 32 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> >> index d4f641cd9de69488fe3d1c1dc9b5a9eafb55ed59..bded290c42891d782344d9a6e63ebdbed6719133 100644
> >> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> >> @@ -80,11 +80,21 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
> >> return;
> >> }
> >>
> >> -static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> >> +static int __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> >> {
> >> + int rc;
> >> +
> >> CS_UNLOCK(drvdata->base);
> >>
> >> tmc_flush_and_stop(drvdata);
> >> +
> >> + rc = tmc_wait_for_tmcready(drvdata);
> >> + if (rc) {
> >> + dev_err(&drvdata->csdev->dev,
> >> + "Failed to disable : TMC is not ready\n");
> >> + CS_LOCK(drvdata->base);
> >> + return rc;
> >> + }
> >> /*
> >> * When operating in sysFS mode the content of the buffer needs to be
> >> * read before the TMC is disabled.
> >> @@ -94,6 +104,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> >> tmc_disable_hw(drvdata);
> >>
> >> CS_LOCK(drvdata->base);
> >> + return 0;
> >> }
> >>
> >> static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> >> @@ -650,7 +661,9 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
> >> ret = -EINVAL;
> >> goto out;
> >> }
> >> - __tmc_etb_disable_hw(drvdata);
> >> + ret = __tmc_etb_disable_hw(drvdata);
> >> + if (ret)
> >> + goto out;
> >> }
> >>
> >> drvdata->reading = true;
> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> >> index a48bb85d0e7f44a25b813f3c828cc3d705d16012..63a1f7501562fa0b5c2fe6ea53dce4d82842bec3 100644
> >> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> >> @@ -1135,11 +1135,21 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
> >> }
> >> }
> >>
> >> -static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> >> +static int __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> >> {
> >> + int rc;
> >> +
> >> CS_UNLOCK(drvdata->base);
> >>
> >> tmc_flush_and_stop(drvdata);
> >> +
> >> + rc = tmc_wait_for_tmcready(drvdata);
> >> + if (rc) {
> >> + dev_err(&drvdata->csdev->dev,
> >> + "Failed to disable : TMC is not ready\n");
> >> + CS_LOCK(drvdata->base);
> >> + return rc;
> >> + }
> >> /*
> >> * When operating in sysFS mode the content of the buffer needs to be
> >> * read before the TMC is disabled.
> >> @@ -1150,7 +1160,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> >> tmc_disable_hw(drvdata);
> >>
> >> CS_LOCK(drvdata->base);
> >> -
> >> + return 0;
> >> }
> >>
> >> void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> >> @@ -1779,9 +1789,11 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
> >> }
> >>
> >> /* Disable the TMC if we are trying to read from a running session. */
> >> - if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS)
> >> - __tmc_etr_disable_hw(drvdata);
> >> -
> >> + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) {
> >> + ret = __tmc_etr_disable_hw(drvdata);
> >> + if (ret)
> >> + goto out;
> >> + }
> >> drvdata->reading = true;
> >> out:
> >> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> >>
> >> ---
> >> base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4
> >> change-id: 20250103-fix_cpu_hung-b5a95179ada4
> >>
> >> Best regards,
> >> --
> >> Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
> >>
> >>
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
This patch series is rebased on coresight-next-v6.12.rc4
* Patches 1 & 2 adds support for allocation of trace buffer pages from
reserved RAM
* Patches 3 & 4 adds support for saving metadata at the time of kernel panic
* Patch 5 adds support for reading trace data captured at the time of panic
* Patches 6 & 7 adds support for disabling coresight blocks at the time of panic
* Patch 8: Gives the full description about this feature as part of documentation
v12 is posted here,
https://lore.kernel.org/linux-arm-kernel/20241129084714.3057080-1-lcherian@…
Changelog from v12:
* Fixed wrong buffer pointer passed to coresigh_insert_barrier_packet
* tmc_read_prepare/unprepare_crashdata need to be called only once and
hence removed from read path and added to tmc_probe
* tmc_read_prepare_crashdata renamed to tmc_prepare_crashdata and
avoid taking locks as its moved to probe function.
* Introduced read status flag, "reading" specific to reserved buffer to keep the
reserved buffer reading independent of the regular buffer.
* open/release ops for reserved buffer has to take care only about the
set/unset the "reading" status flag as the reserved buffer is prepared
during the probe time itself.
* Few other trivial changes
Changelog from v11:
Convert all commands to literal code blocks, that was missed out in v11.
No other code changes.
Changelog from v10:
* Converted all csdev_access_* to readl functions in tmc_panic_sync_*
* Added "tmc" prefix for register snapshots in struct tmc_crash_metadata
* Converted dev_info to dev_dbg in panic handlers
* Converted dsb to dmb in panic handlers
* Fixed marking metadata as invalid when a user is trying to use the
reserved buffer. Earlier this was wrongly set at the time of reading
reserved trace buffer.
* Moved common validation checks to is_tmc_crashdata_valid and minor
code rearrangements for efficiency
* Got rid of sink specific prepare/unprepare invocations
* Got rid of full from struct tmc_resrv_buf
* While reading crashdata, size is now calculated from metadata instead
of relying on reserved buffer size populated by dtb
* Minor documenation fixes
Changelog from v9:
* Add common helper function of_tmc_get_reserved_resource_by_name
for better code reuse
* Reserved buffer validity and crashdata validity has been separated to
avoid interdependence
* New fields added to crash metadata: version, ffcr, ffsr, mode
* Version checks added for metadata validation
* Special file /dev/crash_tmc_xxx would be available only when
crash metadata is valid
* Removed READ_CRASHDATA mode meant for special casing crashdata reads.
Instead, dedicated read function added for crashdata reads from reserved
buffer which is common for both ETR and ETF sinks as well.
* Documentation added to Documentation/tracing/coresight/panic.rst
Changelog from v8:
* Added missing exit path on error in __tmc_probe.
* Few whitespace fixes, checkpatch fixes.
* With perf sessions honouring stop_on_flush sysfs attribute,
removed redundant variable stop_on_flush_en.
Changelog from v7:
* Fixed breakage on perf test -vvvv "arm coresight".
No issues seen with and without "resrv" buffer mode
* Moved the crashdev registration into a separate function.
* Removed redundant variable in tmc_etr_setup_crashdata_buf
* Avoided a redundant memcpy in tmc_panic_sync_etf.
* Tested kernel panic with trace session started uisng perf.
Please see the title "Perf based testing" below for details.
For this, stop_on_flush sysfs attribute is taken into
consideration while starting perf sessions as well.
Changelog from v6:
* Added special device files for reading crashdata, so that
read_prevboot mode flag is removed.
* Added new sysfs TMC device attribute, stop_on_flush.
Stop on flush trigger event is disabled by default.
User need to explicitly enable this from sysfs for panic stop
to work.
* Address parameter for panicstop ETM configuration is
chosen as kernel "panic" address by default.
* Added missing tmc_wait_for_tmcready during panic handling
* Few other misc code rearrangements.
Changelog from v5:
* Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP
* Fixed a memory leak while reading data from /dev/tmc_etrx in
READ_PREVBOOT mode
* Tested reading trace data from crashdump kernel
Changelog from v4:
* Device tree binding
- Description is made more explicit on the usage of reserved memory
region
- Mismatch in memory region names in dts binding and driver fixed
- Removed "mem" suffix from the memory region names
* Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata",
since it contains more than register snapshot.
Related variables are named accordingly.
* Rename struct tmc_drvdata members
resrv_buf -> crash_tbuf
metadata -> crash_mdata
* Size field in metadata refers to RSZ register and hence indicates the
size in 32 bit words. ETR metadata follows this convention, the same
has been extended to ETF metadata as well.
* Added crc32 for more robust metadata and tracedata validation.
* Added/modified dev_dbg messages during metadata validation
* Fixed a typo in patch 5 commit description
Changelog from v3:
* Converted the Coresight ETM driver change to a named configuration.
RFC tag has been removed with this change.
* Fixed yaml issues reported by "make dt_binding_check"
* Added names for reserved memory regions 0 and 1
* Added prevalidation checks for metadata processing
* Fixed a regression introduced in RFC v3
- TMC Status register was getting saved wrongly
* Reverted memremap attribute changes from _WB to _WC to match
with the dma map attributes
* Introduced reserved buffer mode specific .sync op.
This fixes a possible crash when reserved buffer mode was used in
normal trace capture, due to unwanted dma maintenance operations.
Linu Cherian (8):
dt-bindings: arm: coresight-tmc: Add "memory-region" property
coresight: tmc-etr: Add support to use reserved trace memory
coresight: core: Add provision for panic callbacks
coresight: tmc: Enable panic sync handling
coresight: tmc: Add support for reading crash data
coresight: tmc: Stop trace capture on FlIn
coresight: config: Add preloaded configuration
Documentation: coresight: Panic support
.../bindings/arm/arm,coresight-tmc.yaml | 26 ++
Documentation/trace/coresight/panic.rst | 362 ++++++++++++++++++
drivers/hwtracing/coresight/Makefile | 2 +-
.../coresight/coresight-cfg-preload.c | 2 +
.../coresight/coresight-cfg-preload.h | 2 +
.../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++
drivers/hwtracing/coresight/coresight-core.c | 42 ++
.../hwtracing/coresight/coresight-tmc-core.c | 308 ++++++++++++++-
.../hwtracing/coresight/coresight-tmc-etf.c | 92 ++++-
.../hwtracing/coresight/coresight-tmc-etr.c | 184 ++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 105 +++++
include/linux/coresight.h | 12 +
12 files changed, 1208 insertions(+), 12 deletions(-)
create mode 100644 Documentation/trace/coresight/panic.rst
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c
--
2.34.1
When multiple ETMs are enabled simultaneously, the time required
to complete a flush in the process of reading the TMC device node
may exceed the default wait time of 100us. If the TMC capture is
stopped while any ETM has not completed its flush, it can cause
the corresponding CPU to hang.
Fix the by checking the TMCReady bit after the flush. If TMCReady
bit is set, TraceCaptEn bit can be clear; otherwise, return directly
and stop the TMC read.
Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 17 +++++++++++++++--
drivers/hwtracing/coresight/coresight-tmc-etr.c | 22 +++++++++++++++++-----
2 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index d4f641cd9de69488fe3d1c1dc9b5a9eafb55ed59..bded290c42891d782344d9a6e63ebdbed6719133 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -80,11 +80,21 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
return;
}
-static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
+static int __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
{
+ int rc;
+
CS_UNLOCK(drvdata->base);
tmc_flush_and_stop(drvdata);
+
+ rc = tmc_wait_for_tmcready(drvdata);
+ if (rc) {
+ dev_err(&drvdata->csdev->dev,
+ "Failed to disable : TMC is not ready\n");
+ CS_LOCK(drvdata->base);
+ return rc;
+ }
/*
* When operating in sysFS mode the content of the buffer needs to be
* read before the TMC is disabled.
@@ -94,6 +104,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
tmc_disable_hw(drvdata);
CS_LOCK(drvdata->base);
+ return 0;
}
static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
@@ -650,7 +661,9 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
ret = -EINVAL;
goto out;
}
- __tmc_etb_disable_hw(drvdata);
+ ret = __tmc_etb_disable_hw(drvdata);
+ if (ret)
+ goto out;
}
drvdata->reading = true;
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index a48bb85d0e7f44a25b813f3c828cc3d705d16012..63a1f7501562fa0b5c2fe6ea53dce4d82842bec3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1135,11 +1135,21 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
}
}
-static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+static int __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
{
+ int rc;
+
CS_UNLOCK(drvdata->base);
tmc_flush_and_stop(drvdata);
+
+ rc = tmc_wait_for_tmcready(drvdata);
+ if (rc) {
+ dev_err(&drvdata->csdev->dev,
+ "Failed to disable : TMC is not ready\n");
+ CS_LOCK(drvdata->base);
+ return rc;
+ }
/*
* When operating in sysFS mode the content of the buffer needs to be
* read before the TMC is disabled.
@@ -1150,7 +1160,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
tmc_disable_hw(drvdata);
CS_LOCK(drvdata->base);
-
+ return 0;
}
void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
@@ -1779,9 +1789,11 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
}
/* Disable the TMC if we are trying to read from a running session. */
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS)
- __tmc_etr_disable_hw(drvdata);
-
+ if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) {
+ ret = __tmc_etr_disable_hw(drvdata);
+ if (ret)
+ goto out;
+ }
drvdata->reading = true;
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
---
base-commit: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4
change-id: 20250103-fix_cpu_hung-b5a95179ada4
Best regards,
--
Yuanfang Zhang <quic_yuanfang(a)quicinc.com>