== Week of March 17th ==
- STREAM regression (TCWG-388, 4/10)
-- Investigated how to prioritize memory references instructions in GCC scheduler to take full advantage of L2 autopretch hardware in certain ARM cores.
-- Fixed -fdbg-cnt=sched_insn debug counter along the way. It appear to have been broken since GCC 4.7.
- Discussed reg_pressure instruction scheduling with Charlie. (TCWG-135, 1/10)
- Various discussions about instruction scheduling in GCC. (1/10)
- Together with Michael prepared patch list for GCC contingency plan. (3/10)
- Made first-in-series video about tips-and-trick of GCC development. Your critiques are welcome!
-- Using GCC debug counters (7m34s): https://www.youtube.com/watch?v=IWRYCOkgL04
== Week of March 24th ==
- STREAM regression (TCWG-388)
-- Get a prototype patch.
- Other expected and unexpected tasks that come up.
--
Maxim Kuvyrkov
www.linaro.org
Last week
* one day off [2/10]
* NEON scheduling investigation - TCWG-135 [3/10]
. investigated scheduler register pressure heuristics
. call with Maxim about scheduling algorithm
. still more investigation required
* NEON intrinsics vs assembler libvpx performance difference
investigation [5/10]
. GCC seems to generate poor code for address generation in NEON loads/stores
. maybe some improvements to the intrinsics code would also be possible
Plan:
. write down some conclusions about libvpx performance
. investigate PR60609
. more on TCWG-135
. investigate LP1296676 & LP1296601 ICEs when building the kernel
== Progress ==
Machine descriptions for stack smashing in Aarch64 - TCWG-23 (5/10)
* Completed building QEMU for Aarch64 on Ubuntu 13.10. Ran
regression tests on it.
* Submitted patches for libssp as per Marcus suggestions and got it approved.
PGO support for Aarch64 -TCWG- 179 (2/10)
* Installed "CPU2006" tools in foundation model running open embedded image
and started running benchmarks. Plan is to build it with -PGO next.
Bug fix (2/10)
* Working on reproducing and fixing PR60617.
Misc (1/10)
* AMD Internal meeting and work.
== Plan ==
* Bug fix PR60617.
* Build CPU006 benchmarks with -PGO flag
* Restart PGO bootstrap failure investigations
Hi,
I read in the armv8 architecture reference manual that a number of AArch32 instructions have been obsoleted. Do the current armv7 version of GCC ever generate code containing any of these, without me explicitly writing inline assembly? If it can, how can this be turned off? Just would like to make sure that a C-program (without inline assembly) compiled today for armv7 will run in AArch32 mode when armv8 boards come out.
The following are obsoleted in ARMv8:
A32 SWP and SWPB instructions.
Jazelle (only trivial implementations are supported).
VFP short vectors and asynchronous bounces.
Fast Context Switch Extension (FCSE).
Thanks: Magnus
Magnus Karlsson
Software Development Engineering Manager
LSI Corporation
Box 1024, Knarrarnäsgatan 15
SE-164 21 Kista, Sweden
TEL +46 8 594 607 09
FAX +46 8 594 607 10
CELL +46 73 80 444 88
magnus.karlsson(a)lsi.com
== Issues ==
* none
== Progress ==
* LRA on AArch32:
o TCWG-343 : Make LRA the default for the ARM backend (0/10)
- Stop progress on this card, will close it when FSF 4.9 will be released.
o TCWG-345 : Analyse performance of LRA for ARM. (4/10)
- Spec2K figures on Cortex-a15 Analysis.
- re-run benchs in console mode chrubuntu without ASLR + perf tool
* Backports review: (2/10)
o Start to prepare cortex-a53 backports review
* Misc:
o Various meetings and slideware (4/10).
- Linaro and internal ones.
== Next ==
- continue cortex-a53 review
- some backports to do.
- continue on TCWG-345
== Progress ==
* Worked on getting eglibc git mirror back up and running
* Released eglibc 2.19 2014.04
* Respin of glibc aarch64 setcontext patches
* Respin of ld aarch64 RELASZ patch
* Tidied up, rebased and committed ARM ld pointer equality patch
* Work on resurrecting glibc benchmark result graphing script
* Holiday on Friday
== Issues ==
* Couple of hours power outage on Monday
== Plan ==
* Get outstanding glibc and binutils patches committed
* Reorganise JIRA cards for malloc work
* glibc benchmarking
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Add support for fork/vfork/exec events/catchpoints in remote
gdbserver [TCWG-263] [4/10]
-- Debugged catchpoint code and reviewed gdbserver implementation for events.
-- Still require a lot of code understanding before actual
implementation can start.
* Wrote a script that takes two gdb build trees and configuration
arguments to test them in native, remote-native and remote-target
configurations [TCWG-96] [3/10]
* Laptop OS re-install [1/10]
* GDB open cards issues review [1/10]
* Sick half day off on Friday [1/10]
== Plan ==
* Complete work on TCWG-96.
-- Write a script that tests gdb in remote-native configuration using ssh.
-- Integrate all testing scripts and test them.
-- Update wiki page with updated scripts and how to use them.
* Monday Day Off: Pakistan Day 23rd March public holiday roll over.
== Progress ==
CARD-1210 - optimizing prologue/epilogue With -fomit-frame-pointer (4/10)
- regression tested the patch and fixed issues
- Dropping the patch and closing the card as it has been worked on at arm.
TCWG-15 - zero/sign extension elimination for crc (3/10)
- Looked at crc and looked at the other optimizations listed in card 440.
- Improved the local patch to remove the missing optimization
TCWG-413 - Running spec2006 with aarch64 (3/10)
- Built and set-up spec2006.
- Ran into to some compile time and run time errors
== Plan ==
Continue with zero/sign extension elimination
Start looking at literal pool merging
== This week ==
Merged all backports related to a53 support and successfully built arm
and aarch64 cross compilers:
202333 - [AArch64, ARM] Introduce "mrs" type attribute.
202334 - [AArch64] Use neon_<ldm,stm>_2 where appropriate as "type".
202448 - [AArch64] Prevent generic pipeline description from dominating
other pipeline descriptions.
202560 - set "type" attribute properly in arm_cmpsi_insn, cleanup
203241 - Cortex-a53 use Cortex tuning
203611 – 203621 – Neon types Parts 1 to 10
204575 - [ARM, AArch64] Make aarch-common.c files more robust.
205050 - [ARM] Add missing type attribute to zero_extend on arm
204782 - [AArch64] [-mtune cleanup 2/5] Tune for Cortex-A53 by default.
204784 - [AArch64] [-mtune cleanup 4/5] Remove "example-1", "example-2"
tuning options.
204852 - [AArch64] Remove simd_type
205014 - [AArch64] Remove v8type attribute.
205105 - [AArch64] Remove "mode", "mode2" attributes
204783 - [AArch64] [-mtune cleanup 3/5] [Temporary] When asked to tune
for Cortex-A57, tune for Cortex-A15
== Next week ==
Test a53 support
Backport vectorization bug
== Future ==
== Issues ==
* None
== Progress ==
* Identify a missing instruction pattern which blocks fcsel
optimization. A patch was sent out for community review. [2/10,
TCWG-309]
* Identify a ICE when handling dwarf-info in ARM backend when testing
shrink-wrap. A fix was committed to trunk. [2/10]
* Rebase and test the shrink-wrap codes for APCS_FRAME. [5/10]
* Prepare Linaro toolchain 2014.03 binaries release [1/10].
* Investigate CRC improvement chances.
== Plans ==
* Create a prebuilt sysroot based on Linaro eglibc-2014.04.
* Continue on shrink-wrap.
