I'm working on my HiKey. I'm trying to enable CRC extension on ARMv8
in the assembler regardless of the way GCC was built, and regardless
of the user's CFLAGS and CXXFLAGS. I'm encountering an assembler
error: "unknown pseudo-op: `.arch_extension'".
According to [1], I can use ".arch_extension" to enable it. According
to [2], ".arch_extension" is available in GCC 4.6 and GAS 2.21. My
version of Linaro provides GCC 4.9.2 and GAS 2.25.90. I can also
duplicate the issue on GCC113 (compiel farm), which provides GCC 4.8
and GAS 2.24.
The test program is below. Trying to compile it results in:
$ g++ test.cxx -c
/tmp/ccVZ6hiq.s: Assembler messages:
/tmp/ccVZ6hiq.s:24: Error: unknown pseudo-op: `.arch_extension'
/tmp/ccVZ6hiq.s:25: Error: selected processor does not support `crc32b w1,w0,w0'
Trying to compile without ".arch_extension" results in:
$ g++ test.cxx -c
/tmp/cci4wu6d.s: Assembler messages:
/tmp/cci4wu6d.s:24: Error: selected processor does not support `crc32b w1,w0,w0'
Its almost as if ".arch_extension" is not being properly recognized or consumed.
Any ideas what might be going wrong here?
**********
The program:
$ cat test.cxx
#include <arm_neon.h>
#define GCC_INLINE_ATTRIB __attribute__((__gnu_inline__,
__always_inline__, __artificial__))
#if defined(__GNUC__) && !defined(__ARM_FEATURE_CRC32)
__inline unsigned int GCC_INLINE_ATTRIB
CRC32B(unsigned int crc, unsigned char v)
{
unsigned int r;
asm (" \n"
".arch_extension crc \n"
"\t" "crc32b %w2, %w1, %w0 \n"
: "=r"(r) : "r"(crc), "r"((unsigned int)v));
return r;
}
#else
// just use the instrinsic
# define CRC32B(a,b) __crc32b(a,b)
#endif
int main(int argc, char* argv[])
{
return CRC32B(argc, argc);
}
**********
Versions...
$ gcc --version
gcc (Ubuntu/Linaro 4.8.4-2ubuntu1~14.04.3) 4.8.4
$ as -v
GNU assembler version 2.24 (aarch64-linux-gnu) using BFD version (GNU
Binutils for Ubuntu) 2.24
$ lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 14.04.5 LTS
Release: 14.04
Codename: trusty
[1] https://sourceware.org/binutils/docs/as/AArch64-Directives.html#AArch64-Dir…
[2] https://gcc.gnu.org/ml/gcc-help/2012-07/msg00180.html
* Child care (2/10)
== Progress ==
o Linaro GCC/Validation (5/10)
* Released GCC 5 and 6 Linaro source sanpshots
* Progressing on release automation
* Preparing GCC 7 preview release:
- found a build issue for mingw toolchains
- proposed a fix upstream, discussion on-going.
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o Continue release on automation and prepare 2017.05 RC
== Progress ==
* Validation
- kernelci/lava-ci scripts update broke my prototype. We need more
discussion at this point.
- benchmarking scripts, debugging with Jenkins
- reviews
* GCC
- reported a regression on trunk after an LRA fix, now fixed by Vladimir.
- bootstrapping gcc-5 on armv7 (using present continuous because
it's taking so long)
- Linaro bugzilla
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation?
* Benchmarking: debug scripts/jenkins/board setup
* Off Monday 17th
[TCWG-614] Range Thunks
- No review progress, blocked on a request for some refactoring to
unify the address allocation.
[TCWG-1088] Refactoring of address assignment
- Found out that linker scripts can break ARM exceptions in the same
way as they can break the thunk insertion
- Made a prototype of unified address allocation that is good enough
for the current interworking range thunks. This passes the existing
test case that I made to show that linker scripts could break the Mips
LA25 thunk placement.
[TCWG-1089] Fixed problem with ARM exceptions and identical code folding
Plans for next week:
On Holiday Tuesday
[TCWG-1088] Polish up patches and send for review.
Planned Absences:
Tuesday 18th April
Wednesday - Friday 27 - 29 April ACCU 2017
# Progress #
* TCWG-1050, GDB 8.0 release. [4/10]
Release branch is not created, but a lot of C++
patches are posted, and massively change the code even when release
is coming.
** Fix PR 19942, patch v2 is OK. Committed.
** Intel btrace python interface. Intel people posted patches to
adjust the interface as I requested. Reviewing them. They look
much better.
* TCWG-1040, Review SVE patches. [4/10]
SVE patches review. Read Alan's patches and various GDB backends,
like mips, xtensa, and ia64. Feel nervous to approve them because we
have no way testing them. Figure out a unit test to related methods,
and it works well if I build GDB with ASAN. This unit test does find
some existing issues, and patches are posted. In order to make the
test more useful, need to C++-fy regcache, not a small piece of work.
* Upstream reviews [2/10]
** Software single-step on arm-non-eabi. Convince the author that his
patch will break GDB's default behavior, and give some thoughts on
fixing it.
** Propose to deprecate ARM FPA in GDB.
So far, I am not clear what is the "right" process to deprecate
features in GDB. (I know how to deprecate ports and commands).
** Some one complains GDB can't unwind from arm64 kernel irq vector,
which is hand written asm. The fix should be using .cfi directives
to annotate them, however, they want GDB to error out if it can't
unwind. I am suggested to ask in linux-arm-kernel(a)lists.infradead.org
about the expected behavior. Will do next week.
# Plan #
* Mon and Tue off.
* Figure out more ways to test code touched by SVE patches. Convert
regcache to class if necessary.
--
Yao Qi
== Progress ==
* Out of office on Friday [2/10]
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039] [2/10]
- Committed G_FPOW and G_FADD upstream
- Most of the other soft float libcalls are just a matter of boilerplate
* [GlobalISel] Investigate divmod [TCWG-1086] [5/10]
- Working on a patch to support G_(S|U)REM in GlobalISel
- Found an inconsistency in DAGISel, sent a patch upstream
* Misc [1/10]
- Mailing lists, meetings
- Buildbot monitoring (did a bisection, reverted a few patches)
== Plan ==
* Out of office on Monday
* Send patch for TCWG-1086
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.04 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.3+svn246668 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246668
* Backport of [Bugfix] [AArch32] PR target/71436: Restrict
*load_multiple pattern till after LRA
* Backport of [Bugfix] [AArch32] PR target/79911: Invalid vec_select arguments
* Backport of [Bugfix] [AArch64] PR target/79889: Error message on
target attribute on aarch64
* Backport of [Bugfix] [AArch64] PR target/79913: VEC_SELECT bugs in
aarch64 patterns
* Backport of [Bugfix] [AArch64] PR target/79925: tweaks to quoting in
error messages
* Backport of [AArch32] Fix small multiply feature
* Backport of [AArch64] Enable AES fusion with -mcpu=generic
* Backport of [AArch64] Fix bootstrap due to wide_int .elt (0) uninit warning
* Backport of [AArch64] Fix incorrect INS in SIMD mov pattern
* Backport of [AArch64] Fix search_line_fast for aarch64/ILP32
* Backport of [AArch64] Fix typo in aarch64.opt (dummping -> dumping)
* Backport of [AArch64] Improve cost model for ThunderX2 CN99xx
* Backport of [AArch64] Improve generic branch cost
* Backport of [AArch64] more poly64 intrinsics and tests
* Backport of [AArch64] Use 'x' constraint for vector HFmode
multiplication by indexed element instructions
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn246667 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the next
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2017.04/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.4+svn246667
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1] Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2] Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [4/10] Release branch is not created,
but test result
looks good.
** Fix PR 19942, patch v2 is OK. Need to fix some nits before check
in.
** Intel btrace python interface discussion. Good to see that Intel
people accept my suggested new interface, and finalize the details of
the new interface.
* TCWG-1040, Review SVE patches. [4/10]
The overall goal is to remove MAX_REGISTER_SIZE.
Reviewed some Alan's patches, and wrote two patches to remove
MAX_REGISTER_SIZE in frame.c and regcache.c.
* Misc, meeting, [2/10]
~ Plan ~
* More remote tests for GDB 8.0 release.
* SVE patches review, and start to think about GDB target description
changes for SVE.
* Public holiday on Friday and next Monday.
--
Yao Qi
== Progress ==
[TCWG-614] Long Range Thunks
- Posted for upstream review. I may have to do some refactoring of the
address allocation first to unify the linker-script and non
linker-script cases.
- Started work on a prototype that fabricates linker script commands
for the default non linker-script case. Failing 7 tests of 1007 and it
is a mess so some work to do here.
[TLS] Fixed recent breakage in ARM TLS caused by change in the way
that values are written to the GOT.
== Plans ==
Progress the prototype address allocation far enough to post upstream
for comment, I think that this is likely to take a few iterations to
get right.
== Planned Absences ==
ACCU 2017 27-29 April
