== Progress ==
* FDPIC
- GCC: handling feedback on v2 patches
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, again
- discussing collaboration with kernel-ci
* Linaro gcc-7 release
- backported fixes for bug #4007
* Newlib
- sent a few small patches to remove warnings when building for Arm and Aarch64
* misc (conf-calls, meetings, emails, ....)
- (internal) Wrote report about GNU Cauldron 2018
== Next ==
FDPIC:
- GCC: send v3 patches feedback
- uclibc-ng: look at how to test fdpic mode with openadk
Progress:
[VIRT-214 # SVE System Registers ]
Posted v2 patch set for eliminating redundancy between
feature bits and id registers.
[VIRT-249 # SVE System Mode ]
Posted v2 patch set, without the system registers included.
[Upstream]
First 3.1 tcg-next pull request.
Spent a day working on Emilo's suggestion to out-line the entire softmmu
load/store operation. I've placed a shed load of small code segments
within the tcg "prologue", which is within a direct call of the entire
code_gen_buffer. Emilio got some performance numbers from that which
look promising. Need to clean up the patch to work with 32-bit and win64.
[GCC]
V1 of my SUSE+ARM inspired -matomic-ool patch set posted. Includes some
significant improvements to atomic operations in the aarch64 backend.
Got some good feedback and am working my way through those.
r~
* Recovery from Cauldron, then from Connect
== Progress ==
* FDPIC
- GCC: handling feedback on v2 patches
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, again
* Linaro gcc-7 release
- backported fixes for bug #4007
* Newlib
- checked warnings emitted by GCC during newlib build, will send small patches
* misc (conf-calls, meetings, emails, ....)
- Attended Linaro Connect YVR18, contributed to report
== Next ==
FDPIC:
- GCC: handle v2 patches feedback
- uclibc-ng: look at how to test fdpic mode with openadk
- look at how to use Linux kernel atomics
o LLVM
* Machine Outliner on ARM prototype:
- Improved stack fixup handling
- Completed Thumb2 support
- Fixed an issue in Thumb and ARM related to conditional execution
* Bots babysitting
o Misc
* Various meetings and discussions.
SVE Support ([VIRT-198])
========================
- generated a [narrow test case for fdiv_64 rounding error]
- doesn't hit much code but I possibly misunderstanding [the code]
AFAICT inc = ((frac & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 :
0); seems reasonable
[VIRT-198] https://projects.linaro.org/browse/VIRT-198
[narrow test case for fdiv_64 rounding error]
https://github.com/stsquad/qemu/tree/testing/generic-op-tester
[the code]
https://github.com/stsquad/qemu/blob/testing/generic-op-tester/fpu/softfloa…
QEMU Tooling ([VIRT-252])
=========================
[VIRT-252] https://projects.linaro.org/browse/VIRT-252
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
QEMU plugin support ([VIRT-280])
- following discussion with team started adding plugin hooks to
[tracepoint clean-up]
- I think I need to resurrect and expand the cputlb de-macro stuff
to cleanly add memory tracing
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
[tracepoint clean-up]
https://github.com/stsquad/qemu/tree/misc/dfilter-and-trace-tweaks-v2
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v1 0/4} fixes for kvm/arm64 guest debug Message-Id:
<20180926112048.17778-1-alex.bennee(a)linaro.org>
- posted {PATCH} cpus: fix TCG kick timer leak Message-Id:
<20180927171724.30128-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other Tasks
===========
- Administrava
- sorted out expenses for Connect
- organising travel/accommodation for KVM Forum 2018
Completed Reviews [1/1]
=======================
{PATCH v3 0/3} softfloat tests based on berkeley's testfloat
Message-Id: <20180913213910.28189-1-cota(a)braap.org>
- CLOSING NOTE [2018-09-28 Fri 19:40]
I'm happy with this
Absences
========
- KVM Forum 2018 (24th-26th October 2018)
Current Review Queue
====================
* {Qemu-devel} {RFC PATCH 00/13} target/arm: Derive cpu id regs from features
Message-Id: <20180915161738.25257-1-richard.henderson(a)linaro.org>
* {PATCH 00/20} target/arm: sve system mode patches
Message-Id: <20180809042206.15726-1-richard.henderson(a)linaro.org>
* {RFC PATCH 00/12} tests/tcg: Add TriCore tests
Message-Id: <20180501142222.19154-1-kbastian(a)mail.uni-paderborn.de>
* {RFC PATCH v2 00/23} KVM: arm64: Initial support for SVE guests
Message-Id: <1538141967-15375-1-git-send-email-Dave.Martin(a)arm.com>
* {PATCH 00/35} exec: drop BQL from interrupt handling
Message-Id: <20180917163103.6113-1-cota(a)braap.org>
* {PATCH v3 00/13} i386 + x86_64 mttcg
Message-Id: <20180911202823.21657-1-cota(a)braap.org>
--
Alex Bennée
[Connect]
Wrote up Connect Report with notes of presentations and hack-rooms,
for better or worse we have 20 pages of notes.
Wrote up Jira discussion
[TCWG-1468]
Made an example of how to use cmake, clang, newlib and a gcc-embedded
toolchain to build an example and run it on qemu.
[TCWG-1473] Linux kernel big-endian builds
Nearly have a fix that I'm happy with ready to submit.
[TCWG-1471] Fix the Armv6 Linux kernel build
Committed upstream today.
=== Work done during these past 3 weeks ===
* DSGHACK-25 (Support arithmetic on FileCheck regex variable):
+ all my tests pass, started to implement further minor changes to the syntax
* PR87374: external review
+ investigate bug, write patch, test it and send for external review
* GCC PR85434 / CVE-2018-12886: rework needed
+ Approved upstream but found when doing last minute testing after rebase
+ Testing on a wide number of targets a patch to register allocator
to properly ignore some operand when told to
* Linaro Connect Vancouver 2018
+ prepare talk, attend event and write up reports
* Regression testing of LLVM release:
+ extend script to do a LLVM release to be able to build from an
arbitrary branch
+ make weekly regression build from trunk
+ fix here-doc in regression job to test release when scripts it use change
Misc:
+ bits of line management
+ catching up on emails
=== Plan for week 40 ===
* GCC PR85434 / CVE-2018-12886:
+ finish testing, and get both register allocator fix and stack
protector fix committed
* PR87374: external review
+ add documentation and send back for external review
* DSGHACK-25 (Support arithmetic on FileCheck regex variable):
+ finish change to suport last syntax changes
+ extend testcase coverage (add tests for latest syntax change and
add more negative testing)
+ start cleaning up the code
* Try to reproduce perf issue mentioned in week #30's weekly report on
latest perf
* Line management
Progress:
* Post-travel/holiday catchup (email, expenses claims, code review,
team meetings etc)
(this was the lion's share of the time)
* VIRT-65 [QEMU upstream maintainership]
- some patches to fix clang warnings about taking the
address of a field in a packed struct
- make the compatibility "virt-2.10" machine really behave like the 2.10
QEMU's virt board: don't generate external aborts for accesses to bad
physical addresses. (It turns out a few misconfigured Linux
kernels do this.)
- noticed that we only have another 40 or so devices to convert
to be able to complete an API transition (sysbus init methods):
wrote this up for the list to nudge people into doing some conversions
thanks
-- PMM
Progress:
This week was Linaro Connect (Vancouver). Recordings are
online for most sessions I think; some may still be in the
process of being uploaded. For other presentations see:
https://connect.linaro.org/resources/yvr18/
Interesting presentations:
* "My other Machine is Virtual"
-- Alex's talk summarising QEMU's current tracing/debug facilities:
https://connect.linaro.org/resources/yvr18/yvr18-118/
* "SBSA QEMU"
-- Summary of work on an "enterprise" model in QEMU intended for use
as a development platform for firmware and other lower-level code.
https://connect.linaro.org/resources/yvr18/yvr18-511/
* "How to build a C++ processing tool using the clang libraries"
-- Peter Smith doing a fast pass through the clang library APIs
you can use for refactoring-type tools that operate on C++ source.
Watch the talk to figure out if this is something you want to
do at all; read the slides separately for the fine detail and
links to where to find more info, if the answer is "yes"...
https://connect.linaro.org/resources/yvr18/yvr18-223/
* "Diary of a drive-by coder: tips and tricks for working with upstream"
-- James Bottomley talks about successes and failures in upstreaming
one-off patches if you're not a member of the community. I also
asked in the Q&A about what communities can do to make life
easier for such contributors (answer mostly revolved around
better and clearer communication about the chances of a change
being accepted)
https://connect.linaro.org/resources/yvr18/yvr18-503/
* "An open source developer and a lawyer walk into a bar..."
-- Jilayne Lovejoy's keynote
(Personal takeaway: try to reduce my use of "IANAL, but...".)
https://connect.linaro.org/resources/yvr18/yvr18-200k2/
* Fujitsu's keynote on their new A64FX CPU:
https://connect.linaro.org/resources/yvr18/yvr18-400k1/
* Arm Architecture Enhancements in 2018
Matt Gretton-Dann's presentation of ARM v8A 8.5 features.
I was particularly encouraged to see that Arm have been able
to make public the system register and ISA XML on the same day
they announce the new features publicly.
https://connect.linaro.org/resources/yvr18/yvr18-104/
Useful meetings:
* discussion with RTH about handling CPU ID register fields
vs internal QEMU "enable this feature" bits (we have a bit of
an ugly mix of specifying the same thing in both places, and
also overriding ID reg fields from feature bits in some cases;
we'd like to achieve a bit more consistency in what we do...)
* discussion with RTH/Alex on instrumentation plugin APIs. I hope
we're now more or less on the same page about the general principles.
* QEMU roadmap sync with Alex/RTH/Maxim:
- finish v8M work
- heterogenous CPU support (for Musca board emulation)
- finish SVE
- fill in other v8.x missing emulation support
- instrumentation work
Other:
* Greensocs have sent out some QEMU patches to do with
modelling clock trees, which also touch a bit on reset.
QEMU's modelling of reset at the moment is pretty terrible,
so I had a think about how we might manage to do it better.
(Notably we currently only model power-on reset, and we don't
have a good answer for "device A in reset wants to assert a
signal that connects to device B, but there's no guarantee
about what order A and B will reset in". Does anybody know of
any good existing treatments of modelling device reset ?)
thanks
-- PMM
