SVE Support ([VIRT-198])
========================
- wrote up [post on SVE development] with QEMU for for Linaro Blog
- originally planned to publish on QEMU 3.0 release
- HPC team would like it published before their workshop on 26th
July
- write up a abstract for HPC workshop and plan remote time :todo
[VIRT-198] https://projects.linaro.org/browse/VIRT-198
[post on SVE development]
https://docs.google.com/document/d/15v1asqk-6de2RtA7ZWdIQ29PkY92gl3nlwG7_Se…
RISU Support for SVE ([VIRT-199])
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-07-06 Fri 12:37]
Changes merged upstream. Ticket closed.
- generated more traces at different VQ's
- VQ3 (found one error, actually x86 SIGFPE issue)
- VQ16 (found 2 errors in ptrue)
- initial run included errors in whilelo, whilels, wrffr, zip[12]
which went away
- I've parked the tests from ASL work pending legal feedback
[VIRT-199] https://projects.linaro.org/browse/VIRT-199
SVE Reviews
~~~~~~~~~~~
- started reviewing {RFC PATCH 00/16} KVM: arm64: Initial support for
SVE guests Message-Id:
<1529593060-542-1-git-send-email-Dave.Martin(a)arm.com>
QEMU ARMv8.3 Support ([VIRT-241])
=================================
- added remaining v8.1 stories to JIRA and re-organised under
- [ARMv8.1 Mandatory Features] and [ARMv8.1 optional features]
- pondering how much effort to do VHE
- it's mostly conditional re-direction of EL1/EL2 registers so
host kernel can pretend it's in EL1 when really in EL2
- some EL2 registers present slightly different formats when VHE
bit is set
[VIRT-241] https://projects.linaro.org/browse/VIRT-241
[ARMv8.1 Mandatory Features]
https://projects.linaro.org/browse/TCWG-1434
[ARMv8.1 optional features] https://projects.linaro.org/browse/TCWG-1435
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v3 00/20} Travis, Code Coverage and Cross Build
updates Message-Id: <20180702143021.18864-1-alex.bennee(a)linaro.org>
- posted {PULL 00/20} Travis, Code Coverage and Cross Build updates
Message-Id: <20180703101444.23778-12-alex.bennee(a)linaro.org>
- with a follow-up of {PULL v2 00/20} Travis, Code Coverage and
Cross Build updates Message-Id:
<20180704090642.3469-1-alex.bennee(a)linaro.org>
- and {PULL v3 00/20} Travis, Code Coverage and Cross Build updates
Message-Id: <20180705160329.30386-1-alex.bennee(a)linaro.org>
- now merged \o/
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Testing and CI
==============
- spoke with LAVA team about build status and build button
- now have a qa-reports account to submit LAVA jobs via
QEMU CI Loop ([VIRT-187])
~~~~~~~~~~~~~~~~~~~~~~~~~
- investigating porting existing RISU tests via qa-reports
- add additional test patterns :todo
[VIRT-187] https://projects.linaro.org/browse/VIRT-187
KVM CI Loop ([VIRT-2])
~~~~~~~~~~~~~~~~~~~~~~
- need to sync-up on the current state of this work :todo
- started looking at Xiang's latest auto setup scripts
[VIRT-2] https://projects.linaro.org/browse/VIRT-2
[our wiki] https://wiki.linaro.org/Core/Virtualization
MTTCG tests ([VIRT-52])
~~~~~~~~~~~~~~~~~~~~~~~
- need to dust these off and get up-streamed if I'm going to add new
tests :todo
[VIRT-52] https://projects.linaro.org/browse/VIRT-52
Other Tasks
===========
- Spoke to Ilias Apalodimas (LEDGE SIG) about VM networking
- options for zero copy guest to guest networking
- experiments with userspace networking stacks
- lightweight VM+containers
- [Kata Containers] - follow on from Clear Containers work
- Crostini/[CrosVM] work, ChromeOS VM+Docker approach
- Create an Instrumentation EPIC :todo
[Kata Containers] https://katacontainers.io/
[CrosVM] https://chromium.googlesource.com/chromiumos/platform/crosvm/
Completed Reviews [5/5]
=======================
{PATCH v2 00/13} iommu: support txattrs, support TCG execution, implement TZ MPC
Message-Id: <20180604152941.20374-10-peter.maydell(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-14 Thu 19:27]
Looks good.
{PATCH 0/8} Docker improvements
Message-Id: <20180628164643.9668-1-f4bug(a)amsat.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:38]
Grabbed some patches, commented on others
{Qemu-arm} {PATCH v6 00/35} target/arm SVE patches
Message-Id: <20180627043328.11531-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:39]
Looks good
{Qemu-devel} {PATCH v5 00/35} target/arm SVE patches
Message-Id: <20180621015359.12018-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:39]
Looking good, stopped to move to v6
{PATCH 0/4} KVM: arm64: FPSIMD/SVE fixes for 4.17
Message-Id: <1528976039-25826-1-git-send-email-Dave.Martin(a)arm.com>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:40]
Seems sane to me.
Absences
========
- YVR18 Connect (17th-21st September 2018)
- KVM Forum 2018 (24th-26th October 2018)
Current Review Queue
====================
* {RFC PATCH 00/16} KVM: arm64: Initial support for SVE guests
Message-Id: <1529593060-542-1-git-send-email-Dave.Martin(a)arm.com>
* {Qemu-devel} {RFC v2 0/2} Add BPF suuport to Qemu
Message-Id: <20180625110706.23332-1-sameeh(a)daynix.com>
* {PATCH v4 00/19} reverse debugging
Message-Id: <20180528071332.9424.27343.stgit@pasha-VirtualBox>
* {RFC PATCH 00/12} tests/tcg: Add TriCore tests
Message-Id: <20180501142222.19154-1-kbastian(a)mail.uni-paderborn.de>
* {PATCH 0/4} tests/vm: various trivial fixes
Message-Id: <20180628153535.1411-1-f4bug(a)amsat.org>
* {PATCH 0/6} docker: Port to Python 3
Message-Id: <20180627021423.18404-1-ehabkost(a)redhat.com>
--
Alex Bennée
== Progress ==
* FDPIC
- GCC patch series: updating patches.
- uclibc-ng: discussing problem with lib symbols not being weak.
It's not a blocker for FDPIC anyway. Continued to update/clean the
patch series before submission.
* GCC upstream validation:
- looking at some random noise in testing
- reported a couple of regressions
* Infrastructure:
- patch reviews
- cleanup/improvements
* misc (conf-calls, meetings, emails, ....)
== Next ==
* FDPIC: uclibc-ng, GCC
* GCC upstream validation
o One day off
o LLVM bots
* Troubleshot sanitizers regressions on ARM
o LLVM Machine Outliner on ARM
* Rebased prototype on upstream developments
* Reviewing upstream patch on intra-procedure-call
scratch register handling.
* Investigating potential issues w/r to pass ordering
o Misc
* Various meetings and discussions.
[VIRT-198 # QEMU: SVE Emulation Support ]
Full aarch64-linux-user patch set merged.
[VIRT-214 # SVE System Registers ]
Implemented ID_AA64PFR0_EL1, ID_AA64ZFR0_EL1.
[VIRT-249 # SVE System Mode ]
Fixed sve disabled exception routing.
A booted kernel recognizes sve is present, according to /proc/cpuinfo.
However, the kernel crashes as soon as the first sve insn is executed.
Task for next week is to find out why.
r~
SVE Support ([VIRT-198])
========================
- posted {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.bennee(a)linaro.org>
- needed for the HPC guys in their test setups
- pm has grabbed the CNT patches, the rest need rework, not this
cycle
[VIRT-198] https://projects.linaro.org/browse/VIRT-198
RISU Support for SVE ([VIRT-199])
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- posted {RISU PATCH v4 00/22} ARM SVE support for RISU Message-Id:
<20180622141205.16306-1-alex.bennee(a)linaro.org>
- support load/store memory instructions from ASL :todo
- awaiting legal clearance from ARM to publish script
- generated more traces at different VQ's
- VQ3 (found one error, actually x86 SIGFPE issue)
- VQ16 (still generating :-/)
[VIRT-199] https://projects.linaro.org/browse/VIRT-199
[iteration of SVE series]
https://github.com/stsquad/risu/tree/add-sve-support-v3
SVE Reviews
~~~~~~~~~~~
- reviewed {Qemu-devel} {PATCH v5 00/35} target/arm SVE patches
Message-Id: <20180621015359.12018-1-richard.henderson(a)linaro.org>
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v1 00/10} Travis updates and code coverage tweaks
Message-Id: <20180625111935.26108-1-alex.bennee(a)linaro.org>
- spent some time looking at getting xtensa system test stuff done
- posted {PATCH v2 00/21} Travis, Code Coverage and Cross Build
updates Message-Id: <20180629205232.27190-1-alex.bennee(a)linaro.org>
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[hacky fix]
https://github.com/stsquad/qemu/commit/a15577f8a6629f9924d2671a82f0b9801351…
KVM CI Loop ([VIRT-2])
======================
- need to sync-up on the current state of this work :todo
- spoke with LAVA team about build status and build button
- now have a qa-reports account to submit LAVA jobs via
[VIRT-2] https://projects.linaro.org/browse/VIRT-2
[our wiki] https://wiki.linaro.org/Core/Virtualization
Other Tasks
===========
[arm64 story a bit more desktopy]
https://github.com/stsquad/gentoo/tree/arm-keywords-so-far
Completed Reviews [1/1]
=======================
{PATCH v2 00/13} iommu: support txattrs, support TCG execution, implement TZ MPC
Message-Id: <20180604152941.20374-10-peter.maydell(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-14 Thu 19:27]
Looks good.
{PATCH 0/8} Docker improvements
Message-Id: <20180628164643.9668-1-f4bug(a)amsat.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:38]
Grabbed some patches, commented on others
{Qemu-arm} {PATCH v6 00/35} target/arm SVE patches
Message-Id: <20180627043328.11531-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:39]
Looks good
{Qemu-devel} {PATCH v5 00/35} target/arm SVE patches
Message-Id: <20180621015359.12018-1-richard.henderson(a)linaro.org>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:39]
Looking good, stopped to move to v6
{PATCH 0/4} KVM: arm64: FPSIMD/SVE fixes for 4.17
Message-Id: <1528976039-25826-1-git-send-email-Dave.Martin(a)arm.com>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- CLOSING NOTE [2018-06-29 Fri 21:40]
Seems sane to me.
Absences
========
- YVR18 Connect (17th-21st September 2018)
- KVM Forum 2018 (24th-26th October 2018)
Current Review Queue
====================
* {PATCH v4 00/19} reverse debugging
Message-Id: <20180528071332.9424.27343.stgit@pasha-VirtualBox>
* {RFC PATCH 00/12} tests/tcg: Add TriCore tests
Message-Id: <20180501142222.19154-1-kbastian(a)mail.uni-paderborn.de>
* {PATCH 0/4} tests/vm: various trivial fixes
Message-Id: <20180628153535.1411-1-f4bug(a)amsat.org>
* {PATCH 0/6} docker: Port to Python 3
Message-Id: <20180627021423.18404-1-ehabkost(a)redhat.com>
* {PATCH v4 00/14} fp-test + hardfloat
Message-Id: <1528768140-17894-1-git-send-email-cota(a)braap.org>
* {RFC PATCH 00/16} KVM: arm64: Initial support for SVE guests
Message-Id: <1529593060-542-1-git-send-email-Dave.Martin(a)arm.com>
--
Alex Bennée
[TCWG-1424] Investigation into profile and size optimisations
- Completed the pass and got it working on both the old and new pass managers
- Spent quite a bit of time trying to understand how llvm classifies
hot and cold functions, a lot of the details are not documented well
or at all.
- Found another problem with --pgo and lnt when the exec-multisample
option is used. I've applied a local fix to stop the extra runs from
triggering profile collection
- Upstream lnt doesn't seem to collect code size information for a
benchmarks-only run, wrote a script to measure and inject it back.
- Got some benchmark figures on the pass. Difficult to interpret as I
suspect that too many of the benchmarks are too small to give useful
results. There seemed to be some huge regressions when a critical
function stopped getting inlined, but overall performance was
comparable. I need to find some better benchmarks and learn how to
make sense of results.
[TCWG-1368] Buildbot failure investigation
Decided to take a look as an exercise in using the packet.net machines.
Some libfuzzer tests are hanging or taking an extremely long time to
run on aarch64. Reproduced on one of TCWGs packet.net machines. At
early stage of investigation right now as there doesn't seem to be any
obvious answers or easily available diagnostics.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ code review in preparation for 3.0 softfreeze next week:
- PMU emulation improvements
- last round of SVE patches
- i.mx minor code cleanups
- put 'address' annotations into DTB node names
- virtualization extension support in GICv2 emulation
+ sent two target-arm pull requests
+ bug investigation: the small-MPU-regions patchset had a bug which
broke an m68k test image
+ handling lots of pull requests from everybody else
thanks
-- PMM
=== Work done during this 2.5day week ===
* 2.5 day off to take care of my sick son
* stack-protector failure on GCC ARM: more testing needed
+ submitted CVE ID request -> will be known as CVE-2018-12886 once published
+ start testing
* Continue work on DSGHACK-25 (Support arithmetic on FileCheck regex variable)
* Misc improvement to Linaro TCWG infrastructure
=== Plan for week 27 ===
* finish testing of stack protector bug fix and submit patch for review
* DSGHACK-25 (Support arithmetic on FileCheck regex variable): finish patch
o GNU releases
* 6.4 and 7.3 2018.05 deployed
o LLVM
* First prototype implemented for ARM mode
* Working on more cases to handle
* Investigating potential issues w/r to pass ordering
o Misc
* Various meetings and discussions.
[VIRT-198 # QEMU: SVE Emulation Support ]
Implemented FCADD, FCMLA, SDOT, UDOT.
Posted v5 patch set.
[VIRT-210 # SVE first-fault and no-fault loads ]
Implemented for user-only.
Posted an RFC for using a rwlock instead of a mutex to
protect from mmap changes. Emilio Cota wants perf numbers.
Rebased previous glibc sve string patches to align with
the cortex-strings work reviewed by Richard Sandiford.
Found that strrchr fails with glibc's testsuite even though
it didn't work cortex-strings' testsuite.
Found that it would *really* help to have a gdb that understands
the new sve registers, especially predicates. Found that some
sve support is now upstream in gdb. Added some support to the
qemu gdbstub, but so far it just crashes gdb.
[Upstream]
Patch review; the big tickets being SVE RISU and nanoMIPS.
r~
