# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [3/10]
Update patches to address review comments. Commit three patches.
Need to post V3.
* TCWG-561, Handle unavailable memory during frame unwinding. [2/10]
Think about the plan.
* Upstream patches review. [3/10]
** Review IBM kernel-awareness patches.
** Review sparc64 adi patch.
** Review Alan's patch on removing MAX_REGISTER_SIZE. Evaluate other
better but expensive approach.
* Misc, [2/10]
Write a STL container allocator which uses stack instead of heap.
Underestimate the complexity of C++. Need to replace some std::vector
with my vector with stack_allocator in GDB. It should be also useful
to Alan.
# Plan #
* TCWG-1159, send v3.
* TCWG-561, Handle unavailable memory during frame unwinding.
--
Yao Qi
[TCWG-614] Range extension thunks
- No progress on upstream reviews from maintainers this week
I have received some interest on IRC and on at least one of the
reviews from other people wanting the feature so I'm hoping that this
may speed up the process.
- I've committed to rebasing and posting the full patch-set for review
so that interested people can take it and test.
PR31159 Tracked down why LLD wasn't correctly linking ARM BSD port
- lld only provides a dummy absolute value for _GLOBAL_OFFSET_TABLE_
- llvm-mc doesn't transform .word _GLOBAL_OFFSET_TABLE_ - . into
R_ARM_BASE_PREL like GNU as does, this relocation doesn't use the
value of _GLOBAL_OFFSET_TABLE_ . Instead we get R_ARM_REL32 which
needs _GLOBAL_OFFSET_TABLE_ to be set correctly. PR335511
- Patch accepted upstream will commit today
Misc:
- lld consultancy for Android
- Help to fix build error on clang for ARM colleague
- Query on lld behaviour with respect to .ARM.extab, I think lld
behaviour is within spec, but it may be producing larger files so
probably enough to argue the case for a small patch.
-No time to spend on compiler-rt this week
Plans:
- Post all the range-thunk patches for the people interested in it.
- Commit patches accepted last week
== Progress ==
* Out of office on Friday [2/10]
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- Committed a quick fix and started seeing green builds on this, we
can probably move it upstream soon
* TCWG-836 - Replace D01s by Scaleway boards [2/10]
- Set up a selfhost buildbot on one of the Scaleway boards
- It is very, very slow, I did some performance experiments but
there's probably more that can be attempted here
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [2/10]
- The hard float part is implemented, fiddling with the soft float now
- Forked some of that work into a different story for supporting G_SELECT
* TCWG-1174 - [ARM GlobalISel] Support G_SELECT [1/10]
- In progress
* Misc [2/10]
- Mailing lists, code reviews
- TCWG-1136 - LLVM 4.0.1 - Spun up and uploaded the final release candidate
- TCWG-1177 - Investigate failure on clang-cmake-aarch64-lld -
Bisected and reverted a commit upstream
== Plan ==
* More GlobalISel
* More buildbots
* More code reviews
== Progress ==
o Linaro GCC/Validation (7/10)
* Prepared a fix for libgomp/mingw build issue. Submitted upstream
* Analysed ubuntu bug report on unsupported relocations:
- https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1695093
- Identified it as upstream PR 79041
- Fix submitted upstream
* Following upstream discussions on stack clash CVE
- Releases re-spins will done once the issue will be fixed upstream
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o CVE, on-going patches and infra
== Progress ==
* Infrastructure/validation:
- looking at bug #3040
* Benchmarking:
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported a few regressions
- sent a couple of patches (testsuite, ARM_FEATURE_COPROC)
* misc (conf-calls, meetings, emails, ....)
== Progress ==
o Linaro GCC/Validation (7/10)
* backports and branch merges for linaro branches 5, 6 and 7
* released GCC 6 and 7 2017.06 sources snapshots
* Fxed GCC 5 branch merge
* analyzed various infrastructure instabilities
* Mingw32 libgomp build issue due to configure issue, working on a fix
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o complete GCC 5 sources snapshot
o Fix libgomp problem and continue on re-association
== Progress ==
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [2/10]
- In progress
* TCWG-1168 - [ARM GlobalISel] Support G_ICMP [3/10]
- Done, going to commit upstream
* TCWG-1136 - LLVM 4.0.1 [1/10]
- Spinned up rc3
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [2/10]
- Investigated the timeouts in the test-suite and reported upstream
- Sent a patch to increase the threshold for those tests on AArch64,
waiting for feedback
* TCWG-1166 - Investigate Clang diag-flags.cpp failure [1/10]
- Bisected and reverted upstream
* Misc [1/10]
- Mailing lists, meetings etc
== Plan ==
* Wrap up TCWG-1168 and 1172
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [1/10]
Finish writing the commit log and changelog. Patches are posted.
* TCWG-1167, Test AArch32 GDB on AArch64 Linux kernel. [3/10]
Such configuration shows one regression. It is whether condition
checked failed UDF triggers Undefined Instruction Exception or not.
GDB's assumption is NO, but Peter M. told me that it is implementation
defined, so GDB has to handle both.
* gdb/objdump disassembler unification. Done. [1/10]
Commit the the left over patch.
* Pick up Alan H.'s C++ template patch, and post it again. Learned a
lot on C++ 11 default template parameter and SFINAE. Patch is
committed.
* Upstreams review. [3/10]
** Encourage people to build GDB with CLANG. Resist the objections
from other people, and write the "policy" about using other compilers
to build GDB.
** Review IBM's kernel-awareness v4 patches.
* Misc, [2/10].
# Plan #
Get chance to back to my interrupted works:
* TCWG-333, Fix gdb.base/func-ptrs.exp fails in thumb mode.
* TCWG-561, Handle unavailable memory during frame unwinding.
--
Yao Qi
== Progress ==
* Infrastructure/validation:
- still some random results, and still ssh connexion problems with
several machines
- improving abe-bisect script
* Benchmarking:
* GCC:
- 'deprecated IT-blocks' patch: looking at the generated code to
understand the regressions
* GCC upstream validation:
- reported a couple of regressions on trunk, a few bisects, helped
validating some ARM patches
- working on further reducing noise ("random" pass/failures)
- include qemu traces in the logs when a testcase aborts, to help debug
* misc (conf-calls, meetings, emails, ....)
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.06
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.1+svn249190 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.08 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.06/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.1+svn249190
* Backport of [Bugfix] [AArch32] PR target/71607 Fix ICE when loading constant
* Backport of [Bugfix] [AArch64] PR target/80671
config/aarch64/cortex-a57-fma-steering.c:416: bad statement order
* Backport of [Bugfix] PR tree-optimization/79697 unused realloc(0, n)
not eliminated
* Backport of [Bugfix] PR tree-optimization/80613 ICE in
is_gimple_reg_type with -O2
* Backport of [AArch32] Add a new target hook to compute the frame layout
* Backport of [AArch32] Add fuchsia support to libgcc
* Backport of [AArch32] FreeBSD arm libgcc config.host
* Backport of [AArch32] Model Cortex-A53 load forwarding
* Backport of [AArch64] Accept more addressing modes for PRFM
* Backport of [AArch64] Add aes and sha reservations for Thunderx2t99
* Backport of [AArch64] Add crc reservations for Thunderx2t99
* Backport of [AArch64] Improve float to int moves
* Backport of [AArch64] Set jump alignment to 4 for Cortex cores
* Backport of [AArch64] Tighten move constraints for symbolic operands
* Backport of [Misc] Check the alternate cost model just as costs_lt_p
* Backport of [Misc] Record equivalences for spill registers
* Backport of [Testsuite] [AArch32] Only test
tls-disable-literal-pool.c if target supports native TLS
* Backport of [Testsuite] [AArch32] Replace absolute line numbers in
gcc.target/arm
* Backport of [Testsuite] [AArch64] Replace absolute line numbers in
gcc.target/aarch64
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.3+svn249140 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the 2017.08 stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.06/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn249140
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
