- linaro-toolchain - lists.linaro.org

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review: - Managed to review all of RTH's 82-patch SVE2 patchset... + Misc bugs: - fixed some errors in modelling of SRAM in AN547 board - fixed a bug in GICv3 EOI (EL3 should be able to handle Group 1 NS IRQs) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Implemented multiply-add-long-dual-accumulate insns (VMLALDAV, VMLSLDAV, VRMLALDAVH, VRMLSLDAVH) Progress meter: 40/210 (19%) -- PMM

4 years, 4 months

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[ACTIVITY] week ending May. 16 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - did some investigation on getting [Gunyah hypervisor] up and running - debugging xl domU launch under QEMU - got reverse debugging working on virtio ;-) [STR-9] <https://projects.linaro.org/browse/STR-9> [Gunyah hypervisor] <https://github.com/quic/gunyah-hypervisor> QEMU Upstream Work ([UM-2]) =========================== - reviewed a large chunk of rth's FloatParts opus Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org> - posted [PATCH v3 00/31] testing/next pre-PR (hexagon, tricore, misc) Message-Id: <20210512102051.12134-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Other ===== [Linaro JIRA Issues] Updates for LBO-99: QEMU's usage in Linaro Message-Id: <01000178a38e5f60-4b7149b0-b71b-4952-869f-cabdfb9078a6-000000(a)email.amazonses.com> Completed Reviews [1/1] ======================= [PATCH 00/72] Convert floatx80 and float128 to FloatParts Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org> Absences ======== - Bank Holiday on Monday Current Review Queue ==================== TODO [PATCH v3 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210429234201.125565-1-shashi.mallela(a)linaro.org> =========================================================================================================================== TODO [PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS Message-Id: <20210505030443.25310-1-rebecca(a)nuviainc.com> ==================================================================================================================================== TODO [PATCH v6 00/82] target/arm: Implement SVE2 Message-Id: <20210430202610.1136687-1-richard.henderson(a)linaro.org> =================================================================================================================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== -- Alex Bennée

4 years, 4 months

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Bootstrap-O3 broken on 32-bit ARM

by Maxim Kuvyrkov

Hi Richard, Your patch a076632e274abe344ca7648b7c7f299273d4cbe0 appears to have broken bootstrap-O3 for 32-bit armhf. Do you have an AArch32-capable machine to reproduce/investigate this on? Let me know if not, and I'll make a proper bug report with a testcase. ICE: 00:33:32 In function ‘syscall.forkExec’: 00:33:32 go1: error: address taken, but ADDRESSABLE bit not set 00:33:32 PHI argument 00:33:32 &go..C479; 00:33:32 for PHI node 00:33:32 err$__object_78 = PHI <err$__object_76(58), &go..C479(59)> 00:33:32 during GIMPLE pass: fre 00:33:32 go1: internal compiler error: verify_ssa failed 00:33:32 0x9c18d7 verify_ssa(bool, bool) 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/tree-ssa.c:1214 00:33:32 0x6f8d5b execute_function_todo 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2049 00:33:32 0x6f9abf do_per_function 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:1687 00:33:32 0x6f9abf execute_todo 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2096 00:33:32 Please submit a full bug report, 00:33:32 with preprocessed source if appropriate. 00:33:32 Please include the complete backtrace with any bug report. 00:33:32 See <https://gcc.gnu.org/bugs/> for instructions. 00:33:32 Makefile:3001: recipe for target 'syscall.lo' failed Full build log: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… Regards, -- Maxim Kuvyrkov https://www.linaro.org > On May 11, 2021, at 8:15 AM, tcwg-jira (Jira) <projects(a)linaro.org> wrote: > > There is 1 comment. > > > GNU Toolchain / <Mail Attachment.png> GNU-692 IN PROGRESS > Regressions from tcwg_binutils/tcwg_cross/tcwg_gnu CI > > View issue · Add comment > > 1 comment > > tcwg-jira on 11/May/21 5:04 AM > > Successfully identified regression in gcc in CI configuration tcwg_gnu/gnu-master-arm-bootstrap_O3. So far, this commit has regressed CI configurations: > • tcwg_gnu/gnu-master-arm-bootstrap_O3 > Culprit: > <cut> > commit a076632e274abe344ca7648b7c7f299273d4cbe0 > Author: Richard Biener <rguenther(a)suse.de> > Date: Fri May 7 09:51:18 2021 +0200 > middle-end/100464 - avoid spurious TREE_ADDRESSABLE in folding debug stmts > canonicalize_constructor_val was setting TREE_ADDRESSABLE on bases > of ADDR_EXPRs but that's futile when we're dealing with CTOR values > in debug stmts. This rips out the code which was added for Java > and should have been an assertion when we didn't have debug stmts. > To not regress g++.dg/tree-ssa/array-temp1.C we have to adjust the > testcase to not look for a no longer applied invalid optimization. > 2021-05-10 Richard Biener <rguenther(a)suse.de> > PR middle-end/100464 > PR c++/100468 > gcc/ > • gimple-fold.c (canonicalize_constructor_val): Do not set > TREE_ADDRESSABLE. > gcc/cp/ > • call.c (set_up_extended_ref_temp): Mark the temporary > addressable if the TARGET_EXPR was. > gcc/testsuite/ > • gcc.dg/pr100464.c: New testcase. > • g++.dg/tree-ssa/array-temp1.C: Adjust. > </cut> > Details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… > Even more details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… > > > This message was sent by Atlassian Jira (v8.11.1#811002-sha1:94cd716) > Jira is improving email notifications, share your feedback! > Get Jira notifications on your phone! Download the Jira Server app for Android or iOS.

4 years, 4 months

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[ACTIVITY] 3 - 7 May 2021

by Prathamesh Kulkarni

== This Week == * GCC - PR97903 (missed lowering to vtst): Committed fix to trunk, - PR66791: Submitted patch to replace vtst* (a, b) by (a & b) != 0 in arm_neon.h. - Committed fix for build failure in trunk. * Validation - vect metric: Pushed all pending patches. == Next Week == - PR66791: Continue working on more intrinsics - Validation: Monitor vect metric

4 years, 4 months

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[ACTIVITY] 3-7 May 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions - discussing update of the list of configs - tried qemu-6.0, issue with hwasan testing on aarch64 * GCC - MVE/vectorization: waiting for feedback on patches for vcmp, vld2/vst2, vld4/st4 * Misc - scripts patch reviews - looking at gdb issue with register names in target description == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 4 months

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[ACTIVITY] week ending May. 9 2021

by Alex Bennée

QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v2 00/30] testing/next (hexagon, tricore, ppc, signals, cirrus) Message-Id: <20210504100223.25427-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/7] plugins/next (windows, leaks, tcg tracing) Message-Id: <20210505092259.8202-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> [Linaro JIRA Issues] Updates for LBO-99: QEMU's usage in Linaro Message-Id: <01000178a38e5f60-4b7149b0-b71b-4952-869f-cabdfb9078a6-000000(a)email.amazonses.com> ============================================================================================================================================================= Completed Reviews [3/3] ======================= [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> [PATCH 0/5] misc: Replace alloca() by g_malloc() Message-Id: <20210505170055.1415360-6-philmd(a)redhat.com> [PATCH v2 0/9] misc: Replace alloca() by g_malloc() Message-Id: <CANCZdfqiHxQoG+g3bq_KL01yWCHUbF5qxJWN=sD37h7UJFMZ7g(a)mail.gmail.com> Absences ======== - Bank Holiday on Monday Current Review Queue ==================== TODO [PATCH v6 00/82] target/arm: Implement SVE2 Message-Id: <20210430202610.1136687-1-richard.henderson(a)linaro.org> =================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== -- Alex Bennée

4 years, 4 months

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[ACTIVITY] report week ending 6 May

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] - sent some small patches: fixing Coverity issues; converting a few users of a legacy API to the new function * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - Implemented more insns: VMUL, VSTRB/H/W, VMAX, VMIN, VABD, VHADD, VHSUB, VMULL, VRMULH. Progress meter: 36/210 (17%) -- PMM

4 years, 4 months

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Flakey LLVM buildbot builds on clang-cmake-armv7-quick

by Christian Kühnel

Hi folks, I just noticed that your builds on clang-cmake-armv7-quick seem to be flakey from time to time: https://lab.llvm.org/buildbot/#/builders/107/builds/7394 https://lab.llvm.org/buildbot/#/builders/107/builds/7390 https://lab.llvm.org/buildbot/#/builders/107/builds/7369 https://lab.llvm.org/buildbot/#/builders/107/builds/7359 I just got hit by one of the flakes with a documentation-only change. I looks like the build is timing out... Best, Christian

4 years, 4 months

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[ACTIVITY] week ending 2 May 2021

by Richard Henderson

[um-2] Patch review: power10, arm. Fixes for Alex's new signals.c test: sparc, s390. [qemu-349] Refreshed sve2 patch set. r~

4 years, 4 months

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[ACTIVITY] week ending May. 2 2021

by Alex Bennée

QEMU Device and Machine Models ([QEMU-418]) =========================================== - posted [kvm-unit-tests PATCH v1 0/4] enable LPI and ITS for TCG Message-Id: <20210428101844.22656-1-alex.bennee(a)linaro.org> [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - updated [testing/next branch] we some more fixes [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Other ===== - Spent more time on blog post for [LBO-99] [LBO-99] <https://projects.linaro.org/browse/LBO-99> Completed Reviews [3/3] ======================= [PATCH v3 0/2] tests/docker: tests/tcg/ppc64le: Newer toolchain to build tests for PowerISA v3.1 instructions Message-Id: <20210423205757.1752480-1-matheus.ferst(a)eldorado.org.br> [PATCH 0/2] plugins: Freeing allocated values in hash tables. Message-Id: <20210421140934.7561-1-ma.mandourr(a)gmail.com> [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210401024152.203896-1-shashi.mallela(a)linaro.org> Absences ======== - Bank Holiday on Monday Current Review Queue ==================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== TODO [RFC v14 00/80] arm cleanup experiment for kvm-only build Message-Id: <20210416162824.25131-1-cfontana(a)suse.de> =================================================================================================================== -- Alex Bennée

4 years, 4 months

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[ACTIVITY] report week ending 30 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - release work: rc5 Monday, and then 6.0 final release on Thursday. - sent a pullreq with some accumulated arm patches now 6.1 is open - fixed a trivial bug where WFI in the usermode emulator crashed * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - Implemented more instructions: logic ops, VCLS, VCLZ, VREV, VMVN, VABS, VNEG, VADD, VDUP, VSUB, VMULH, and widening VLDR. (These are all simple "always call an out-of-line helper" versions. We'll want an optimised "we know we have no predication" version for many of them, but I plan to do that afterwards.) - Worked through the v8M Arm ARM identifying which insns we must implement. There are 210 insn patterns in total, of which I have currently implemented 23, so we can produce a rough-and-ready progress meter: 23/210 (11%) (There is of course work to do beyond just the insns, but they form the bulk of it, so the meter has some utility.) -- PMM

4 years, 4 months

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[ACTIVITY] 26-30 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions * GCC - committed cleanup patches - sent a few testsuite improvement patches - MVE/vectorization: Send patches for vcmp, vld2/vst2, vld4/st4 * Misc - scripts patch reviews == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 4 months

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[ACTIVITY] week ending Apr. 25 2021

by Alex Bennée

QEMU Support for Xen ([STR-20]) =============================== - continued reviewing [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> - this is looking pretty solid now - cut new version of [arm build clean-ups based on Claudio's series] - testing reveals some breakage to track down next week [STR-20] <https://projects.linaro.org/browse/STR-20> [arm build clean-ups based on Claudio's series] <https://github.com/stsquad/qemu/tree/xen/arm-build-cleanups-v3> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/11] rc2 fixes (check-tcg, gitlab, gdbstub) Message-Id: <20210406150041.28753-1-alex.bennee(a)linaro.org> - some time trying to debug last weeks PR, eventually merged - posted [PATCH for post 6.0 v1 00/25] testing/next (hexagon/tricore/test cc) Message-Id: <20210419145435.14083-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/tcg: add a multiarch signals test to stress test signal delivery Message-Id: <20210421132931.11127-1-alex.bennee(a)linaro.org> - hunting for RC failure in s390x - posted [PATCH] target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability Message-Id: <20210422154427.13038-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> GSoC/Intern Mentoring ===================== GSoC 2021 proposal initiation for AGL Message-Id: <CAC+yH-Z_KZKuQ0nmAgk-+B+HW88sNjztObtWwazof+cAGJGuuQ(a)mail.gmail.com> GSoC: cache modelling plugin inquiry Message-Id: <CAD-LL6hLk1XAB5VWwHgMOWQV=bT1+FCnf8f-q9MVw5e5A4RMqg(a)mail.gmail.com> GSoC - QEMU Ideas Message-Id: <CALpwMJz0kb2BDreTWBbt945FR+sLX=sKzHSv8pMb5LkLwXqEJA(a)mail.gmail.com> Synced up with potential AGL Jailhouse/VirtIO GSoC applicant Other ===== - bit more write-up of blog post for [LBO-99] [LBO-99] <https://projects.linaro.org/browse/LBO-99> Completed Reviews [8/8] ======================= [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document Message-Id: <72bc8020-2028-82db-219c-a6ae311e26df(a)redhat.com> [PATCH v4 00/12] target/arm mte fixes Message-Id: <20210406174031.64299-4-richard.henderson(a)linaro.org> [PATCH 0/4] Acceptance Tests: update assets location and cancel tests if missing Message-Id: <20200907042000.415931-1-crosa(a)redhat.com> Added: <2020-09-07 Mon> [RFC PATCH 0/3] tests/tcg/ppc64le: paddi tests Message-Id: <20210415214138.563795-1-matheus.ferst(a)eldorado.org.br> [RFC PATCH 00/15] gitlab-ci: Allow forks to use different pipelines than mainstream Message-Id: <20210418233448.1267991-11-f4bug(a)amsat.org> [PATCH 0/2] gdbstub: implement support for blocking interrupts on single stepping Message-Id: <20210401144152.1031282-1-mlevitsk(a)redhat.com> [PATCH v2 0/7] linux-user: sigaction fixes/cleanups Message-Id: <20210422230227.314751-1-richard.henderson(a)linaro.org> testing/next - hexagon toolchain update Message-Id: <BN7PR02MB4194DF5752EF3BADE858018DB8799(a)BN7PR02MB4194.namprd02.prod.outlook.com> [PATCH] tests/tcg: Run tests on arch variants again Message-Id: <20210312152105.1836543-1-f4bug(a)amsat.org> [PATCH 0/1] libbpf dependecy for docker containers. Message-Id: <20210406082947.672708-1-andrew(a)daynix.com> [PATCH v3 00/15] tests/tcg: Add TriCore tests Message-Id: <20210305170045.869437-1-kbastian(a)mail.uni-paderborn.de> Absences ======== Current Review Queue ==================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== TODO [RFC v14 00/80] arm cleanup experiment for kvm-only build Message-Id: <20210416162824.25131-1-cfontana(a)suse.de> =================================================================================================================== TODO [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210401024152.203896-1-shashi.mallela(a)linaro.org> =========================================================================================================================== -- Alex Bennée

4 years, 4 months

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[ACTIVITY] report week ending 23 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - code review: + Shashi's ITS emulation patchset + RTH's remaining fixes for MTE + RTH's patchset to implement alignment checking - release work: sadly we found a pretty nasty crasher bug at the last minute, so we'll release rc5 on Monday and final release Thursday (with luck) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - useful discussions with RTH about how to implement MVE and in particular how to handle its various flavours of insn predication - some progress in writing code to implement the first insn (VLDR) thanks -- PMM

4 years, 4 months

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[ACTIVITY] 19-23 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions * GCC - committed further fix for testcase for PR96770 - sent a few testsuite improvement patches - resumed work on MVE/auto-vectorization. Added support for vcmp.f16. Checking fp16 support in previous patches. * Misc - scripts patch reviews == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 4 months

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[ACTIVITY] 12-16 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions - Reduced build frequency on release branches, now same as trunk: daily bump and arm/aarch64 "interesting" commits * GCC - pinged further fix for testcase for PR96770 - preparing cortex-m55 validation setup - looking at cmse tests vs qemu - Linaro BZ 5755/upstream 100049 * GDB - uploaded cleaned up last known-to-work branch to sourceware so that maintainers can have a look at it - uploaded latest wip based on 8.2 branch too * Misc - scripts patch reviews == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 5 months

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[ACTIVITY] report week ending Apr 16

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Finished and posted patches implementing remap support for AN524 - Release work for rc3 - Sent a set of refactoring patches that split out some files we were previously #including into translate.c so they are separate compilation units. - Thought a bit more about reset handling (in the course of writing the AN524 remap patches I again ran into some of the deficiencies of our current reset implementation; I really must take some time this release cycle to try to improve things here...) - Fixed bug where our AN547 board model accidentally disabled the FPU on the Cortex-M55... - ...and one where we were accidentally giving it an M33 rather than an M55 ! - Respun and extended some patches from Paolo which fix our use of QEMU and system headers in the 2 C++ files in the codebase (which were broken by a change in new versions of glib) - started looking at some of the for-6.1 patch review queue, which I had been postponing in favour of for-6.0 stuff * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - re-read the MVE portions of the v8M Arm ARM, sketched out a plan of where to start with the QEMU implementation thanks -- PMM

4 years, 5 months

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qemu bfloat16 branch

by Richard Henderson

https://gitlab.com/rth7680/qemu/-/commits/tgt-arm-bf16 It isn't a large extension, so all done. I added aarch64 simd, aarch32 neon, and sve support all at once. I've tested it via risu vs FVP. I've based this on my SVE2 branch, since there are some cleanups that made that easier. I'll post patches to qemu-devel next week. r~

4 years, 5 months

2
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[ACTIVITY] 5-9 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - No regression to report this week. Issues on gcc-9 and gcc-10 release branches had already been reported by other people. * GCC - pinged further fix for testcase for PR96770 - Looking at failures for cortex-M, only found testisms so far * Misc - Fixed benchmarking jobs on stm32 == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 5 months

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[ACTIVITY] week ending 11 Apr 2021

by Richard Henderson

[UM-2] * Patch review. Lots. [QEMU-389 # Bfloat16 ] * Implemented. Will post patches next week. r~

4 years, 5 months

1
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[ACTIVITY] week ending Apr. 11 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - had sync-up with Akashi-san/Vincent about approaches for the Zephyr demo - need to write-up on Monday [STR-9] <https://projects.linaro.org/browse/STR-9> QEMU Support for Xen ([STR-20]) =============================== - continued reviewing [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> - this is looking pretty solid now - cut new version of [arm build clean-ups based on Claudio's series] - testing reveals some breakage to track down next week [STR-20] <https://projects.linaro.org/browse/STR-20> [arm build clean-ups based on Claudio's series] <https://github.com/stsquad/qemu/tree/xen/arm-build-cleanups-v3> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/11] rc2 fixes (check-tcg, gitlab, gdbstub) Message-Id: <20210406150041.28753-1-alex.bennee(a)linaro.org> - some time trying to debug last weeks PR, eventually merged [UM-2] <https://projects.linaro.org/browse/UM-2> GSoC/Intern Mentoring ===================== GSoC 2021 proposal initiation for AGL Message-Id: <CAC+yH-Z_KZKuQ0nmAgk-+B+HW88sNjztObtWwazof+cAGJGuuQ(a)mail.gmail.com> GSoC: cache modelling plugin inquiry Message-Id: <CAD-LL6hLk1XAB5VWwHgMOWQV=bT1+FCnf8f-q9MVw5e5A4RMqg(a)mail.gmail.com> GSoC - QEMU Ideas Message-Id: <CALpwMJz0kb2BDreTWBbt945FR+sLX=sKzHSv8pMb5LkLwXqEJA(a)mail.gmail.com> Synced up with potential AGL Jailhouse/VirtIO GSoC applicant Completed Reviews [3/3] ======================= [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document Message-Id: <72bc8020-2028-82db-219c-a6ae311e26df(a)redhat.com> [PATCH v4 00/12] target/arm mte fixes Message-Id: <20210406174031.64299-4-richard.henderson(a)linaro.org> Absences ======== Current Review Queue ==================== TODO [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> ================================================================================================================== TODO [RFC 0/8] virtio: Improve boot time of virtio-scsi-pci and virtio-blk-pci Message-Id: <20210325150735.1098387-1-groug(a)kaod.org> =================================================================================================================================== TODO [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> =========================================================================================================================== TODO [PATCH v2 00/29] tcg: Workaround macOS 11.2 mprotect bug Message-Id: <20210314212724.1917075-1-richard.henderson(a)linaro.org> ================================================================================================================================ -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 9 Apr

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] - more release work, bug triage, etc - started implementing the memory-remapping feature of the AN524 FPGA image (which allows the BRAM and QSPI to be swapped either at startup or dynamically under guest control). Some guests (like ARM TF-M) assume the QSPI mapping. thanks -- PMM

4 years, 5 months

1
0
0 0

[ACTIVITY] 29 March-2 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported minor testsuite issues (eg failures with -mabi=ilp32 on aarch64) - re-started looking at validation for cortex-m55, realized that qemu does not support MVE yet * GCC - posted further fix for testcase for PR96770 - fixed PR 99786 - committed fix for PR 99773 * Misc == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending Apr. 4 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted virtio-scmi backend on Zephyr as both Xen DomU and Jailhouse Partition demo suggestion Message-Id: <87ft0cyiqi.fsf(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 6.0-rc2? v1 0/6] check-tcg for non-x86 hosts Message-Id: <20210329110303.15235-1-alex.bennee(a)linaro.org> - posted [PATCH for 6.0-rc2 v2 00/11] various fixes, pre-PR (check-tcg, gdbstub, gitlab) Message-Id: <20210401102530.12030-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [7/7] ======================= [PATCH v1 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210323041238.133835-1-shashi.mallela(a)linaro.org> [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> [PATCH V2 0/6] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1617278395.git.viresh.kumar(a)linaro.org> [0/0] tcg/mips: Fix SoftTLB comparison on mips backend Message-Id: <20210401100457.191458-1-kele.hwang(a)gmail.com> [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document Message-Id: <72bc8020-2028-82db-219c-a6ae311e26df(a)redhat.com> Current Review Queue ==================== TODO [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> ================================================================================================================== TODO [RFC 0/8] virtio: Improve boot time of virtio-scsi-pci and virtio-blk-pci Message-Id: <20210325150735.1098387-1-groug(a)kaod.org> =================================================================================================================================== TODO [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> =========================================================================================================================== TODO [PATCH v2 00/29] tcg: Workaround macOS 11.2 mprotect bug Message-Id: <20210314212724.1917075-1-richard.henderson(a)linaro.org> ================================================================================================================================ -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending 28 Mar 2021

by Richard Henderson

[UM-2] * Fix exec-vary.c vs gcc -flto. * Fix ppc tb->flags usage. * Patch review: - v11 of claudio's arm accel work - hexagon stuff - arm pcmr settings r~

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending Mar. 28 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - attended the [Stratos sync-call] - more talk about rust-vmm for daemons QEMU Upstream Work ([UM-2]) =========================== - posted [PULL v2 00/15] misc fixes (strtoz, plugins, guest-loader) Message-Id: <20210317072216.16316-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] gitlab: extend timeouts for CFI builds Message-Id: <20210322142110.4766-1-alex.bennee(a)linaro.org> - posted [PATCH for 6.0 v2 00/22] fixes for rc1 pre-PR (kernel-doc, semihosting, testing) Message-Id: <20210323165308.15244-1-alex.bennee(a)linaro.org> - posted [PULL for 6.0 00/22] various fixes (kernel-doc, semihosting, testing) Message-Id: <20210324143021.8560-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Other ===== - Provisioning new aarch64 CI machine for QEMU project Completed Reviews [7/7] ======================= [PATCH] FreeBSD: Upgrade to 12.2 release Message-Id: <20210319165138.117225-1-thuth(a)redhat.com> [PATCH] tests/meson: Only build softfloat objects if TCG is selected Message-Id: <20210322114739.4078408-1-f4bug(a)amsat.org> [PATCH v28 00/23] i386 cleanup PART 2 Message-Id: <20210322132800.7470-1-cfontana(a)suse.de> [RFC v10 00/49] arm cleanup experiment for kvm-only build Message-Id: <20210322140206.9513-1-cfontana(a)suse.de> [RFC v11 00/55] arm cleanup experiment for kvm-only build Message-Id: <20210323151749.21299-5-cfontana(a)suse.de> [PATCH 0/2] Fix atomic test in "configure" + bump FreeBSD CI to 12.2 Message-Id: <20210317110512.583747-1-thuth(a)redhat.com> [PATCH v1 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210323041238.133835-1-shashi.mallela(a)linaro.org> Absences ======== - Linaro Connect Sessions Current Review Queue ==================== TODO [RFC 0/8] virtio: Improve boot time of virtio-scsi-pci and virtio-blk-pci Message-Id: <20210325150735.1098387-1-groug(a)kaod.org> =================================================================================================================================== TODO [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> ======================================================================================================================== TODO [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> =========================================================================================================================== TODO [PATCH v2 00/29] tcg: Workaround macOS 11.2 mprotect bug Message-Id: <20210314212724.1917075-1-richard.henderson(a)linaro.org> ================================================================================================================================ -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 26 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - tagged rc0 - various bug investigation/patches for 6.0-ish stuff: + machines with a 'platform bus' incorrectly treated all sysbus devices as hotpluggable: wrote and sent patchseries + respin of gpex pci-host "don't fault for unmapped MMIO/PIO window accesses" patch + document how to use gdbstub/gdb for a multi-cluster machine where the clusters are different gdb inferiors + looked for workarounds for macos Appkit bug where Apple broke menubars for apps that start off as console apps and programmatically switch themselves to being GUI apps; various online suggestions don't seem to help, except for "when app starts, force the Dock to become active and then grab back focus 200ms later". Maybe we'll do that, but it's pretty ugly... thanks -- PMM

4 years, 5 months

1
0
0 0

[ACTIVITY] 22-26 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - No regression to report this week * GCC - testsuite cleanup: committed a patch series - fixed PR 99727 - filed / discussed PR 99773 - WIP PR 99786 * Misc == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 5 months

1
0
0 0

[ACTIVITY] 15-19 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Small improvement to pre-commit testing scripts to allow running a subset of the tests (and thus save a lot of time) * GCC - MVE autovectorization: - vcmp support of FP types OK. - testsuite cleanup: looking at current failures, only found issues with tests so far. Testing several small testsuite patches is taking a long time due to the number of configurations * Misc == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 19 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - softfreeze was this week, lots of pullreq processing - spun v2 of "fix M-profile load of PC/SP from ELF images via memory aliases" thanks -- PMM

4 years, 5 months

1
0
0 0

Please use staging for your new bots; clang-cmake-aarch64-full is red for a month

by Galina Kistanova

Hello Linaro Toolchain Working Group, Please connect your new bots to the staging first and make them reliably green there: linaro-aarch64-flang-debug linaro-aarch64-flang-latest-clang linaro-aarch64-flang-latest-gcc clang-cmake-aarch64-full is red for a month. https://lab.llvm.org/buildbot/#/builders/7?numbuilds=700 Could you move linaro-aarch64-full to the staging and make it green again, please? Please let me know if I could help or you have questions. Thanks Galina

4 years, 6 months

3
4
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Re: Clang targetting x64 linker

by Maxim Kuvyrkov

Hi Joel, Indeed, LLD is not configured to be used by default in LLVM-12.0.0-rc1. You need to add -fuse-ld=lld option for it to work. We’ll fix this in the final LLVM-12 release for WoA, which is expected in around 2 weeks. Thanks for catching this! c:\Users\tcwg\source\maxim>..\llvm-12.0.0-rc1\bin\clang-cl.exe hello.c clang-cl: error: unable to execute command: Couldn't execute program 'C:\BuildTools\VC\Tools\MSVC\14.28.29333\bin\Hostx64\arm64\link.exe': Unknown error (0xD8) clang-cl: error: linker command failed with exit code 1 (use -v to see invocation) c:\Users\tcwg\source\maxim>..\llvm-12.0.0-rc1\bin\clang-cl.exe -fuse-ld=lld hello.c c:\Users\tcwg\source\maxim>hello.exe Hello c:\Users\tcwg\source\maxim>..\llvm-12.0.0-rc1\bin\clang.exe -fuse-ld=lld hello.c c:\Users\tcwg\source\maxim>hello.exe Hello -- Maxim Kuvyrkov https://www.linaro.org > On 4 Mar 2021, at 19:43, Joel Cox <Joel.Cox(a)arm.com> wrote: > > Hi > > I was trying "clang hello.c" from command line, but "clang-cl hello.c" gives me the same error. I am unsure if this is what you mean but neither work. > > Thanks, > Joel > > -----Original Message----- > From: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org> > Sent: 04 March 2021 16:40 > To: Joel Cox <Joel.Cox(a)arm.com> > Cc: linaro-toolchain(a)lists.linaro.org > Subject: Re: Clang targetting x64 linker > > Hi Joel, > > Are you using clang-cl.exe as compiler/linker driver? It’s easiest to use clang-cl.exe as it aims to be a direct replacement for MSVC’s cl.exe, but will use LLVM tools. In particular, when clang-cl.exe uses LLVM Linker (LLD) by default. > > If you are using linux-style clang.exe as the driver, then you need to specify -fuse-ld=lld to use LLD. > > Does this help? > > Regards, > > -- > Maxim Kuvyrkov > https://www.linaro.org > >> On 4 Mar 2021, at 19:11, Joel Cox <Joel.Cox(a)arm.com> wrote: >> >> Hi >> >> I've been trying to run clang on a Windows on Arm machine, but it keeps trying to using the link.exe located in "Visual studio/..../Host64/arm64", which is (seemingly) an x64 tool and as such doesn't run, and crashes the process. >> Is there a way to set clang to look at VS's x86 link.exe? Or if there is an arm64 version that clang should be using instead? >> >> Thanks, >> Joel >> IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. >> _______________________________________________ >> linaro-toolchain mailing list >> linaro-toolchain(a)lists.linaro.org >> https://lists.linaro.org/mailman/listinfo/linaro-toolchain > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 6 months

1
2
0 0

[ACTIVITY] week ending 14 Mar 2021

by Richard Henderson

[UM-2] * Clean up tcg code_gen_buffer mapping. * Clean up ppc tb->flags madness. * Rebase tci clean up. * Random patch review. [VIRT-349] * Send v4 of sve2 patch set. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending Mar. 14 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - attended the [rust-vmm sync call] [rust-vmm sync call] <https://etherpad.opendev.org/p/rust-vmm-sync-2021> VirtIO RPMB ([STR-5]) - followed more of [RFC PATCH 0/5] RPMB internal and user-space API + WIP virtio-rpmb frontend Message-Id: <CACRpkda9f-BNmu-CaNsghnDoOcSXvvvji=tag2Xos+tg_nNZ0w(a)mail.gmail.com> [STR-5] <https://projects.linaro.org/browse/STR-5> [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [qemu-web PATCH] pages: update deprecation policy links to "official" manual Message-Id: <20210308103049.3653-1-alex.bennee(a)linaro.org> - posted [qemu-web RFC PATCH] _download/source.html: show the GPG fingerprint for releases Message-Id: <20210308111649.14898-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/4] semihosting/next (SYS_HEAPINFO fix) Message-Id: <20210309141727.12522-1-alex.bennee(a)linaro.org> - posted [PULL 00/18] testing, docs, semihosting move and guest-loader Message-Id: <20210308135104.24903-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/15] testing, docs, semihosting move and guest-loader Message-Id: <20210310160002.11659-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/7] testing/next (hexagon 2, electric boogaloo) Message-Id: <20210310192331.29284-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/15] testing, docs, semihosting move and guest-loader Message-Id: <20210310160002.11659-1-alex.bennee(a)linaro.org> - posted [PATCH v3 0/4] semihosting/next (SYS_HEAPINFO) Message-Id: <20210309172127.20470-1-alex.bennee(a)linaro.org> - posted [PATCH v5 0/5] semihosting/next (SYS_HEAPINFO) Message-Id: <20210312102029.17017-1-alex.bennee(a)linaro.org> - posted [PATCH v1 00/14] plugins/next (phys addr, syscalls, lots of docs) Message-Id: <20210312172821.31647-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH v2] linux-user: Fix executable page of /proc/self/maps Message-Id: <20210308091959.986540-1-nsurbayrole(a)quarkslab.com> [PATCH] plugins: new syscalls plugin Message-Id: <20200812115816.4454-1-matthias(a)weckbecker.name> Added: <2020-08-12 Wed> [PATCH v2] plugins: Expose physical addresses instead of device offsets Message-Id: <20210309202802.211756-1-aaron(a)os.amperecomputing.com> Absences ======== - Lockdown 3: Half day schooling - ends soon! Current Review Queue ==================== TODO [PATCH 0/4] Upgrade Meson to 0.57.x Message-Id: <20210310104937.253532-1-pbonzini(a)redhat.com> ================================================================================================= TODO [RFC v3 00/23] arm cleanup experiment for kvm-only build Message-Id: <20210303114053.20305-1-cfontana(a)suse.de> ================================================================================================================== Added: <2021-03-04 Thu> TODO [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> =================================================================================================================== Added: <2021-02-16 Tue> TODO [PATCH v2 00/15] tcg/arm: host neon support -- Alex Bennée

4 years, 6 months

1
0
0 0

[ACTIVITY] 8-12 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Bisected last week regressions, but there had already been reported/fixed. * GCC - MVE autovectorization: - vcmp support mostly complete. support of FP types looks OK, though trickier than expected. - vld2/vst2 and vld4/vst4 done. * Misc - stm32 benchmarking harness: good speed up after removing useless toolchain multilib builds (7 minutes vs 1h+) - fixed GCC bisect Jenkins job == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * Resume GDB/FDPIC work * Troubleshoot Jenkins problems

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 12 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Mostly caught up on code review now: have done all the patches that are targeting 6.0 - Sent out some pullreqs with for-6.0 material - Wrote a patch to make us emulate the right number of counters for the PMU according to what each CPU should have, rather than always 4 - Had a go at fixing the M-profile vector table load on reset to handle aliased memory regions * QEMU-364 [QEMU support for ARMv8.1-M extensions] - mps3-an524 and -an547 patchseries now in master: this epic is done! thanks -- PMM

4 years, 6 months

1
0
0 0

Pre-commit CI with libc++

by Louis Dionne

Folks, I am pleased to announce the move of libc++ to pre-commit CI. Over the past few months, we have set up Buildkite jobs on top of the Phabricator integration built by Mikhail and Christian, and we now run almost all of the libc++ build bots whenever a Phabricator review is created. The bots also run when a commit is pushed to the master branch, similarly to the existing Buildbot setup. You can see the libc++ pipeline in action here: https://buildkite.com/llvm-project/libcxx-ci. This is great -- we’ve been waiting to set up pre-commit CI for a long time, and we’ve seen a giant productivity gain since it’s up. I think everyone who contributes to libc++ greatly benefits, seeing how reviews are now used to trigger CI and improve our confidence in changes. This change does have an impact on existing build bots that are not owned by one of the libc++ maintainers. While I transferred the build bots that we owned (which Eric had set up) to Buildkite, the remaining build bots will have to be moved to Buildkite by their respective owners. These builds bots are (owners in CC): libcxx-libcxxabi-x86_64-linux-debian libcxx-libcxxabi-x86_64-linux-debian-noexceptions libcxx-libcxxabi-libunwind-x86_64-linux-debian libcxx-libcxxabi-singlethreaded-x86_64-linux-debian libcxx-libcxxabi-libunwind-armv7-linux libcxx-libcxxabi-libunwind-armv8-linux libcxx-libcxxabi-libunwind-armv7-linux-noexceptions libcxx-libcxxabi-libunwind-armv8-linux-noexceptions libcxx-libcxxabi-libunwind-aarch64-linux libcxx-libcxxabi-libunwind-aarch64-linux-noexceptions The process of moving these bots over to Buildkite is really easy. Please take a look at the documentation at https://libcxx.llvm.org/docs/AddingNewCIJobs.html#addingnewcijobs and contact me if you need additional help. To make sure we get the full benefits of pre-commit CI soon, I would like to put a cutoff date on supporting the old libc++ builders at http://lab.llvm.org:8011/builders. I would propose that after January 1st 2021 (approx. 1 month from now), the libc++ specific build bots at lab.llvm.org be removed in favor of the Buildkite ones. If you currently own a bot, please make sure to add an equivalent Buildkite bot by that cutoff date to make sure your configuration is still supported, or let me know if you need an extension. Furthermore, with the ease of creating new CI jobs with this infrastructure, we will consider any libc++ configuration not covered by a pre-commit bot as not explicitly supported. It doesn’t mean that such configurations won’t work -- it just means that we won’t be making bold claims about supporting configurations we’re unable to actually test. So if you care about a configuration, please open a discussion and let’s see how we can make sure it's tested properly! I am thrilled to be moving into the pre-commit CI era. The benefits we see so far are huge, and we're loving it. Thanks, Louis PS: This has nothing to do with a potential move or non-move to GitHub. The current pre-commit CI works with Phabricator, and would work with GitHub if we decided to switch. Let’s try to keep those discussions separate :-). PPS: We’re still aiming to support non libc++ specific Buildbots. For example, if something in libc++ breaks a Clang bot, we’ll still be monitoring that. I’m just trying to move the libc++-specific configurations to pre-commit.

4 years, 6 months

5
6
0 0

[ACTIVITY] week ending 7 Mar 2021

by Richard Henderson

[VIRT-349 # QEMU SVE2 Support ] I have a working FVP SVE2 install! I used a new FVP version (11.13.36) from the last time that I tried (11.13.21 on Jan 27). I used a debian-testing snapshot from 1-MAR, which has linux 5.10 bundled, and fvp revc dtb installed. I used https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.gi… (which is linked to by one of the howtos that Peter forwarded) and chose the "pre-built uefi" version. I need to report a bug on this build script -- the "build from source" option does not work on a system that has all python3 and no python2. I've rebuilt all of the risu trace files for vq=4 (512-bit). I'm now refreshing my qemu branch to test. [UM-61 # TCG Core Maintainership ] PR for patch queue; aa64 fixes, tci fixes, tb_lookup cleanups. [UM-2 # Upstream Maintainership ] Patch review, mostly v8.1m board stuff. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending Mar. 7 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted [PATCH v2] vhost-user.rst: add clarifying language about protocol negotiation Message-Id: <20210303145011.14547-1-alex.bennee(a)linaro.org> Linux Userspace ABI for RPMB devices ([STR-31]) ----------------------------------------------- - posted [RFC PATCH 0/5] RPMB internal and user-space API + WIP virtio-rpmb frontend Message-Id: <20210303135500.24673-1-alex.bennee(a)linaro.org> - has stimulated discussion on the thread, will see next posting from Thomas QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/9] testing/next (docs, hexagon, cfi, docker) Message-Id: <20210305092328.31792-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/3] semihosting/next (move from hw, heapinfo) Message-Id: <20210305135451.15427-1-alex.bennee(a)linaro.org> - optimising tb lookup ---------------------- - CLOSING NOTE [2021-03-05 Fri 17:22] rth merged my changes plus a pre-compute of cflags. Completed Reviews [8/8] ======================= [PATCH v3 0/2] gitlab-ci.yml: Add jobs to test CFI Message-Id: <20210304030948.9367-1-dbuono(a)linux.vnet.ibm.com> [PATCH 0/4] hexagon: Add Docker image & testing to gitlab-ci Message-Id: <20210228222314.304787-1-f4bug(a)amsat.org> - CLOSING NOTE [2021-03-04 Thu 20:04] Queued to my tree Added: <2021-03-02 Tue> [PATCH v2] tests/docker: Use --arch-only when building Debian cross image Message-Id: <20210223211115.2971565-1-f4bug(a)amsat.org> [PATCH] linux-user: Adjust pgd_find_hole_fallback result with guest_loaddr Message-Id: <20210303094919.x6wnlh6qulx72fz6(a)titan.localdomain> - CLOSING NOTE [2021-03-05 Fri 14:12] Added: <2021-03-03 Wed> [PATCH 00/44] hw/arm: New board model mps3-an547 Message-Id: <20210219144617.4782-1-peter.maydell(a)linaro.org> - CLOSING NOTE [2021-03-05 Fri 14:14] Looks like others have already looked over it. ADDED: <2021-03-04 Thu> [PATCH v3 00/70] TCI fixes and cleanups Message-Id: <20210208023752.270606-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2021-03-05 Fri 16:59] v4 released, wish I'd noticed earlier ;-) Added: <2021-02-08 Mon> [PATCH 00/27] tcg patch queue Message-Id: <20210302175741.1079851-1-richard.henderson(a)linaro.org> [PATCH 0/3] docs: replace master/slave with more accurate wording Message-Id: <20210226143413.188046-1-pbonzini(a)redhat.com> Absences ======== - Lockdown 3: Half day schooling - ends soon! Current Review Queue ==================== TODO [RFC v3 00/23] arm cleanup experiment for kvm-only build Message-Id: <20210303114053.20305-1-cfontana(a)suse.de> ================================================================================================================== Added: <2021-03-04 Thu> TODO [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> =================================================================================================================== Added: <2021-02-16 Tue> TODO [PATCH v2 00/15] tcg/arm: host neon support Message-Id: <20210208024625.271018-1-richard.henderson(a)linaro.org> ================================================================================================================== Added: <2021-02-08 Mon> -- Alex Bennée

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 5 Mar

by Peter Maydell

Progress (short week, 2 days): * Some time spent on setting up new work laptop * Started in on the pile of code review that had built up while I was on holiday... made a bit of progress and sent out one pullreq. Queue length now: 16 series. thanks -- PMM

4 years, 6 months

1
0
0 0

What does suffix ' ... isra.0' mean in compiled symbols in GCC 10.2?

by Guodong Xu

Hi, all Does anybody know what does '.....isra.0' mean in GCC 10.2 compiled objects? I just noticed this issue when using bcc/eBPF tools. I submitted the detail into * https://github.com/iovisor/bcc/issues/3293 Simply put, when building a linux kernel with GCC 10.2, the symbol 'finish_task_switch' becomes 'finish_task_switch.isra.0' in the object (as reported by 'nm') Because a lot of kernel tracers (such as bcc) use 'finish_task_switch' as the probe point, this change in the compilation result can make all result such tools fail. Thanks. Best regards, Guodong Xu

4 years, 6 months

2
2
0 0

[ACTIVITY] 1-5 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a couple of regressions to bisect. - minor testcase fix - reported a couple of new failures * GCC - MVE autovectorization: - vcmp support mostly complete. Minor update needed to support FP types. - working on interleaved vector load/store support * Misc - fixed stm32 benchmarking harness, it's working again. - submitted patches to reduce the toolchain build time (for benchmarking we don't need all multilibs which take ages to build) == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 6 months

1
0
0 0

Clang targetting x64 linker

by Joel Cox

Hi I've been trying to run clang on a Windows on Arm machine, but it keeps trying to using the link.exe located in "Visual studio/..../Host64/arm64", which is (seemingly) an x64 tool and as such doesn't run, and crashes the process. Is there a way to set clang to look at VS's x86 link.exe? Or if there is an arm64 version that clang should be using instead? Thanks, Joel IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 6 months

2
1
0 0

LLVM12 Clang doesn't start

by Joel Cox

Hi, I've been trying to use clang on Windows on Arm machine (Samsung Galaxy Book S), but whenever I try to use it, I get either nothing (in powershell) or an error popup: "The application was unable to start correctly (0x000007b)". The release I'm using is LLVM-12.0.0-rc1-woa64.exe<https://github.com/llvm/llvm-project/releases/download/llvmorg-12.0.0-rc1/L…> from https://github.com/llvm/llvm-project/releases/tag/llvmorg-12.0.0-rc1 I have a feeling there might be a library or dependency I am missing. Any help with how to resolve this issue would be appreciated. Thanks, Joel IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 6 months

2
1
0 0

[ACTIVITY] week ending 28 Feb 2021

by Richard Henderson

[UM-2 # QEMU Upstream Work] * A lot of patch review. * Some target/i386 cleanup, as followup to said patch review. * Collecting patches for tcg-next. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending Feb. 28 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - some planning discussion around STR-26/STR-7 - posted vhost reply_ack negotiation (a.k.a differences in vhost-user behaviour with libvhost-user and vhost-user-backend.rs) Message-Id: <8735xskm7j.fsf(a)linaro.org> - posted [vhost.rs PR] - posted [VHOST USER SPEC PATCH] vhost-user.rst: add clarifying language about protocol negotiation Message-Id: <20210226111619.21178-1-alex.bennee(a)linaro.org> [vhost.rs PR] <https://github.com/rust-vmm/vhost/pull/24> [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v2 0/6] testing/next (meson check-tcg, fedora bump, docs) Message-Id: <20210222101455.12640-1-alex.bennee(a)linaro.org> - posted [PULL 0/7] testing updates (build, docs, dumps) Message-Id: <20210224114926.6303-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Other ===== - some kernel/QEMU debugging for LKFT folks Completed Reviews [4/4] ======================= [PATCH v20 00/17] i386 cleanup PART 2 Message-Id: <20210218172156.25520-1-cfontana(a)suse.de> - CLOSING NOTE [2021-02-22 Mon 13:28] Only glanced over, mainly in prep for ARM series which is based on this Added: <2021-02-19 Fri> [PATCH] tests/docker: Use --arch-only when building Debian cross images Message-Id: <20210223170910.2916721-1-f4bug(a)amsat.org> [PATCH v5 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20210219215838.752547-4-crosa(a)redhat.com> [PATCH 0/3] gitlab-pipeline-status script: provide more information on errors Message-Id: <20210222193240.921250-2-crosa(a)redhat.com> Absences ======== - Lockdown 3: Half home-schooling Current Review Queue ==================== * [PATCH 0/2] semihosting: Move it out of hw/ Message-Id: <20210226131356.3964782-1-f4bug(a)amsat.org> Added: <2021-02-26 Fri> * [RFC v1 00/38] arm cleanup experiment for kvm-only build Message-Id: <20210221092449.7545-1-cfontana(a)suse.de> Added: <2021-02-21 Sun> * [PATCH 00/44] hw/arm: New board model mps3-an547 Message-Id: <20210219144617.4782-1-peter.maydell(a)linaro.org> Added: <2021-02-20 Sat> * [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> Added: <2021-02-16 Tue> -- Alex Bennée

4 years, 6 months

1
0
0 0

[ACTIVITY] 22-26 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a few regressions to bisect. Fixed a minor testcase issue * GCC - MVE autovectorization: Working on vcmp. After some cleanup & factorization, the cmp operators work on GCC vectors. I will now resume work on auto-vectorization. * Misc - fixes in stm32 benchmarking harness == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending 21 Feb 2021

by Richard Henderson

* After proving that the aarch64 host problem with booting s390x with virtio was lack of barriers for the guest memory model, I've spent some time working on a ld-acq/st-rel optimizer for tcg. * Minor rev of tci rewrite. * Some patch review on claudio's kvm/tcg split. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending Feb. 21 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Wrote a short pitch deck for Stratos - AGL Follow-up sync discussion - lead to thinking about measuring the impact of buffer copy for virtio-gpu guests Message-Id: <87y2fmsrxw.fsf(a)linaro.org> - [Stratos Sync - this week discussing virtio-i2c] - spent some time discussing firmer requirements for the work [Stratos Sync - this week discussing virtio-i2c] <https://collaborate.linaro.org/display/STR/2021-02-18+Project+Stratos+Sync+…> VirtIO RPMB ([STR-5]) - More work on the [Rust version of virtio-rpmb] - after debugging vhost reply_ack negotiation issues Message-Id: <8735xskm7j.fsf(a)linaro.org> now can boot kernel - next step processing the actual RPMB frames [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/15] testing and gdbstub updates Message-Id: <20210215094244.12716-1-alex.bennee(a)linaro.org> - posted [PATCH v2] meson.build: expose TCG cross compiler information in summary Message-Id: <20210216102522.6279-1-alex.bennee(a)linaro.org> - posted [PATCH v3 00/23] plugins/next pre-PR (hwprofile, regression fixes, icount count fix) Message-Id: <20210213130325.14781-1-alex.bennee(a)linaro.org> - posted [PULL 00/23] plugin updates (hwprofile, CF_NOCACHE, io_recompile) Message-Id: <20210218094706.23038-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/6] my current testing/next queue (meson/gitlab/fedora bump) Message-Id: <20210217121932.19986-4-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [8/8] ======================= [PATCH] linux-user/elfload: munmap proper address in pgd_find_hole_fallback Message-Id: <20210131061849.12615-1-vfazio(a)xes-inc.com> [PATCH] linux-user/elfload: do not assume MAP_FIXED_NOREPLACE kernel support Message-Id: <20210131061930.14554-1-vfazio(a)xes-inc.com> [RFC v18 00/15] i386 cleanup PART 2 Message-Id: <20210212123622.15834-1-cfontana(a)suse.de> [PATCH v2] target/mips: fetch code with translator_ld Message-Id: <20210125105818.2707067-1-f4bug(a)amsat.org> [PATCH] travis.yml: Limit simultaneous jobs to 3 Message-Id: <20210217102531.1441557-1-thuth(a)redhat.com> [PATCH] gitlab-ci: Display Avocado log content when tests timeout Message-Id: <20210215171438.935665-1-philmd(a)redhat.com> [PATCH] gitlab-ci.yml: Run check-tcg with TCI Message-Id: <20210127055903.40148-1-thuth(a)redhat.com> [PATCH] docker: Bump Fedora images to release 33 Message-Id: <20210118181255.314672-1-philmd(a)redhat.com> Absences ======== - Lockdown 3: No schooling, just half term distractions! Current Review Queue ==================== * [PATCH v20 00/17] i386 cleanup PART 2 Message-Id: <20210218172156.25520-1-cfontana(a)suse.de> Added: <2021-02-19 Fri> * [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> Added: <2021-02-16 Tue> * [PATCH v2 00/15] tcg/arm: host neon support Message-Id: <20210208024625.271018-1-richard.henderson(a)linaro.org> Added: <2021-02-08 Mon> -- Alex Bennée

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 19 Feb

by Peter Maydell

Progress: * QEMU-364 [QEMU support for ARMv8.1-M extensions] + sent out v2 of the MPS3-AN524 series (minor changes only) + discovered that I need to implement the SSE-300's System Counter + implemented the system counter, did some final testing and reviewing, and sent out v1 of the MPS3-AN547 series to the list + once these patches are reviewed and in master the QEMU-413 epic will be complete -- PMM

4 years, 6 months

1
0
0 0

Many of your builders are red for long time

by Galina Kistanova

Hello Linaro Toolchain Working Group, libcxx-libcxxabi-libunwind-armv8-linux has been red for 5 days. clang-cmake-aarch64-global-isel has been red for 10 days. clang-cmake-aarch64-quick has been red for 10 days. clang-cmake-armv7-global-isel has been red for 10 days. clang-cmake-armv7-lnt has been red for 10 days. clang-cmake-aarch64-lld has been red for 11 days. clang-cmake-armv8-lld has been red for 11 days. clang-cmake-thumbv7-full-sh has been red for 11 days. clang-cmake-armv7-full has been red for 11 days. Is anybody looking at this? I also noticed that some of your workers are less reliable than others. For example, inaro-tk1-09 worker was last time producing a green build 2 months ago - http://lab.llvm.org:8011/#/workers/2?numbuilds=500 I'm removing the linaro-tk1-09 worker from the production buildbot for now. Please feel free to connect it to the staging and make the builder reliably green. Then it could be returned back to the production. linaro-armv8-windows-msvc-01 and linaro-armv8-windows-msvc-02 have been red for the least 4 months. I'm removing them from the production buildbot. You can return them back to production after they are reliably green in the staging. Please feel free to ask if you have questions. Thanks Galina

4 years, 6 months

3
7
0 0

[ACTIVITY] 8-12 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a few regressions to bisect. Fixed a minor testcase issue - native validation in Linaro's lab: we still see a few random results * GCC - MVE autovectorization: Working on vcmp. * Misc - fixes in stm32 benchmarking harness == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking Holidays next week, back Monday 22nd Feb

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 12 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + sent out a small code-cleanup patchset for some arm display device models to remove no-longer-needed support for non-32bpp outputs + tracked down (with the aid of Paolo) why our build system had started building the documentation every time you run 'make'; sent a fix + code review todo queue status: 12 items, but the oldest was only sent to the list on Monday... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + An MPS3 Cortex-M55 FPGA image is now publicly available: the AN547. We'll provide a model of this in QEMU. Started working on the patchseries to implement it (relatively small changes on top of the SSE-300 work I've already done but not sent out, and the mps3-an524 series I sent out for review last week). This is basically code-complete but I need to do some more testing and ideally I'd like the AN524 series to get reviewed before I send out another 40-patch series that would have to be based on top of that one. thanks -- PMM

4 years, 7 months

1
0
0 0

Re: [lldb-dev] 12.0.0-rc1 Release has been tagged

by Diana Picus

Hello, I've uploaded binaries for Windows on Arm: 081373cc76e88224020fea42eba2161d972f03bb83ebc055fb3cd4f2cfcdfb95 LLVM-12.0.0-rc1-woa64.exe It was built from the current release/12.x branch (commit b46924ee) with two patches applied on top: - https://reviews.llvm.org/D96259 - https://reviews.llvm.org/D96498 It contains "clang;clang-tools-extra;lld;compiler-rt” projects. Compiler-RT has sanitizers disabled (MEMPROF and XRAY use sanitizer infrastucture). I.e., === + -DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;lld;compiler-rt" ^ + -DCOMPILER_RT_BUILD_SANITIZERS=OFF ^ + -DCOMPILER_RT_BUILD_MEMPROF=OFF ^ + -DCOMPILER_RT_BUILD_XRAY=OFF ^ === I've attached the changes we had to make to llvm/utils/releases/build_llvm_package.bat. @Maxim Kuvyrkov is going to clean them up and post a patch in the next couple of weeks (he's been doing all the hard work, I'm just uploading). This is the first time we're trying to provide a release for Windows on Arm, so if anyone has any comments or questions, feel free to send an email :) Cheers, Diana On Thu, 28 Jan 2021 at 05:05, Tom Stellard via lldb-dev < lldb-dev(a)lists.llvm.org> wrote: > Hi, > > I've tagged the 12.0.0-rc1 release. Testers can begin testing and upload > binaries. > > -Tom > > _______________________________________________ > lldb-dev mailing list > lldb-dev(a)lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-dev >

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending Feb. 7 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - TSC Stratos next cycle presentation - [Stratos Sync - this week discussing Rust] - Followed up on Rust presentation and sketched out some areas of interest [STR-9] <https://projects.linaro.org/browse/STR-9> [Stratos Sync - this week discussing Rust] <https://collaborate.linaro.org/display/STR/2021-02-04+Project+Stratos+Sync+…> QEMU Support for Xen ([STR-20]) =============================== - latest iteration of [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> - while re-basing [my Xen loader and fixes tree] - realised that [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Message-Id: <20200929224355.1224017-1-philmd(a)redhat.com> would be useful - which awaits [PATCH v14 00/22] i386 cleanup PART 2 Message-Id: <20210128092814.8676-1-cfontana(a)suse.de> being merged - bunch of related review of pre-cursor stuff [STR-20] <https://projects.linaro.org/browse/STR-20> [my Xen loader and fixes tree] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Upstream Work ([UM-2]) =========================== - caught up on a bunch of review - got about halfway through rth's mega TCI series - posted [PATCH v1 00/15] testing/gdbstub/docs pre-PR Message-Id: <20210202134001.25738-1-alex.bennee(a)linaro.org> - will roll PR on Monday - some discussion on Detecting Faulting Instructions From Plugins Message-Id: <YBTRSK4/F5KLH+FZ(a)strawberry.localdomain> - looks like we need special handling for instrumentation on recompiled IO ops [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [5/5] ======================= [PATCH 00/10] target: Provide target-specific Kconfig Message-Id: <20210131111316.232778-1-f4bug(a)amsat.org> [PATCH v3 0/5] Fix some style problems in contrib Message-Id: <20210118031004.1662363-1-zhouyang789(a)huawei.com> [PATCH v15 00/23] i386 cleanup PART 2 Message-Id: <20210201100903.17309-1-cfontana(a)suse.de> [PATCH 00/22] Acceptance Test: introduce base class for Linux based tests Message-Id: <20210203172357.1422425-9-crosa(a)redhat.com> [PATCH v2 0/5] Move remaining x86 Travis jobs to the gitlab-CI Message-Id: <20210205091857.845389-1-thuth(a)redhat.com> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v6 00/11] Support disabling TCG on ARM (part 2) Message-Id: <20210131115022.242570-1-f4bug(a)amsat.org> Added: <2021-01-31 Sun> * [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-29 Fri> * [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Message-Id: <20210124025306.3949-1-leif(a)nuviainc.com> Added: <2021-01-25 Mon> -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] 1-5 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - not really catching up, now ~15 days late due to the numerous commits. Manually fast-forwarded the latest build to today. I'll bisect manually for regressions if needed. - re-enabled native validation in Linaro's lab: we are sending test results again * GCC - MVE autovectorization: vorn patch committed. Working on vcmp. == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 5 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + lots of code review this week, including another round of rth's MTE user-mode patchset * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Sent out an RFC proposing some more Clock API changes (since it'll be a while before I'm ready to post the series with the new timer device that requires them) + The SSE-200 Cortex-M33-based MPS3 AN524 FPGA image is a useful target to model: the Zephyr folks would like it, and it is a good stepping stone to an MPS3 FPGA image with a Cortex-M55/SSE-300 in it. Wrote a patchset for an mps3-an524 board model, and sent it out for review. -- PMM

4 years, 7 months

1
0
0 0

an Ubuntu test rebuild with LTO turned on

by Matthias Klose

Please see https://lists.ubuntu.com/archives/ubuntu-devel/2021-January/041341.html https://wiki.ubuntu.com/ToolChain/LTO Some builds only fail on AArch64, these are: buildlog_ubuntu-hirsute-arm64.abiword_3.0.4~dfsg-2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.adabrowse_4.0.3-12_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.adacontrol_1.21r6b-5_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.armnn_19.11.1-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.cctools_7.1.2-2ubuntu3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.csound_1:6.14.0~dfsg-6build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.dh-ada-library_6.20_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.dietlibc_0.34~cvs20160606-12_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.entropybroker_2.9-3build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.fpc_3.2.0+dfsg-8build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.grcompiler_5.2-2.1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.haskell-hopenpgp-tools_0.23.1-1build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ignition-common_3.5.0+dfsg1-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.lazarus_2.0.10+dfsg-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.lepton-eda_1.9.13-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.libcxx-serial_1.2.1-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.minetest_5.3.0+repack-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ogre-1.12_1.12.5+dfsg1-1ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.openmsx_16.0-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.parsinsert_1.04-7ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.prometheus-alertmanager_0.21.0+ds-2build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.pyqt5_5.15.2+dfsg-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.racon_1.4.13-2build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.rampler_1.1.1-3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ruby-http-parser.rb_0.6.0-5_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.shasta_0.6.0-4build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.snd_20.9-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.sogo_4.3.2-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.swiglpk_4.65.0-2build3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.synfig_1.2.2+dfsg-3build3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.synfigstudio_1.2.2-1build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.tcc_0.9.27+git20200814.62c30a4a-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.unar_1.10.1-2build9_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.valgrind_1:3.16.1-1ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.vulkan-tools_1.2.154.0+dfsg1-1_BUILDING.txt.gz arm64 Note that some of those like the Ada related ones are false positives, and I didn't look at the arm64 specific issues yet. All builds were done using the GCC 10 branch. Matthias

4 years, 7 months

2
2
0 0

[ACTIVITY] week ending Jan. 31 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - some prep for next weeks TSC QEMU Device and Machine Models ([QEMU-418]) =========================================== - added a bunch of new cards for ARMv8.7 features using ARMs new feature type QEMU Support for Xen ([STR-20]) =============================== - latest iteration of [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> - while re-basing [my Xen loader and fixes tree] - realised that [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Message-Id: <20200929224355.1224017-1-philmd(a)redhat.com> would be useful - which awaits [PATCH v14 00/22] i386 cleanup PART 2 Message-Id: <20210128092814.8676-1-cfontana(a)suse.de> being merged [STR-20] <https://projects.linaro.org/browse/STR-20> [my Xen loader and fixes tree] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/2] meson fixups for check-tcg/softfloat Message-Id: <20210126145356.7860-1-alex.bennee(a)linaro.org> - posted some documentation patches while helping LKFT team get up and running - [PATCH] docs/system: document an example vexpress-a15 invocation Message-Id: <20210128185300.2875-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH v4 0/4] meson: Try to clarify TCG / TCI options for new users Message-Id: <8f1f2dc6-5ad2-7d48-c2f9-9afa1e4d4065(a)weilnetz.de> [PATCH 00/23] TCI fixes and cleanups Message-Id: <20210128082331.196801-1-richard.henderson(a)linaro.org> [PATCH] accel/tcg: Add URL of clang bug to comment about our workaround Message-Id: <20210129130330.30820-1-peter.maydell(a)linaro.org> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-29 Fri> * [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Message-Id: <20210124025306.3949-1-leif(a)nuviainc.com> Added: <2021-01-25 Mon> * [PATCH v3 00/21] target-arm: Implement ARMv8.5-MemTag, user mode Message-Id: <20210115224645.1196742-1-richard.henderson(a)linaro.org> Added: <2021-01-18 Mon> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] 25-29 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - not really catching up, now ~10 days late due to the numerous commits * GCC - Neon intrinsics: vceqzq improvement (PR98730) commited - MVE autovectorization: vorn patch submitted - opened PR98891 about Neon vectorization regression * infra: - reviewed patches. - ABE's make-check-gcc is currently broken == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 29 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + usual upstream maintenance, code review, etc * QEMU-364 [QEMU support for ARMv8.1-M extensions] + CMSDK Clock changes now upstream + When integrating those with the SSE timer model, found what seem like some more clock API changes we could use; patches in progress Some Arm-internal training and similar admin tasks this week. thanks -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending 24 Jan 2021

by Richard Henderson

[UM-61 TCG Maint] 3 different attempts at fixing the out-of-temps failure produced by the tcg-constant patch set. The last, longjmp to restart w/ a smaller tb, seems unlikely to have unanticipated side effects. [UM-2 QEMU Maint] Refresh two patches toward cortex-a76. Misc patch review. Partial fix for target/ppc mis-use of tb->flags. r~

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending Jan. 24 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted Project Stratos planning priorities for the next development cycle (-> Oct2021) Message-Id: <87im7rtpyq.fsf(a)linaro.org> - baring feedback from members during voting I think this is what we are doing - attended [AGL discussion] on zero-copy for virtio-gpu with Peter Griffin - more meetings on other collaboration opportunities, drew more slide ware - bootstrapped my RB5 rig, just need to figure out how to update the kernel [STR-9] <https://projects.linaro.org/browse/STR-9> [AGL discussion] <https://confluence.automotivelinux.org/display/VE/Meeting+Agenda?src=contex…> QEMU Device and Machine Models ([QEMU-418]) =========================================== - flurry of syncing and card creation, solidified [QEMU-414] [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> [QEMU-414] <https://projects.linaro.org/browse/QEMU-414> QEMU Support for Xen ([STR-20]) =============================== - continued looking at [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> [STR-20] <https://projects.linaro.org/browse/STR-20> QEMU Upstream Work ([UM-2]) =========================== - respun [PULL v2 00/30] testing, gdbstub and semihosting Message-Id: <20210118111745.20104-1-alex.bennee(a)linaro.org> to fix NetBSD issue - posted [PATCH v1 0/6] testing/next (docker binfmt tests) Message-Id: <20210119175208.763-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/8] testing/next (docker, binfmt, gdb version) Message-Id: <20210122181854.23105-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [4/4] ======================= [PATCH] util/log: flush TB cache when log level changes Message-Id: <161130982491.1038646.15688151175539344664.stgit@pasha-ThinkPad-X280> [PATCH v3] hw/core/qdev-properties-system: Rewrite set_pci_host_devaddr using GLib Message-Id: <20201125083300.861206-1-philmd(a)redhat.com> [RFC PATCH] tests/docker: Allow passing --network option when building images Message-Id: <20210119054502.531451-1-f4bug(a)amsat.org> [PATCH] tcg: Increase the static number of temporaries Message-Id: <20210121025439.1120405-1-richard.henderson(a)linaro.org> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v3 00/21] target-arm: Implement ARMv8.5-MemTag, user mode Message-Id: <20210115224645.1196742-1-richard.henderson(a)linaro.org> Added: <2021-01-18 Mon> * [PATCH 0/6] accel: Restrict TCG-specific code Message-Id: <20210117164813.4101761-1-f4bug(a)amsat.org> Added: <2021-01-18 Mon> * [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-13 Wed> * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] 18-22 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - catching up, still ~1 week late due to the numerous commits * GCC - Neon intrinsics: looking at vceqzq improvement (PR98730) - MVE autovectorization: WIP on vorn and vcmp. - helping with cortex-m0 libgcc patch validation. Opened PR98779 about issues in libgcc wrt -mpure-code. * infra: - reviewed patches. - ABE's make-check-gcc is currently broken == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 22 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review (including RTH's MTE-for-user-mode-emulation) + Investigating an intermittent failure of a test case involving an s390 guest on aarch64 hosts... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Converted the ARMSSE (IoTKit/SSE-200) code over to use the Clock framework, which was added to QEMU after ARMSSE was first written. (This is a prereq for adding the new-in-SSE-300 timer device, which will use Clocks.) Sent the patches out for review. I'm currently experimenting with a schedule of: Mon: JIRA task work; Tue: code review; Thu: JIRA task work; Fri: misc upstream thanks -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending 17 Jan 2021

by Richard Henderson

[UM-61 TCG Maint] Refresh tcg backend constraints. Pull request for tcg constants. -- which caused reported failures. [UM-2 QEMU Maint] Refresh sve pred_desc fixes. Refresh arm alignment fixes. Misc review. [QEMU-344 ARMv8.5-MemTag] Refresh mte user-only patch set. r~

4 years, 7 months

1
0
0 0

Re: Compilation issue with Linaro ARM toolchain

by Mathieu Poirier

Adding the Linaro toolchain group mailing list. On Mon, Jan 18, 2021 at 05:49:39PM +0300, Sergey Suloev wrote: > Hi, guys, > > I am having an issue builduing kernel 5.11 (rc4) with Linaro ARM toolchain. > The issue seems to be related to CC plugins sources. > Here is my build log: https://pastebin.com/DTn7Szax. I have never seen this > before with versions 5.10 and below. > > Thank you, > Sergey > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel(a)lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

4 years, 7 months

3
2
0 0

[ACTIVITY] 11-15 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - catching up, still ~1 week late due to the numerous commits * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: committed - MVE autovectorization: movmisalign, vshl and vshr: committed. WIP on next operators. - opened 2 PRs about missed optims related to these recent patches - helping with cortex-m0 libgcc patch validation * infra: - reviewed ABE patches. - fixed abe-tests == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending Jan. 17 2021

by Alex Bennée

QEMU Device and Machine Models ([QEMU-418]) =========================================== - flurry of syncing and card creation, solidified [QEMU-414] [QEMU-414] <https://projects.linaro.org/browse/QEMU-414> VirtIO Initiative ([STR-9]) =========================== - discussion about next cycle, call on Monday [STR-9] <https://projects.linaro.org/browse/STR-9> QEMU Support for Xen ([STR-20]) =============================== - started looking at [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> [STR-20] <https://projects.linaro.org/browse/STR-20> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/9] testing/next (tags!, more travis/shippable deprecation) Message-Id: <20210113151408.27939-1-alex.bennee(a)linaro.org> - posted [PATCH v2 00/12] testing/next (tags!, shippable/travis deprecation, regression fixes, checkpatch) Message-Id: <20210114165730.31607-1-alex.bennee(a)linaro.org> - posted [PULL 00/30] testing, gdbstub and semihosting Message-Id: <20210115130828.23968-1-alex.bennee(a)linaro.org> - looks like a NetBSD regression needs to be looked at [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [1/1] ======================= Re: [PATCH v6 34/35] Auto-import Docker support files Message-Id: <1610080146-14968-1-git-send-email-tsimpson(a)quicinc.com> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-13 Wed> * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> -- Alex Bennée

4 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 15 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + code review, pullreq + fixed the "breaks a gitlab CI run" issue with the 'merge docs into a single sphinx manual' patch * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Progress with the SSE-300 model: - finished model of new timer device - updated iotkit-sysctl register block with SSE-300 specific behaviour - implemented simple dummy model of new CPU<N>_PWRCTRL register block - made sse-300 code more data-driven so it can handle sse-300 putting some of the devices at different places thanks -- PMM

4 years, 8 months

1
0
0 0

[ACTIVITY] week ending Jan. 10 2021

by Alex Bennée

QEMU Device and Machine Models ([QEMU-418]) =========================================== - pinged tsc/tle about scheduling a call for next week [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - flushed gdbstub and semihosting queues - sent pre-PR series to list [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [2/2] ======================= [PATCH V1] gdbstub: suspended state support Message-Id: <1609963815-417989-1-git-send-email-steven.sistare(a)oracle.com> [PATCH] gdbstub.c uses incorrect check for active gdb in use_gdb_syscalls Message-Id: <20201223212752.1145294-1-keithp(a)keithp.com> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v6 0/5] Enable plugin support on msys2/mingw Message-Id: <20201013002806.1447-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> -- Alex Bennée

4 years, 8 months

1
0
0 0

[ACTIVITY] 4-8 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - restarted validation after e/o year maintenance - catching up, no regression to report so far * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: movmisalign accepted, waiting for boostrap results vshl and vshr: pinged. - helping with cortex-m0 libgcc patch validation * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - reviewed ABE patches == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 8 Jan

by Peter Maydell

Progress (2 day week this week): * UM-2 [QEMU upstream maintainership] + Unsurprisingly, pretty much just catching up with email, pull requests, code review, bug reports, respins of patchsets... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + The final parts of base v8.1M and Cortex-M55 support are now in master. thanks -- PMM

4 years, 8 months

1
0
0 0

[ACTIVITY] 2 weeks ending 27 Dec 2020

by Richard Henderson

(or the 10 days preceding Christmas) [UM-61 TCG Maint] New version of tcg constants patch set. TCG backend constraints cleanup. ARM NEON host patch set. [UM-2 QEMU Maint] Fixed tcg gvec bug vs hosts without vector support. Rebase and re-send pauth impdef algorithm. Patch review: mips, riscv. gdbstub. r~

4 years, 8 months

1
0
0 0

[ACTIVITY] week ending Dec. 20 2020

by Alex Bennée

VirtIO RPMB ([STR-5]) ===================== - Continued working on Rust port of vhost-user-rpmb - Re-based and updated the [QEMU based branch] [QEMU based branch] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-rpmb-v2> QEMU Support for Xen ([STR-20]) =============================== - re-based and continued to work on Xen development environment - with my [current branch] I can now boot domU inside dom0 - also can now run qemu-aarch64 as a Dom0 PV backend [branch to clean-up and add "virt" machine] <https://github.com/stsquad/qemu/tree/xen/add-xen-virt-machine> [current branch] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Device and Machine Models ([QEMU-418]) =========================================== - created new initiative for tracking work both in and outside group - we don't want another watchdog duplication - worked on refining definition for [CPU model for QEMU] - wrote to Linaro open discussion list to canvas members requirements Message-Id: <878saesi0x.fsf(a)linaro.org> [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> [CPU model for QEMU] <https://projects.linaro.org/browse/QEMU-414> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] configure: add --without-default-features Message-Id: <20201202153827.17446-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/8] testing/next (without-features, gitlab, python) Message-Id: <20201210190417.31673-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/6] gdbstub (auxv, tests, cleanup) Message-Id: <20201214153012.12723-6-alex.bennee(a)linaro.org> - posted [PULL 00/11] testing and configure updates Message-Id: <20201216164827.24457-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/11] testing and configure updates Message-Id: <20201217094330.17400-1-alex.bennee(a)linaro.org> - still stalled due to some stale build issues (unable to repro) - posted [PATCH v2 0/9] gdbstub/next (cleanups, softmmu, SVE) Message-Id: <20201218112707.28348-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Other work ========== - bootstrapped gitdm metadata for GCC project - planning for Stratos/QEMU Next Cycle - declared bankruptcy on my review queue, flushed most of it Completed Reviews [5/5] ======================= [PATCH v4 00/11] hvf: Implement Apple Silicon Support Message-Id: <20201203234857.21051-2-agraf(a)csgraf.de> [RFC v9 00/22] i386 cleanup Message-Id: <20201208194839.31305-1-cfontana(a)suse.de> [PATCH 0/3] hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot Message-Id: <1607937538-69471-1-git-send-email-bmeng.cn(a)gmail.com> [PATCH 0/2] Fix test-char reference counting bug Message-Id: <20201215224133.3545901-1-ehabkost(a)redhat.com> [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Message-Id: <20201125213617.2496935-1-keithp(a)keithp.com> Absences ======== - Back on Jan 5th, Happy Christmas Current Review Queue ==================== * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v6 0/5] Enable plugin support on msys2/mingw Message-Id: <20201013002806.1447-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> -- Alex Bennée

4 years, 8 months

1
0
0 0

[ACTIVITY] 14-18 December 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures, trunk build broken several times * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: committed veor, vbic, vmvn and vneg. Sent movmisalign, vshl and vshr patches. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - reviewed ABE patches == Next == Holidays until Jan 4th, 2021 == Future == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 8 months

1
0
0 0

[ACTIVITY] 7 - 11 Dec 2020

by Prathamesh Kulkarni

== This Week == * PR97872 (missed optimization for comparison on vectors) - Committed fix to trunk * PR97903 (Lower a & b != 0 to vtst) - In progress * PR66791 (Replace builtins by vector extensions in arm_neon.h intrinsics) - Committed patches for vmvn - Patches approved for vcreate, vneg, vclt, vcgt. == Next Week == - PR97903 - PR66791: Commit approved patches and work on new intrinsics

4 years, 9 months

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perf issue: etm traces are dumped to the wrong AUX buffer

by Zied Guermazi

hi I am using perf syscall to collect etm traces for btraces implementation in GDB running on Linux kernel 5.9.1 on a cortex A7. in this test case, I am debugging a multi-threaded process (2 pthreads). For each thread, GDB is calling the sys call perf_event_open and gives the corresponding thread ptid.lwp as argument. for each syscall, the AUX buffer is mmap(ped) to a dedicated memory. this is working for almost all test cases I have, except this one, where it has 50% failure rate when executed manually. 90% failure rate when executed from a script. the source code for debugged program is listed below. /* This testcase is part of GDB, the GNU debugger. Copyright 2013-2019 Free Software Foundation, Inc. Contributed by Intel Corp. <markus.t.metzger(a)intel.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <pthread.h> static pthread_barrier_t barrier; static int global; static void * test(void *arg) { pthread_barrier_wait(&barrier); global= 42; /* bp.1 */ pthread_barrier_wait(&barrier); global= 42; /* bp.2 */ return arg; } int main (void) { pthread_t th; pthread_barrier_init(&barrier, NULL, 2); pthread_create(&th, NULL, test, NULL); test(NULL); pthread_join(th, NULL); pthread_barrier_destroy(&barrier); return 0; /* bp.3 */ } in this test case, a breakpoint is set at the line containing the comment /* bp.1 */ , and we start collecting traces. a second breakpoint is set at the line containing the comment /* bp.2 */, and we analyze collected traces. in a successful testcase we get both threads traces in dedicated buffers thread 1 [Switching to thread 1 (Thread 0xb6ff9ca0 (LWP 8813))] #0test (arg=0x0) at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 126 instructions in 15 functions (0 gaps) for thread 1 (Thread 0xb6ff9ca0 (LWP 8813)). (gdb) record function-call-history /ilc 1 test inst 1,9 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 2 pthread_barrier_wait@plt inst 10,12 at 3 pthread_barrier_wait inst 13,32 at 4 __aeabi_uidivmod inst 33,36 at 5 __udivsi3 inst 37,39 at 6 __udivsi3 inst 40,48 at 7 __aeabi_uidivmod inst 49,52 at 8 pthread_barrier_wait inst 53,77 at 9 __libc_do_syscall inst 78,80 at 10 pthread_barrier_wait inst 81,102 at 11 __aeabi_uidivmod inst 103,106 at 12 __udivsi3 inst 107,109 at 13 __udivsi3 inst 110,118 at 14 __aeabi_uidivmod inst 119,122 at 15 pthread_barrier_wait inst 123,126 at here is a log of the collected trace generic elements cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION thread 2 [Switching to thread 2 (Thread 0xb6ea7460 (LWP 8816))] #0test (arg=0x0) at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 150 instructions in 20 functions (0 gaps) for thread 2 (Thread 0xb6ea7460 (LWP 8816)). (gdb) record function-call-history /ilc 1 test inst 1,9 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 2 pthread_barrier_wait@plt inst 10,12 at 3 pthread_barrier_wait inst 13,32 at 4 __aeabi_uidivmod inst 33,36 at 5 __udivsi3 inst 37,39 at 6 __udivsi3 inst 40,48 at 7 __aeabi_uidivmod inst 49,52 at 8 pthread_barrier_wait inst 53,66 at 9 __aeabi_uidivmod inst 67,70 at 10 __udivsi3 inst 71,73 at 11 __udivsi3 inst 74,82 at 12 __aeabi_uidivmod inst 83,86 at 13 pthread_barrier_wait inst 87,103 at 14 __libc_do_syscall inst 104,106 at 15 pthread_barrier_wait inst 107,126 at 16 __aeabi_uidivmod inst 127,130 at 17 __udivsi3 inst 131,133 at 18 __udivsi3 inst 134,142 at 19 __aeabi_uidivmod inst 143,146 at 20 pthread_barrier_wait inst 147,150 at here is a log of the collected trace generic elements cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION in the failing test we got all traces in one buffer, the second one is empty (gdb) thread 1 [Switching to thread 1 (Thread 0xb6ff9ca0 (LWP 8826))] #0 test (arg=0x0) at /home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 276 instructions in 36 functions (0 gaps) for thread 1 (Thread 0xb6ff9ca0 (LWP 8826)). (gdb) record function-call-history /ilc 1 1 test inst 1,9 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 2 pthread_barrier_wait@plt inst 10,12 at 3 pthread_barrier_wait inst 13,32 at 4 __aeabi_uidivmod inst 33,36 at 5 __udivsi3 inst 37,39 at 6 __udivsi3 inst 40,48 at 7 __aeabi_uidivmod inst 49,52 at 8 pthread_barrier_wait inst 53,77 at 9 __libc_do_syscall inst 78,80 at 10 test inst 81,88 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 11 pthread_barrier_wait@plt inst 89,91 at 12 pthread_barrier_wait inst 92,111 at 13 __aeabi_uidivmod inst 112,115 at 14 __udivsi3 inst 116,118 at 15 __udivsi3 inst 119,127 at 16 __aeabi_uidivmod inst 128,131 at 17 pthread_barrier_wait inst 132,145 at 18 __aeabi_uidivmod inst 146,149 at 19 __udivsi3 inst 150,152 at 20 __udivsi3 inst 153,161 at 21 __aeabi_uidivmod inst 162,165 at 22 pthread_barrier_wait inst 166,182 at 23 __libc_do_syscall inst 183,185 at 24 pthread_barrier_wait inst 186,205 at 25 __aeabi_uidivmod inst 206,209 at 26 __udivsi3 inst 210,212 at 27 __udivsi3 inst 213,221 at 28 __aeabi_uidivmod inst 222,225 at 29 pthread_barrier_wait inst 226,229 at 30 test inst 230,230 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 31 pthread_barrier_wait inst 231,252 at 32 __aeabi_uidivmod inst 253,256 at 33 __udivsi3 inst 257,259 at 34 __udivsi3 inst 260,268 at 35 __aeabi_uidivmod inst 269,272 at 36 pthread_barrier_wait inst 273,276 at here is a log of the collected trace generic elements cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION (gdb) thread 2 [Switching to thread 2 (Thread 0xb6ea7460 (LWP 8827))] #0test (arg=0x0) at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 0 instructions in 0 functions (0 gaps) for thread 2 (Thread 0xb6ea7460 (LWP 8827)). (gdb) record function-call-history /ilc 1 No trace. (gdb) is there any known issues for calling perf_event_open twice for two different threads? is there any known issues for flushing traces when a switch between two threads takes place? is there any known issue for tracing threads when switching happens due to a pthread_barrier_wait? do you have any other hint to provide here? Kind regards Zied Guermazi

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending 13 Dec 2020

by Richard Henderson

[UM-2] New revision on arm alignment patch set. Patch review: mips and i386 cleanups. [UM-61] New revision on splitwx patch set. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 11 Dec

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + sent out a pullreq for 6.0, and did a bunch more patch review + sent out a respin of the "build one manual, not five" RFC I sent last month; nobody objected to the RFC so this time around it is a proper PATCH + had a brief scan through the GIC architecture specification to look at what extra GICv4 and GICv4.1 add (the big thing is that the ITS is now mandatory; QEMU doesn't emulate that yet) * VIRT-364 [QEMU support for ARMv8.1-M extensions] + SSE-300 timer device model more or less functionally-complete (though untested). I ran into some issues with QEMU's Clock APIs that I needed to fix in the process -- sent a patchseries trying to address those. + Got most of the outstanding v8.1M patches into master; sent a small patch series with respins of the last 4 or so patches that needed more work thanks -- PMM

4 years, 9 months

1
0
0 0

[ACTIVITY] 7-11 December 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: committed vand and vorr patches. Sent updated versions of veor, vbic and vmvn. vshr and vshl need some refactorization with Neon versions, clarified the best way to go with Arm maintainers. - PR97875 (suboptimal vectorization on MVE): investigation shows that movmisalign patterns are missing for MVE. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - debugging issues with our docker containers - looking at ABE patches * misc: - provided feedback to Arm's partner wrt Intrinsics documentation == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending 6 Dec 2020

by Richard Henderson

[UM-59] More work on softfloat rem; f128 still needs work. [UM-2] Patch review, notably v8.1m, mips cleanups, arc port. Revisions to arm alignment patch set. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] 30 November-4 December 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: handling feedback on(vand, vorr, veor, vshr, vshl). WIP vmvn, vbic. Found further vectorization issues. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers - looking at ABE patches == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 9 months

1
0
0 0

[ACTIVITY] 30 Nov - 4 Dec 2020

by Prathamesh Kulkarni

== This Week == * PR97872 (missed optimization on less-than vector comparison) - Upstream discussion with Richard, patch close to being approved. - Causes a regression for pr78102.c. * PR66791 (replace builtins by vector extensions in arm_neon.h intrinsics) - Submitted patches for vmvn, vcreate, vneg. - Kyrill approved patch for vmvn, and asked to remove corresponding builtins from being created in backend. == Next Week == - Hopefully commit fix for PR97872 - Continue with PR66791 - Start looking at another vectorization PR

4 years, 9 months

1
0
0 0

Timeout tests timing out

by David Blaikie

The clang-cmake-armv8-lld (linaro-toolchain owners) buildbot is timing out trying to run some timeout tests (Dan Liew author): Pass: http://lab.llvm.org:8011/builders/clang-cmake-armv8-lld/builds/5672 Fail: http://lab.llvm.org:8011/builders/clang-cmake-armv8-lld/builds/5673 Is there anything we can do to the buildbot? Or the tests? (bump up the time limits or maybe remove the tests as unreliable?)

4 years, 9 months

5
14
0 0

[ACTIVITY] week ending Dec. 6 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - started reviewing latest EPAM IOREQ/VirtIO patches Message-Id: <1606732298-22107-1-git-send-email-olekstysh(a)gmail.com> VirtIO RPMB ([STR-5]) ===================== - Continued working on Rust port of vhost-user-rpmb VirtIO Portability Demo ([STR-13]) ================================== - done and closed QEMU Support for Xen ([STR-20]) =============================== - re-based and continued to work on Xen development environment - with my [current branch] I can now boot domU inside dom0 - also can now run qemu-aarch64 as a Dom0 PV backend [current branch] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Device and Machine Models ([QEMU-418]) =========================================== - created new initiative for tracking work both in and outside group - we don't want another watchdog duplication - worked on refining definition for [CPU model for QEMU] - wrote to Linaro open discussion list to canvas members requirements Message-Id: <878saesi0x.fsf(a)linaro.org> [CPU model for QEMU] <https://projects.linaro.org/browse/QEMU-414> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] configure: add --without-default-features Message-Id: <20201202153827.17446-1-alex.bennee(a)linaro.org> Other work ========== - bootstrapped gitdm metadata for GCC project Completed Reviews [1/1] ======================= [PATCH v4 00/11] hvf: Implement Apple Silicon Support Message-Id: <20201203234857.21051-2-agraf(a)csgraf.de> -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 3 Dec

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Cut down the patch review queue a bit ready for 6.0 development cycle * VIRT-364 [QEMU support for ARMv8.1-M extensions] + started working on modelling of the SSE-300. Have done some of the easy "ID registers are different" stuff and started on modelling a new timer device that isn't in the SSE-200. thanks -- PMM

4 years, 9 months

1
0
0 0

[ACTIVITY] 23 - 27 Nov 2020

by Prathamesh Kulkarni

== This Week == * PR66791 (Replace __builtins_* in arm_neon.h intrinsics by C vector extensions) - Submitted patch for vmvn, waiting for feedback. - Created and tested patches for vcreate and vneg. * PR97849 (segfault in ifcvt with -march=armv8.2-a+sve) - Committed fix to trunk. == Next Week == - PR97872 - Continue with PR66791

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Nov. 29 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Raised [STR-21] to cover some Zephyr work - Synced with EPAM and ARM to discuss their work and direction [STR-21] <https://projects.linaro.org/browse/STR-21> VirtIO RPMB ([STR-5]) ===================== - Started investigating Rust port of vhost-user-rpmb [STR-5] <https://projects.linaro.org/browse/STR-5> VirtIO Portability Demo ([STR-13]) ================================== - delivered gold copy for talk at [OSS and ALS Japan 2020] - synced with ALS guys on talk [OSS and ALS Japan 2020] <https://sched.co/f2Yk> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 for 5.1 00/10] various fixes (CI, Xen, plugins) Message-Id: <20201110192316.26397-1-alex.bennee(a)linaro.org> - posted [[PULL for 5.2-rc3 0/7] various CI cleanups (scripts, avocado, gitlab)] [UM-2] <https://projects.linaro.org/browse/UM-2> [[PULL for 5.2-rc3 0/7] various CI cleanups (scripts, avocado, gitlab)] <mu4e:i:20201123112518.13425-1-alex.bennee@linaro.org> Completed Reviews [4/4] ======================= [for-5.2 0/9] docs: Move orphan top-level .rst files into manuals Message-Id: <20201112144041.32278-1-peter.maydell(a)linaro.org> [PATCH v3 00/41] Mirror map JIT memory for TCG Message-Id: <20201106032921.600200-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2020-11-14 Sat 11:52] Had a brief look over, waiting for next revision Added: <2020-11-06 Fri> [PATCH v2 00/13] Remove GCC < 4.8 checks Message-Id: <20201126112915.525285-1-marcandre.lureau(a)redhat.com> [PATCH] gdbstub: Correct misparsing of vCont C/S requests Message-Id: <20201121210342.10089-1-peter.maydell(a)linaro.org> Absences ======== - Illness Current Review Queue ==================== * [PATCH v2 0/4] linux/sparc: more get/set_context fixes Message-Id: <20201106152738.26026-1-peter.maydell(a)linaro.org> Added: <2020-11-06 Fri> * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] 23-27 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: sent a few patches (vand, vorr, veor, vshr, vshl). WIP vmvn, vbic * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers - looking at ABE patches == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements Reply Forward

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 27 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Cut rc3; there were a few last-minute bugfixes that came in so we will need an rc4 * VIRT-364 [QEMU support for ARMv8.1-M extensions] + read through the SSE-300 TRM and identified the required work to model it (it's similar to the SSE-200 which we already have but with various minor changes and a couple of new devices) * wisdom tooth extracted \o/ thanks -- PMM

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending 22 Nov 2020

by Richard Henderson

[UM-59 # FPU Emulation Maintainership ] Lots more work converting to FloatParts. Almost all floatx80 now converted. Still to do are log2 and rem/mod for full conversion. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] 16-20 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: more patterns updates (vshl, vshr). WIP * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 20 Nov

by Peter Maydell

Generally productive week rather derailed at the end by a sudden onset of toothache Thursday night :-/ Progress: * UM-2 [QEMU upstream maintainership] + usual release cycle work * VIRT-364 [QEMU support for ARMv8.1-M extensions] + Worked through the remaining set of identified new features for v8.1M implementing them. + Fixed a handful of pre-existing bugs along the way. + Sent out a patchset with all this plus the "Implement (no-MVE) Cortex-M55 model" patch on top, since we now have all the pieces needed for it. + The next and final piece of work here is to implement a model of a board that uses the Cortex-M55. -- PMM

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Nov. 15 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO Portability Demo ([STR-13]) ================================== - recorded AGL demo videos (KVM, TCG Xen Dom0 with and without Xen aware kernel) - recorded [preview version of talk] [STR-13] <https://projects.linaro.org/browse/STR-13> [preview version of talk] <https://fileserver.linaro.org/s/wgt2AAj9rxYqJop> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 for 5.1 00/10] various fixes (CI, Xen, plugins) Message-Id: <20201110192316.26397-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [2/2] ======================= [for-5.2 0/9] docs: Move orphan top-level .rst files into manuals Message-Id: <20201112144041.32278-1-peter.maydell(a)linaro.org> [PATCH v3 00/41] Mirror map JIT memory for TCG Message-Id: <20201106032921.600200-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2020-11-14 Sat 11:52] Had a brief look over, waiting for next revision Added: <2020-11-06 Fri> Current Review Queue ==================== * [PATCH v2 0/4] linux/sparc: more get/set_context fixes Message-Id: <20201106152738.26026-1-peter.maydell(a)linaro.org> Added: <2020-11-06 Fri> * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> -- Alex Bennée

4 years, 10 months

1
0
0 0

[ACTIVITY] 9-13 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: started patterns updates (vand, vorr, veor) * Misc - investigated LP bug 1747966 (https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966) there is a fix in binutils upstream: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0e6a3f07f50723d18… * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 13 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + investigated and fixed a bug that had been lurking unfixed in our n800 models for years which prevented guest boot of Maemo images + docs tidyup: moved "orphan" rST documents into the manual structure so they actually get shipped to users + usual release candidate related work * VIRT-364 [QEMU support for ARMv8.1-M extensions] + working on handling for new FP system registers; the FPCXT regs in particular have some tricky corners... thanks -- PMM

4 years, 10 months

1
0
0 0

[ACTIVITY] week ending 8 Nov 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] * Fix neon register offsets big-endian hosts. * Fix neon register offsets for VTBL. * Working through a 4th revision of float128_muladd. * Random patch review and bug fixes. [UM-61 # TCG Core Maintainership ] * Two revisions of split w^x patch set. r~

4 years, 10 months

1
0
0 0

Demo of using etm traces on arm for instructions and functions recording and reverse debugging

by Zied Guermazi

hi all, to demonstrate extending gdb to use etm traces for implementing btrace on arm processors, I have made this video available on youtube https://youtu.be/ptKbJRNUqUI users can then have access to process record and replay, on instructions and functions level (https://sourceware.org/gdb/current/onlinedocs/gdb/Process-Record-and-Replay…) and reverse debugging(https://www.gnu.org/software/gdb/news/reversible.html) we have all functionalities available for intel PT except tracing multi-threaded applications. In this demo I have "reconstructed" the cspr register to enable setting breakpoints in reverse debugging. it is still dirty (adds arm specific register to an architecture agnostic structure) but it shows that it works when implemented properly Kind Regards Zied Guermazi

4 years, 10 months

1
0
0 0

[ACTIVITY] 2-6 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - PR96767: patch committed - PR96770: patch committed - patch for C++ thunks with -mpure-code and cortex-m0: patches committed - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: handling feedback * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 10 months

1
0
0 0

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