- linaro-toolchain - lists.linaro.org

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/llvm-release-arm-spec2k6-Os - Build # 15 - Successful!

by ci_notify＠linaro.org

Successfully identified regression in *llvm* in CI configuration tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-Os. So far, this commit has regressed CI configurations: - tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-Os Culprit: <cut> commit 3a2b05f9fe74fcf9560632cf2695058d47d8683b Author: Evgeniy Brevnov <ybrevnov(a)azul.com> Date: Fri Jul 24 18:57:10 2020 +0700 [BPI][NFC] Consolidate code to deal with SCCs under a dedicated data structure. In order to facilitate review of D79485 here is a small NFC change which restructures code around handling of SCCs in BPI. Reviewed By: davidxl Differential Revision: https://reviews.llvm.org/D84514 </cut> Results regressed to (for first_bad == 3a2b05f9fe74fcf9560632cf2695058d47d8683b) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: -5 # build_llvm true: -3 # true: 0 # benchmark -Os_mthumb -- artifacts/build-3a2b05f9fe74fcf9560632cf2695058d47d8683b/results_id: 1 # 401.bzip2,bzip2_base.default regressed by 104 from (for last_good == 7294ca3f6ecacd05a197bbf0637e10afcb99b6d6) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: -5 # build_llvm true: -3 # true: 0 # benchmark -Os_mthumb -- artifacts/build-7294ca3f6ecacd05a197bbf0637e10afcb99b6d6/results_id: 1 Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… Results ID of last_good: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-release-arm-spec2k6-Os/699 Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… Results ID of first_bad: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-release-arm-spec2k6-Os/688 Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… Configuration details: Reproduce builds: <cut> mkdir investigate-llvm-3a2b05f9fe74fcf9560632cf2695058d47d8683b cd investigate-llvm-3a2b05f9fe74fcf9560632cf2695058d47d8683b git clone https://git.linaro.org/toolchain/jenkins-scripts mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh cd llvm # Reproduce first_bad build git checkout --detach 3a2b05f9fe74fcf9560632cf2695058d47d8683b ../artifacts/test.sh # Reproduce last_good build git checkout --detach 7294ca3f6ecacd05a197bbf0637e10afcb99b6d6 ../artifacts/test.sh cd .. </cut> History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… Build log: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… Full commit (up to 1000 lines): <cut> commit 3a2b05f9fe74fcf9560632cf2695058d47d8683b Author: Evgeniy Brevnov <ybrevnov(a)azul.com> Date: Fri Jul 24 18:57:10 2020 +0700 [BPI][NFC] Consolidate code to deal with SCCs under a dedicated data structure. In order to facilitate review of D79485 here is a small NFC change which restructures code around handling of SCCs in BPI. Reviewed By: davidxl Differential Revision: https://reviews.llvm.org/D84514 --- llvm/include/llvm/Analysis/BranchProbabilityInfo.h | 71 ++++++++- llvm/lib/Analysis/BranchProbabilityInfo.cpp | 164 +++++++++++++-------- 2 files changed, 169 insertions(+), 66 deletions(-) diff --git a/llvm/include/llvm/Analysis/BranchProbabilityInfo.h b/llvm/include/llvm/Analysis/BranchProbabilityInfo.h index 3e72afba36c3..7feb5b625938 100644 --- a/llvm/include/llvm/Analysis/BranchProbabilityInfo.h +++ b/llvm/include/llvm/Analysis/BranchProbabilityInfo.h @@ -151,13 +151,66 @@ public: /// Forget analysis results for the given basic block. void eraseBlock(const BasicBlock *BB); - // Use to track SCCs for handling irreducible loops. - using SccMap = DenseMap<const BasicBlock *, int>; - using SccHeaderMap = DenseMap<const BasicBlock *, bool>; - using SccHeaderMaps = std::vector<SccHeaderMap>; - struct SccInfo { + class SccInfo { + // Enum of types to classify basic blocks in SCC. Basic block belonging to + // SCC is 'Inner' until it is either 'Header' or 'Exiting'. Note that a + // basic block can be 'Header' and 'Exiting' at the same time. + enum SccBlockType { + Inner = 0x0, + Header = 0x1, + Exiting = 0x2, + }; + // Map of basic blocks to SCC IDs they belong to. If basic block doesn't + // belong to any SCC it is not in the map. + using SccMap = DenseMap<const BasicBlock *, int>; + // Each basic block in SCC is attributed with one or several types from + // SccBlockType. Map value has uint32_t type (instead of SccBlockType) + // since basic block may be for example "Header" and "Exiting" at the same + // time and we need to be able to keep more than one value from + // SccBlockType. + using SccBlockTypeMap = DenseMap<const BasicBlock *, uint32_t>; + // Vector containing classification of basic blocks for all SCCs where i'th + // vector element corresponds to SCC with ID equal to i. + using SccBlockTypeMaps = std::vector<SccBlockTypeMap>; + SccMap SccNums; - SccHeaderMaps SccHeaders; + SccBlockTypeMaps SccBlocks; + + public: + explicit SccInfo(const Function &F); + + /// If \p BB belongs to some SCC then ID of that SCC is returned, otherwise + /// -1 is returned. If \p BB belongs to more than one SCC at the same time + /// result is undefined. + int getSCCNum(const BasicBlock *BB) const; + /// Returns true if \p BB is a 'header' block in SCC with \p SccNum ID, + /// false otherwise. + bool isSCCHeader(const BasicBlock *BB, int SccNum) const { + return getSccBlockType(BB, SccNum) & Header; + } + /// Returns true if \p BB is an 'exiting' block in SCC with \p SccNum ID, + /// false otherwise. + bool isSCCExitingBlock(const BasicBlock *BB, int SccNum) const { + return getSccBlockType(BB, SccNum) & Exiting; + } + /// Fills in \p Enters vector with all such blocks that don't belong to + /// SCC with \p SccNum ID but there is an edge to a block belonging to the + /// SCC. + void getSccEnterBlocks(int SccNum, + SmallVectorImpl<BasicBlock *> &Enters) const; + /// Fills in \p Exits vector with all such blocks that don't belong to + /// SCC with \p SccNum ID but there is an edge from a block belonging to the + /// SCC. + void getSccExitBlocks(int SccNum, + SmallVectorImpl<BasicBlock *> &Exits) const; + + private: + /// Returns \p BB's type according to classification given by SccBlockType + /// enum. Please note that \p BB must belong to SSC with \p SccNum ID. + uint32_t getSccBlockType(const BasicBlock *BB, int SccNum) const; + /// Calculates \p BB's type and stores it in internal data structures for + /// future use. Please note that \p BB must belong to SSC with \p SccNum ID. + void calculateSccBlockType(const BasicBlock *BB, int SccNum); }; private: @@ -196,6 +249,9 @@ private: /// Track the last function we run over for printing. const Function *LastF = nullptr; + /// Keeps information about all SCCs in a function. + std::unique_ptr<const SccInfo> SccI; + /// Track the set of blocks directly succeeded by a returning block. SmallPtrSet<const BasicBlock *, 16> PostDominatedByUnreachable; @@ -210,8 +266,7 @@ private: bool calcMetadataWeights(const BasicBlock *BB); bool calcColdCallHeuristics(const BasicBlock *BB); bool calcPointerHeuristics(const BasicBlock *BB); - bool calcLoopBranchHeuristics(const BasicBlock *BB, const LoopInfo &LI, - SccInfo &SccI); + bool calcLoopBranchHeuristics(const BasicBlock *BB, const LoopInfo &LI); bool calcZeroHeuristics(const BasicBlock *BB, const TargetLibraryInfo *TLI); bool calcFloatingPointHeuristics(const BasicBlock *BB); bool calcInvokeHeuristics(const BasicBlock *BB); diff --git a/llvm/lib/Analysis/BranchProbabilityInfo.cpp b/llvm/lib/Analysis/BranchProbabilityInfo.cpp index a396b5ad21c6..195fc69d9601 100644 --- a/llvm/lib/Analysis/BranchProbabilityInfo.cpp +++ b/llvm/lib/Analysis/BranchProbabilityInfo.cpp @@ -148,6 +148,105 @@ static const uint32_t IH_TAKEN_WEIGHT = 1024 * 1024 - 1; /// instruction. This is essentially never taken. static const uint32_t IH_NONTAKEN_WEIGHT = 1; +BranchProbabilityInfo::SccInfo::SccInfo(const Function &F) { + // Record SCC numbers of blocks in the CFG to identify irreducible loops. + // FIXME: We could only calculate this if the CFG is known to be irreducible + // (perhaps cache this info in LoopInfo if we can easily calculate it there?). + int SccNum = 0; + for (scc_iterator<const Function *> It = scc_begin(&F); !It.isAtEnd(); + ++It, ++SccNum) { + // Ignore single-block SCCs since they either aren't loops or LoopInfo will + // catch them. + const std::vector<const BasicBlock *> &Scc = *It; + if (Scc.size() == 1) + continue; + + LLVM_DEBUG(dbgs() << "BPI: SCC " << SccNum << ":"); + for (const auto *BB : Scc) { + LLVM_DEBUG(dbgs() << " " << BB->getName()); + SccNums[BB] = SccNum; + calculateSccBlockType(BB, SccNum); + } + LLVM_DEBUG(dbgs() << "\n"); + } +} + +int BranchProbabilityInfo::SccInfo::getSCCNum(const BasicBlock *BB) const { + auto SccIt = SccNums.find(BB); + if (SccIt == SccNums.end()) + return -1; + return SccIt->second; +} + +void BranchProbabilityInfo::SccInfo::getSccEnterBlocks( + int SccNum, SmallVectorImpl<BasicBlock *> &Enters) const { + + for (auto MapIt : SccBlocks[SccNum]) { + const auto *BB = MapIt.first; + if (isSCCHeader(BB, SccNum)) + for (const auto *Pred : predecessors(BB)) + if (getSCCNum(Pred) != SccNum) + Enters.push_back(const_cast<BasicBlock *>(BB)); + } +} + +void BranchProbabilityInfo::SccInfo::getSccExitBlocks( + int SccNum, SmallVectorImpl<BasicBlock *> &Exits) const { + for (auto MapIt : SccBlocks[SccNum]) { + const auto *BB = MapIt.first; + if (isSCCExitingBlock(BB, SccNum)) + for (const auto *Succ : successors(BB)) + if (getSCCNum(Succ) != SccNum) + Exits.push_back(const_cast<BasicBlock *>(BB)); + } +} + +uint32_t BranchProbabilityInfo::SccInfo::getSccBlockType(const BasicBlock *BB, + int SccNum) const { + assert(getSCCNum(BB) == SccNum); + + assert(SccBlocks.size() > static_cast<unsigned>(SccNum) && "Unknown SCC"); + const auto &SccBlockTypes = SccBlocks[SccNum]; + + auto It = SccBlockTypes.find(BB); + if (It != SccBlockTypes.end()) { + return It->second; + } + return Inner; +} + +void BranchProbabilityInfo::SccInfo::calculateSccBlockType(const BasicBlock *BB, + int SccNum) { + assert(getSCCNum(BB) == SccNum); + uint32_t BlockType = Inner; + + if (llvm::any_of(make_range(pred_begin(BB), pred_end(BB)), + [&](const BasicBlock *Pred) { + // Consider any block that is an entry point to the SCC as + // a header. + return getSCCNum(Pred) != SccNum; + })) + BlockType |= Header; + + if (llvm::any_of( + make_range(succ_begin(BB), succ_end(BB)), + [&](const BasicBlock *Succ) { return getSCCNum(Succ) != SccNum; })) + BlockType |= Exiting; + + // Lazily compute the set of headers for a given SCC and cache the results + // in the SccHeaderMap. + if (SccBlocks.size() <= static_cast<unsigned>(SccNum)) + SccBlocks.resize(SccNum + 1); + auto &SccBlockTypes = SccBlocks[SccNum]; + + if (BlockType != Inner) { + bool IsInserted; + std::tie(std::ignore, IsInserted) = + SccBlockTypes.insert(std::make_pair(BB, BlockType)); + assert(IsInserted && "Duplicated block in SCC"); + } +} + static void UpdatePDTWorklist(const BasicBlock *BB, PostDominatorTree *PDT, SmallVectorImpl<const BasicBlock *> &WorkList, SmallPtrSetImpl<const BasicBlock *> &TargetSet) { @@ -511,38 +610,6 @@ bool BranchProbabilityInfo::calcPointerHeuristics(const BasicBlock *BB) { return true; } -static int getSCCNum(const BasicBlock *BB, - const BranchProbabilityInfo::SccInfo &SccI) { - auto SccIt = SccI.SccNums.find(BB); - if (SccIt == SccI.SccNums.end()) - return -1; - return SccIt->second; -} - -// Consider any block that is an entry point to the SCC as a header. -static bool isSCCHeader(const BasicBlock *BB, int SccNum, - BranchProbabilityInfo::SccInfo &SccI) { - assert(getSCCNum(BB, SccI) == SccNum); - - // Lazily compute the set of headers for a given SCC and cache the results - // in the SccHeaderMap. - if (SccI.SccHeaders.size() <= static_cast<unsigned>(SccNum)) - SccI.SccHeaders.resize(SccNum + 1); - auto &HeaderMap = SccI.SccHeaders[SccNum]; - bool Inserted; - BranchProbabilityInfo::SccHeaderMap::iterator HeaderMapIt; - std::tie(HeaderMapIt, Inserted) = HeaderMap.insert(std::make_pair(BB, false)); - if (Inserted) { - bool IsHeader = llvm::any_of(make_range(pred_begin(BB), pred_end(BB)), - [&](const BasicBlock *Pred) { - return getSCCNum(Pred, SccI) != SccNum; - }); - HeaderMapIt->second = IsHeader; - return IsHeader; - } else - return HeaderMapIt->second; -} - // Compute the unlikely successors to the block BB in the loop L, specifically // those that are unlikely because this is a loop, and add them to the // UnlikelyBlocks set. @@ -653,12 +720,11 @@ computeUnlikelySuccessors(const BasicBlock *BB, Loop *L, // Calculate Edge Weights using "Loop Branch Heuristics". Predict backedges // as taken, exiting edges as not-taken. bool BranchProbabilityInfo::calcLoopBranchHeuristics(const BasicBlock *BB, - const LoopInfo &LI, - SccInfo &SccI) { + const LoopInfo &LI) { int SccNum; Loop *L = LI.getLoopFor(BB); if (!L) { - SccNum = getSCCNum(BB, SccI); + SccNum = SccI->getSCCNum(BB); if (SccNum < 0) return false; } @@ -685,9 +751,9 @@ bool BranchProbabilityInfo::calcLoopBranchHeuristics(const BasicBlock *BB, else InEdges.push_back(I.getSuccessorIndex()); } else { - if (getSCCNum(*I, SccI) != SccNum) + if (SccI->getSCCNum(*I) != SccNum) ExitingEdges.push_back(I.getSuccessorIndex()); - else if (isSCCHeader(*I, SccNum, SccI)) + else if (SccI->isSCCHeader(*I, SccNum)) BackEdges.push_back(I.getSuccessorIndex()); else InEdges.push_back(I.getSuccessorIndex()); @@ -1072,26 +1138,7 @@ void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI, assert(PostDominatedByUnreachable.empty()); assert(PostDominatedByColdCall.empty()); - // Record SCC numbers of blocks in the CFG to identify irreducible loops. - // FIXME: We could only calculate this if the CFG is known to be irreducible - // (perhaps cache this info in LoopInfo if we can easily calculate it there?). - int SccNum = 0; - SccInfo SccI; - for (scc_iterator<const Function *> It = scc_begin(&F); !It.isAtEnd(); - ++It, ++SccNum) { - // Ignore single-block SCCs since they either aren't loops or LoopInfo will - // catch them. - const std::vector<const BasicBlock *> &Scc = *It; - if (Scc.size() == 1) - continue; - - LLVM_DEBUG(dbgs() << "BPI: SCC " << SccNum << ":"); - for (auto *BB : Scc) { - LLVM_DEBUG(dbgs() << " " << BB->getName()); - SccI.SccNums[BB] = SccNum; - } - LLVM_DEBUG(dbgs() << "\n"); - } + SccI = std::make_unique<SccInfo>(F); std::unique_ptr<PostDominatorTree> PDTPtr; @@ -1119,7 +1166,7 @@ void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI, continue; if (calcColdCallHeuristics(BB)) continue; - if (calcLoopBranchHeuristics(BB, LI, SccI)) + if (calcLoopBranchHeuristics(BB, LI)) continue; if (calcPointerHeuristics(BB)) continue; @@ -1131,6 +1178,7 @@ void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI, PostDominatedByUnreachable.clear(); PostDominatedByColdCall.clear(); + SccI.release(); if (PrintBranchProb && (PrintBranchProbFuncName.empty() || </cut>

4 years, 5 months

1
0
0 0

Binutils help? Aarch64 PE/COFF support to enable UEFI Secure Boot

by Steve McIntyre

Hi folks, I'm hoping that I might be able to get some development help with binutils for aarch64... I'm maintaining the UEFI Secure Boot stack in Debian (shim etc.), including for arm64/aarch64 (as I wanted to make that work too!). UEFI binaries are awkward for those of used to the Linux and ELF world - they're PE/COFF format with different calling conventions to match the Microsoft world. But we've made things work. On x86 platforms, the shim build process uses objcopy --target=efi-app-$(ARCH) to produce the final output binaries. We've never had similar support for the aarch64 platform, and instead somebody came up with a method using locally-hacked linker script and "-O binary" to generate the output binaries. That's worked well enough for a while, but it's been annoying for various reasons (particularly debugging problems). *However*, recently for security reasons we've tweaked the layout of Secure Boot binaries [1] and this has caused lots of problems. The older hacks to hand-build the right sections etc. needed significant extra work, and we're still dealing with awkward bugs related to this. Based ont these problems, I recently had to make the painful decision to drop support for arm64 SB in Debian. I know that other distributions are feeling similar pain. :-( Rather than continuing to hack on things, I think it's (way past) time that we did things correctly! We need aarch64 binary format support in binutils so we can just use it like we do on x86. AFAICS, there is already a bug open asking for this from last year [2]. Could I please prevail on some friendly neighourhood aarch64 toolchain engineer to help with that? Thanks for considering, Steve [1] https://github.com/rhboot/shim/blob/main/SBAT.md [2] https://sourceware.org/bugzilla/show_bug.cgi?id=26206#add_comment -- Steve McIntyre, Cambridge, UK. steve(a)einval.com "...In the UNIX world, people tend to interpret `non-technical user' as meaning someone who's only ever written one device driver." -- Daniel Pead

4 years, 5 months

5
6
0 0

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O2_LTO - Build # 15 - Successful!

by ci_notify＠linaro.org

Successfully identified regression in *llvm* in CI configuration tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2_LTO. So far, this commit has regressed CI configurations: - tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2_LTO Culprit: <cut> commit 8fe62b7af1127691d6732438b322e66ae6d39a03 Author: Max Kazantsev <mkazantsev(a)azul.com> Date: Thu Apr 22 12:50:38 2021 +0700 [GVN] Introduce loop load PRE This patch allows PRE of the following type of loads: ``` preheader: br label %loop loop: br i1 ..., label %merge, label %clobber clobber: call foo() // Clobbers %p br label %merge merge: ... br i1 ..., label %loop, label %exit ``` Into ``` preheader: %x0 = load %p br label %loop loop: %x.pre = phi(x0, x2) br i1 ..., label %merge, label %clobber clobber: call foo() // Clobbers %p %x1 = load %p br label %merge merge: x2 = phi(x.pre, x1) ... br i1 ..., label %loop, label %exit ``` So instead of loading from %p on every iteration, we load only when the actual clobber happens. The typical pattern which it is trying to address is: hot loop, with all code inlined and provably having no side effects, and some side-effecting calls on cold path. The worst overhead from it is, if we always take clobber block, we make 1 more load overall (in preheader). It only matters if loop has very few iteration. If clobber block is not taken at least once, the transform is neutral or profitable. There are several improvements prospect open up: - We can sometimes be smarter in loop-exiting blocks via split of critical edges; - If we have block frequency info, we can handle multiple clobbers. The only obstacle now is that we don't know if their sum is colder than the header. Differential Revision: https://reviews.llvm.org/D99926 Reviewed By: reames </cut> Results regressed to (for first_bad == 8fe62b7af1127691d6732438b322e66ae6d39a03) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # build_llvm true: -3 # true: 0 # benchmark -O2_LTO -- artifacts/build-8fe62b7af1127691d6732438b322e66ae6d39a03/results_id: 1 # 464.h264ref,h264ref_base.default regressed by 104 from (for last_good == 722d4d8e7585457d407d0639a4ae2610157e06a8) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # build_llvm true: -3 # true: 0 # benchmark -O2_LTO -- artifacts/build-722d4d8e7585457d407d0639a4ae2610157e06a8/results_id: 1 Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… Results ID of last_good: tx1_64/tcwg_bmk_llvm_tx1/bisect-llvm-master-aarch64-spec2k6-O2_LTO/641 Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… Results ID of first_bad: tx1_64/tcwg_bmk_llvm_tx1/bisect-llvm-master-aarch64-spec2k6-O2_LTO/642 Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… Configuration details: Reproduce builds: <cut> mkdir investigate-llvm-8fe62b7af1127691d6732438b322e66ae6d39a03 cd investigate-llvm-8fe62b7af1127691d6732438b322e66ae6d39a03 git clone https://git.linaro.org/toolchain/jenkins-scripts mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh cd llvm # Reproduce first_bad build git checkout --detach 8fe62b7af1127691d6732438b322e66ae6d39a03 ../artifacts/test.sh # Reproduce last_good build git checkout --detach 722d4d8e7585457d407d0639a4ae2610157e06a8 ../artifacts/test.sh cd .. </cut> History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… Build log: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… Full commit (up to 1000 lines): <cut> commit 8fe62b7af1127691d6732438b322e66ae6d39a03 Author: Max Kazantsev <mkazantsev(a)azul.com> Date: Thu Apr 22 12:50:38 2021 +0700 [GVN] Introduce loop load PRE This patch allows PRE of the following type of loads: ``` preheader: br label %loop loop: br i1 ..., label %merge, label %clobber clobber: call foo() // Clobbers %p br label %merge merge: ... br i1 ..., label %loop, label %exit ``` Into ``` preheader: %x0 = load %p br label %loop loop: %x.pre = phi(x0, x2) br i1 ..., label %merge, label %clobber clobber: call foo() // Clobbers %p %x1 = load %p br label %merge merge: x2 = phi(x.pre, x1) ... br i1 ..., label %loop, label %exit ``` So instead of loading from %p on every iteration, we load only when the actual clobber happens. The typical pattern which it is trying to address is: hot loop, with all code inlined and provably having no side effects, and some side-effecting calls on cold path. The worst overhead from it is, if we always take clobber block, we make 1 more load overall (in preheader). It only matters if loop has very few iteration. If clobber block is not taken at least once, the transform is neutral or profitable. There are several improvements prospect open up: - We can sometimes be smarter in loop-exiting blocks via split of critical edges; - If we have block frequency info, we can handle multiple clobbers. The only obstacle now is that we don't know if their sum is colder than the header. Differential Revision: https://reviews.llvm.org/D99926 Reviewed By: reames --- llvm/include/llvm/Transforms/Scalar/GVN.h | 6 ++ llvm/lib/Transforms/Scalar/GVN.cpp | 92 +++++++++++++++++++++++++-- llvm/test/Transforms/GVN/PRE/pre-loop-load.ll | 9 ++- 3 files changed, 98 insertions(+), 9 deletions(-) diff --git a/llvm/include/llvm/Transforms/Scalar/GVN.h b/llvm/include/llvm/Transforms/Scalar/GVN.h index 13f55ddcf2d6..70662ca213c3 100644 --- a/llvm/include/llvm/Transforms/Scalar/GVN.h +++ b/llvm/include/llvm/Transforms/Scalar/GVN.h @@ -328,6 +328,12 @@ private: bool PerformLoadPRE(LoadInst *Load, AvailValInBlkVect &ValuesPerBlock, UnavailBlkVect &UnavailableBlocks); + /// Try to replace a load which executes on each loop iteraiton with Phi + /// translation of load in preheader and load(s) in conditionally executed + /// paths. + bool performLoopLoadPRE(LoadInst *Load, AvailValInBlkVect &ValuesPerBlock, + UnavailBlkVect &UnavailableBlocks); + /// Eliminates partially redundant \p Load, replacing it with \p /// AvailableLoads (connected by Phis if needed). void eliminatePartiallyRedundantLoad( diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp index 846a5cdb33d1..29da739fa16e 100644 --- a/llvm/lib/Transforms/Scalar/GVN.cpp +++ b/llvm/lib/Transforms/Scalar/GVN.cpp @@ -91,13 +91,14 @@ using namespace PatternMatch; #define DEBUG_TYPE "gvn" -STATISTIC(NumGVNInstr, "Number of instructions deleted"); -STATISTIC(NumGVNLoad, "Number of loads deleted"); -STATISTIC(NumGVNPRE, "Number of instructions PRE'd"); +STATISTIC(NumGVNInstr, "Number of instructions deleted"); +STATISTIC(NumGVNLoad, "Number of loads deleted"); +STATISTIC(NumGVNPRE, "Number of instructions PRE'd"); STATISTIC(NumGVNBlocks, "Number of blocks merged"); -STATISTIC(NumGVNSimpl, "Number of instructions simplified"); +STATISTIC(NumGVNSimpl, "Number of instructions simplified"); STATISTIC(NumGVNEqProp, "Number of equalities propagated"); -STATISTIC(NumPRELoad, "Number of loads PRE'd"); +STATISTIC(NumPRELoad, "Number of loads PRE'd"); +STATISTIC(NumPRELoopLoad, "Number of loop loads PRE'd"); STATISTIC(IsValueFullyAvailableInBlockNumSpeculationsMax, "Number of blocks speculated as available in " @@ -1447,6 +1448,84 @@ bool GVN::PerformLoadPRE(LoadInst *Load, AvailValInBlkVect &ValuesPerBlock, return true; } +bool GVN::performLoopLoadPRE(LoadInst *Load, AvailValInBlkVect &ValuesPerBlock, + UnavailBlkVect &UnavailableBlocks) { + if (!LI) + return false; + + const Loop *L = LI->getLoopFor(Load->getParent()); + // TODO: Generalize to other loop blocks that dominate the latch. + if (!L || L->getHeader() != Load->getParent()) + return false; + + BasicBlock *Preheader = L->getLoopPreheader(); + BasicBlock *Latch = L->getLoopLatch(); + if (!Preheader || !Latch) + return false; + + Value *LoadPtr = Load->getPointerOperand(); + // Must be available in preheader. + if (!L->isLoopInvariant(LoadPtr)) + return false; + + // We plan to hoist the load to preheader without introducing a new fault. + // In order to do it, we need to prove that we cannot side-exit the loop + // once loop header is first entered before execution of the load. + if (ICF->isDominatedByICFIFromSameBlock(Load)) + return false; + + BasicBlock *LoopBlock = nullptr; + for (auto *Blocker : UnavailableBlocks) { + // Blockers from outside the loop are handled in preheader. + if (!L->contains(Blocker)) + continue; + + // Only allow one loop block. Loop header is not less frequently executed + // than each loop block, and likely it is much more frequently executed. But + // in case of multiple loop blocks, we need extra information (such as block + // frequency info) to understand whether it is profitable to PRE into + // multiple loop blocks. + if (LoopBlock) + return false; + + // Do not sink into inner loops. This may be non-profitable. + if (L != LI->getLoopFor(Blocker)) + return false; + + // Blocks that dominate the latch execute on every single iteration, maybe + // except the last one. So PREing into these blocks doesn't make much sense + // in most cases. But the blocks that do not necessarily execute on each + // iteration are sometimes much colder than the header, and this is when + // PRE is potentially profitable. + if (DT->dominates(Blocker, Latch)) + return false; + + // Make sure that the terminator itself doesn't clobber. + if (Blocker->getTerminator()->mayWriteToMemory()) + return false; + + LoopBlock = Blocker; + } + + if (!LoopBlock) + return false; + + // Make sure the memory at this pointer cannot be freed, therefore we can + // safely reload from it after clobber. + if (LoadPtr->canBeFreed()) + return false; + + // TODO: Support critical edge splitting if blocker has more than 1 successor. + MapVector<BasicBlock *, Value *> AvailableLoads; + AvailableLoads[LoopBlock] = LoadPtr; + AvailableLoads[Preheader] = LoadPtr; + + LLVM_DEBUG(dbgs() << "GVN REMOVING PRE LOOP LOAD: " << *Load << '\n'); + eliminatePartiallyRedundantLoad(Load, ValuesPerBlock, AvailableLoads); + ++NumPRELoopLoad; + return true; +} + static void reportLoadElim(LoadInst *Load, Value *AvailableValue, OptimizationRemarkEmitter *ORE) { using namespace ore; @@ -1544,7 +1623,8 @@ bool GVN::processNonLocalLoad(LoadInst *Load) { if (!isLoadInLoopPREEnabled() && LI && LI->getLoopFor(Load->getParent())) return Changed; - return Changed || PerformLoadPRE(Load, ValuesPerBlock, UnavailableBlocks); + return Changed || PerformLoadPRE(Load, ValuesPerBlock, UnavailableBlocks) || + performLoopLoadPRE(Load, ValuesPerBlock, UnavailableBlocks); } static bool impliesEquivalanceIfTrue(CmpInst* Cmp) { diff --git a/llvm/test/Transforms/GVN/PRE/pre-loop-load.ll b/llvm/test/Transforms/GVN/PRE/pre-loop-load.ll index 15bc49e7ab9a..8ca12284d5c4 100644 --- a/llvm/test/Transforms/GVN/PRE/pre-loop-load.ll +++ b/llvm/test/Transforms/GVN/PRE/pre-loop-load.ll @@ -7,22 +7,25 @@ declare void @may_free_memory() declare i32 @personality_function() -; TODO: We can PRE the load from gc-managed memory away from the hot path. +; We can PRE the load from gc-managed memory away from the hot path. define i32 @test_load_on_cold_path_gc(i32 addrspace(1)* %p) gc "statepoint-example" personality i32 ()* @"personality_function" { ; CHECK-LABEL: @test_load_on_cold_path_gc( ; CHECK-NEXT: entry: +; CHECK-NEXT: [[X_PRE1:%.*]] = load i32, i32 addrspace(1)* [[P:%.*]], align 4 ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ] -; CHECK-NEXT: [[X:%.*]] = load i32, i32 addrspace(1)* [[P:%.*]], align 4 +; CHECK-NEXT: [[X:%.*]] = phi i32 [ [[X_PRE1]], [[ENTRY:%.*]] ], [ [[X2:%.*]], [[BACKEDGE:%.*]] ] +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE]] ] ; CHECK-NEXT: [[COND:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: br i1 [[COND]], label [[HOT_PATH:%.*]], label [[COLD_PATH:%.*]] ; CHECK: hot_path: ; CHECK-NEXT: br label [[BACKEDGE]] ; CHECK: cold_path: ; CHECK-NEXT: call void @may_free_memory() +; CHECK-NEXT: [[X_PRE:%.*]] = load i32, i32 addrspace(1)* [[P]], align 4 ; CHECK-NEXT: br label [[BACKEDGE]] ; CHECK: backedge: +; CHECK-NEXT: [[X2]] = phi i32 [ [[X_PRE]], [[COLD_PATH]] ], [ [[X]], [[HOT_PATH]] ] ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], [[X]] ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[IV_NEXT]], 1000 ; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]] </cut>

4 years, 5 months

1
0
0 0

Re: Buildbot failure in LLVM Buildbot on clang-armv7-quick

by Philip Reames

This bot failure appears to be unrelated to the fingered change. From the commit log, I'd guess that 9eaf0d120 by Joel E. Denny <jdenny.ornl(a)gmail.com> was the triggering change, but that's not in the blame list. Joel, FYI. Linaro folks, as bot owner, you should investigate why the blame list is wrong. JFYI, this is not the only bot failing with the wrong blame list, so it might be a common problem. Philip On 6/25/21 10:43 AM, llvm.buildmaster(a)lab.llvm.org wrote: > The Buildbot has detected a failed build on builder clang-armv7-quick while building llvm. > > Full details are available at: > https://lab.llvm.org/buildbot#builders/171/builds/113 > > Worker for this Build: linaro-clang-armv7-quick > Blamelist: > Philip Reames <listmail(a)philipreames.com> > > BUILD FAILED: failed 48104 expected passes 1 unexpected failures 72 expected failures Unexpected test result output SKIPPED 26089 unsupported tests (failure) > > Step 5 (ninja check 1) failure: 48104 expected passes 1 unexpected failures 72 expected failures Unexpected test result output SKIPPED 26089 unsupported tests (failure) > ******************** TEST 'Clang :: utils/update_cc_test_checks/check-globals.test' FAILED ******************** > Script: > -- > : 'RUN: at line 1'; rm -rf /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp && mkdir /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp > : 'RUN: at line 5'; cp /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/Inputs/check-globals.c /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c > : 'RUN: at line 6'; /usr/bin/python3.6 /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/update_cc_test_checks.py --clang /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/clang --opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c --check-globals > : 'RUN: at line 7'; /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/FileCheck /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/check-globals.test --input-file=/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c --match-full-lines -strict-whitespace -check-prefixes=BOTH,NRM > : 'RUN: at line 10'; cp /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/Inputs/check-globals.c /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c > : 'RUN: at line 11'; /usr/bin/python3.6 /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/update_cc_test_checks.py --clang /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/clang --opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c --check-globals --include-generated-funcs > : 'RUN: at line 12'; /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/FileCheck /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/check-globals.test --input-file=/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c --match-full-lines -strict-whitespace -check-prefixes=BOTH,IGF > : 'RUN: at line 17'; cp /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm-again.c > : 'RUN: at line 18'; /usr/bin/python3.6 /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/update_cc_test_checks.py --clang /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/clang --opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm-again.c --check-globals > : 'RUN: at line 19'; diff -u /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm-again.c > : 'RUN: at line 20'; rm /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm-again.c > : 'RUN: at line 22'; cp /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf-again.c > : 'RUN: at line 23'; /usr/bin/python3.6 /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/update_cc_test_checks.py --clang /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/clang --opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/opt /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf-again.c --check-globals --include-generated-funcs > : 'RUN: at line 25'; diff -u /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf-again.c > : 'RUN: at line 26'; rm /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf-again.c > : 'RUN: at line 31'; cp /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/Inputs/lit.cfg.example /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/lit.cfg > : 'RUN: at line 33'; /usr/bin/python3.6 /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/lit/lit.py -Dclang_obj_root=/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang -j1 -vv /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp > : 'RUN: at line 35'; /usr/bin/python3.6 /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/lit/lit.py -Dclang_obj_root=/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang -j1 -vv /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp 2>&1 | /home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/FileCheck -check-prefix=LIT-RUN /home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/check-globals.test > -- > Exit Code: 1 > > Command Output (stdout): > -- > $ ":" "RUN: at line 1" > $ "rm" "-rf" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp" > $ "mkdir" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp" > $ ":" "RUN: at line 5" > $ "cp" "/home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/Inputs/check-globals.c" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c" > $ ":" "RUN: at line 6" > $ "/usr/bin/python3.6" "/home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/update_cc_test_checks.py" "--clang" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/clang" "--opt" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/opt" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c" "--check-globals" > # command stderr: > NOTE: Executing non-FileChecked RUN line: true > > $ ":" "RUN: at line 7" > $ "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/FileCheck" "/home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/check-globals.test" "--input-file=/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c" "--match-full-lines" "-strict-whitespace" "-check-prefixes=BOTH,NRM" > $ ":" "RUN: at line 10" > $ "cp" "/home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/Inputs/check-globals.c" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c" > $ ":" "RUN: at line 11" > $ "/usr/bin/python3.6" "/home/tcwg-buildslave/worker/clang-armv7-quick/llvm/llvm/utils/update_cc_test_checks.py" "--clang" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/clang" "--opt" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/opt" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c" "--check-globals" "--include-generated-funcs" > # command stderr: > NOTE: Executing non-FileChecked RUN line: true > > $ ":" "RUN: at line 12" > $ "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/bin/FileCheck" "/home/tcwg-buildslave/worker/clang-armv7-quick/llvm/clang/test/utils/update_cc_test_checks/check-globals.test" "--input-file=/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/igf.c" "--match-full-lines" "-strict-whitespace" "-check-prefixes=BOTH,IGF" > $ ":" "RUN: at line 17" > $ "cp" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm.c" "/home/tcwg-buildslave/worker/clang-armv7-quick/stage1/tools/clang/test/utils/update_cc_test_checks/Output/check-globals.test.tmp/norm-again.c" > $ ":" "RUN: at line 18" > ... > > Sincerely, > LLVM Buildbot >

4 years, 5 months

3
2
0 0

Re: [CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os_LTO - Build # 31 - Fixed!

by Maxim Kuvyrkov

I’m running historical performance experiments, and this commit from 2019 showed up on my radar. Just in case someone is interested in running Fortran code on memory-constrained M-profile cores ... It appears that Janne’s patch increases code-size of 437.leslie3d by around 2% on 32-bit ARM (well, Thumb2, to be precise). It may be interesting to check what’s going on, since AArch64 is not affected. One possibility is that before this patch all literal-pool entries for error messages were shared, and with variation of error messages all of them became different entries, thus increasing code size. -- Maxim Kuvyrkov https://www.linaro.org > On 28 Jun 2021, at 00:54, ci_notify(a)linaro.org wrote: > > Successfully identified regression in *gcc* in CI configuration tcwg_bmk_gnu_tk1/gnu-release-arm-spec2k6-Os_LTO. So far, this commit has regressed CI configurations: > - tcwg_bmk_gnu_tk1/gnu-release-arm-spec2k6-Os_LTO > - tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os > > Culprit: > <cut> > commit d74a8b0579edd0c42921eccc45ab986d24f2fef0 > Author: Janne Blomqvist <jb(a)gcc.gnu.org> > > PR fortran/68401 Improve allocation error message > </cut> > > Results regressed to (for first_bad == d74a8b0579edd0c42921eccc45ab986d24f2fef0) > # reset_artifacts: > -10 > # build_abe binutils: > -9 > # build_abe stage1 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: > -8 > # build_abe linux: > -7 > # build_abe glibc: > -6 > # build_abe stage2 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: > -5 > # true: > 0 > # benchmark -Os_LTO_mthumb -- artifacts/build-d74a8b0579edd0c42921eccc45ab986d24f2fef0/results_id: > 1 > # 437.leslie3d,leslie3d_base.default regressed by 102 > > from (for last_good == 777c02825229f14cf91c6044827ea42a77ded4a3) > # reset_artifacts: > -10 > # build_abe binutils: > -9 > # build_abe stage1 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: > -8 > # build_abe linux: > -7 > # build_abe glibc: > -6 > # build_abe stage2 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer: > -5 > # true: > 0 > # benchmark -Os_LTO_mthumb -- artifacts/build-777c02825229f14cf91c6044827ea42a77ded4a3/results_id: > 1 > > Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… > Results ID of last_good: tk1_32/tcwg_bmk_gnu_tk1/bisect-gnu-release-arm-spec2k6-Os_LTO/531 > Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… > Results ID of first_bad: tk1_32/tcwg_bmk_gnu_tk1/bisect-gnu-release-arm-spec2k6-Os_LTO/539 > Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… > > Configuration details: > > > Reproduce builds: > <cut> > mkdir investigate-gcc-d74a8b0579edd0c42921eccc45ab986d24f2fef0 > cd investigate-gcc-d74a8b0579edd0c42921eccc45ab986d24f2fef0 > > git clone https://git.linaro.org/toolchain/jenkins-scripts > > mkdir -p artifacts/manifests > curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… --fail > curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… --fail > curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… --fail > chmod +x artifacts/test.sh > > # Reproduce the baseline build (build all pre-requisites) > ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh > > cd gcc > > # Reproduce first_bad build > git checkout --detach d74a8b0579edd0c42921eccc45ab986d24f2fef0 > ../artifacts/test.sh > > # Reproduce last_good build > git checkout --detach 777c02825229f14cf91c6044827ea42a77ded4a3 > ../artifacts/test.sh > > cd .. > </cut> > > History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… > > Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… > Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… > > Full commit (up to 1000 lines): > <cut> > commit d74a8b0579edd0c42921eccc45ab986d24f2fef0 > Author: Janne Blomqvist <jb(a)gcc.gnu.org> > Date: Sat Aug 17 08:45:37 2019 +0300 > > PR fortran/68401 Improve allocation error message > > Improve the error message that is printed when a memory allocation > fails, by including the location, and the size of the allocation that > failed. > > Regtested on x86_64-pc-linux-gnu. > > gcc/fortran/ChangeLog: > > 2019-08-17 Janne Blomqvist <jb(a)gcc.gnu.org> > > PR fortran/68401 > * trans-decl.c (gfc_build_builtin_function_decls): Replace > os_error with os_error_at decl. > * trans.c (trans_runtime_error_vararg): Modify so the error > function decl is passed directly. > (gfc_trans_runtime_error): Pass correct error function decl. > (gfc_trans_runtime_check): Likewise. > (trans_os_error_at): New function. > (gfc_call_malloc): Use trans_os_error_at. > (gfc_allocate_using_malloc): Likewise. > (gfc_call_realloc): Likewise. > * trans.h (gfor_fndecl_os_error): Replace with gfor_fndecl_os_error_at. > > libgfortran/ChangeLog: > > 2019-08-17 Janne Blomqvist <jb(a)gcc.gnu.org> > > PR fortran/68401 > * gfortran.map: Add GFORTRAN_10 node, add _gfortran_os_error_at > symbol. > * libgfortran.h (os_error_at): New prototype. > * runtime/error.c (os_error_at): New function. > > From-SVN: r274599 > --- > gcc/fortran/ChangeLog | 17 +++++++++++- > gcc/fortran/trans-decl.c | 12 ++++---- > gcc/fortran/trans.c | 68 +++++++++++++++++++++++++++------------------ > gcc/fortran/trans.h | 2 +- > libgfortran/ChangeLog | 8 ++++++ > libgfortran/gfortran.map | 5 ++++ > libgfortran/libgfortran.h | 4 +++ > libgfortran/runtime/error.c | 46 +++++++++++++++++++++++++++++- > 8 files changed, 126 insertions(+), 36 deletions(-) > > diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog > index bab69f3000e..a3b9e6bf486 100644 > --- a/gcc/fortran/ChangeLog > +++ b/gcc/fortran/ChangeLog > @@ -1,3 +1,18 @@ > +2019-08-17 Janne Blomqvist <jb(a)gcc.gnu.org> > + > + PR fortran/68401 > + * trans-decl.c (gfc_build_builtin_function_decls): Replace > + os_error with os_error_at decl. > + * trans.c (trans_runtime_error_vararg): Modify so the error > + function decl is passed directly. > + (gfc_trans_runtime_error): Pass correct error function decl. > + (gfc_trans_runtime_check): Likewise. > + (trans_os_error_at): New function. > + (gfc_call_malloc): Use trans_os_error_at. > + (gfc_allocate_using_malloc): Likewise. > + (gfc_call_realloc): Likewise. > + * trans.h (gfor_fndecl_os_error): Replace with gfor_fndecl_os_error_at. > + > 2019-08-16 Jeff Law <law(a)redhat.com> > Mark Eggleston <mark.eggleston(a)codethink.com> > > @@ -18,7 +33,7 @@ > * trans-common.c (find_equivalence) : New local variable dummy_symbol, > accumulated equivalence attributes from each symbol then check for > conflicts. > - > + > 2019-08-16 Richard Biener <rguenther(a)suse.de> > > * trans-intrinsic.c (gfc_conv_intrinsic_findloc): Initialize > diff --git a/gcc/fortran/trans-decl.c b/gcc/fortran/trans-decl.c > index 2a9b852568a..3c6ab60e9b2 100644 > --- a/gcc/fortran/trans-decl.c > +++ b/gcc/fortran/trans-decl.c > @@ -102,7 +102,7 @@ tree gfor_fndecl_error_stop_string; > tree gfor_fndecl_runtime_error; > tree gfor_fndecl_runtime_error_at; > tree gfor_fndecl_runtime_warning_at; > -tree gfor_fndecl_os_error; > +tree gfor_fndecl_os_error_at; > tree gfor_fndecl_generate_error; > tree gfor_fndecl_set_args; > tree gfor_fndecl_set_fpe; > @@ -3679,11 +3679,11 @@ gfc_build_builtin_function_decls (void) > void_type_node, 3, pvoid_type_node, integer_type_node, > pchar_type_node); > > - gfor_fndecl_os_error = gfc_build_library_function_decl_with_spec ( > - get_identifier (PREFIX("os_error")), ".R", > - void_type_node, 1, pchar_type_node); > - /* The runtime_error function does not return. */ > - TREE_THIS_VOLATILE (gfor_fndecl_os_error) = 1; > + gfor_fndecl_os_error_at = gfc_build_library_function_decl_with_spec ( > + get_identifier (PREFIX("os_error_at")), ".RR", > + void_type_node, -2, pchar_type_node, pchar_type_node); > + /* The os_error_at function does not return. */ > + TREE_THIS_VOLATILE (gfor_fndecl_os_error_at) = 1; > > gfor_fndecl_set_args = gfc_build_library_function_decl ( > get_identifier (PREFIX("set_args")), > diff --git a/gcc/fortran/trans.c b/gcc/fortran/trans.c > index 84511477b39..583f6e3b25b 100644 > --- a/gcc/fortran/trans.c > +++ b/gcc/fortran/trans.c > @@ -447,7 +447,7 @@ gfc_build_array_ref (tree base, tree offset, tree decl, tree vptr) > arguments and a locus. */ > > static tree > -trans_runtime_error_vararg (bool error, locus* where, const char* msgid, > +trans_runtime_error_vararg (tree errorfunc, locus* where, const char* msgid, > va_list ap) > { > stmtblock_t block; > @@ -501,18 +501,13 @@ trans_runtime_error_vararg (bool error, locus* where, const char* msgid, > /* Build the function call to runtime_(warning,error)_at; because of the > variable number of arguments, we can't use build_call_expr_loc dinput_location, > irectly. */ > - if (error) > - fntype = TREE_TYPE (gfor_fndecl_runtime_error_at); > - else > - fntype = TREE_TYPE (gfor_fndecl_runtime_warning_at); > + fntype = TREE_TYPE (errorfunc); > > loc = where ? where->lb->location : input_location; > tmp = fold_build_call_array_loc (loc, TREE_TYPE (fntype), > fold_build1_loc (loc, ADDR_EXPR, > build_pointer_type (fntype), > - error > - ? gfor_fndecl_runtime_error_at > - : gfor_fndecl_runtime_warning_at), > + errorfunc), > nargs + 2, argarray); > gfc_add_expr_to_block (&block, tmp); > > @@ -527,7 +522,10 @@ gfc_trans_runtime_error (bool error, locus* where, const char* msgid, ...) > tree result; > > va_start (ap, msgid); > - result = trans_runtime_error_vararg (error, where, msgid, ap); > + result = trans_runtime_error_vararg (error > + ? gfor_fndecl_runtime_error_at > + : gfor_fndecl_runtime_warning_at, > + where, msgid, ap); > va_end (ap); > return result; > } > @@ -566,8 +564,10 @@ gfc_trans_runtime_check (bool error, bool once, tree cond, stmtblock_t * pblock, > /* The code to generate the error. */ > va_start (ap, msgid); > gfc_add_expr_to_block (&block, > - trans_runtime_error_vararg (error, where, > - msgid, ap)); > + trans_runtime_error_vararg > + (error ? gfor_fndecl_runtime_error_at > + : gfor_fndecl_runtime_warning_at, > + where, msgid, ap)); > va_end (ap); > > if (once) > @@ -595,13 +595,28 @@ gfc_trans_runtime_check (bool error, bool once, tree cond, stmtblock_t * pblock, > } > > > +static tree > +trans_os_error_at (locus* where, const char* msgid, ...) > +{ > + va_list ap; > + tree result; > + > + va_start (ap, msgid); > + result = trans_runtime_error_vararg (gfor_fndecl_os_error_at, > + where, msgid, ap); > + va_end (ap); > + return result; > +} > + > + > + > /* Call malloc to allocate size bytes of memory, with special conditions: > + if size == 0, return a malloced area of size 1, > + if malloc returns NULL, issue a runtime error. */ > tree > gfc_call_malloc (stmtblock_t * block, tree type, tree size) > { > - tree tmp, msg, malloc_result, null_result, res, malloc_tree; > + tree tmp, malloc_result, null_result, res, malloc_tree; > stmtblock_t block2; > > /* Create a variable to hold the result. */ > @@ -626,13 +641,14 @@ gfc_call_malloc (stmtblock_t * block, tree type, tree size) > null_result = fold_build2_loc (input_location, EQ_EXPR, > logical_type_node, res, > build_int_cst (pvoid_type_node, 0)); > - msg = gfc_build_addr_expr (pchar_type_node, > - gfc_build_localized_cstring_const ("Memory allocation failed")); > tmp = fold_build3_loc (input_location, COND_EXPR, void_type_node, > null_result, > - build_call_expr_loc (input_location, > - gfor_fndecl_os_error, 1, msg), > - build_empty_stmt (input_location)); > + trans_os_error_at (NULL, > + "Error allocating %lu bytes", > + fold_convert > + (long_unsigned_type_node, > + size)), > + build_empty_stmt (input_location)); > gfc_add_expr_to_block (&block2, tmp); > } > > @@ -701,11 +717,9 @@ gfc_allocate_using_malloc (stmtblock_t * block, tree pointer, > } > else > { > - /* Here, os_error already implies PRED_NORETURN. */ > - tmp = build_call_expr_loc (input_location, gfor_fndecl_os_error, 1, > - gfc_build_addr_expr (pchar_type_node, > - gfc_build_localized_cstring_const > - ("Allocation would exceed memory limit"))); > + /* Here, os_error_at already implies PRED_NORETURN. */ > + tree lusize = fold_convert (long_unsigned_type_node, size); > + tmp = trans_os_error_at (NULL, "Error allocating %lu bytes", lusize); > gfc_add_expr_to_block (&on_error, tmp); > } > > @@ -1664,7 +1678,7 @@ internal_realloc (void *mem, size_t size) > tree > gfc_call_realloc (stmtblock_t * block, tree mem, tree size) > { > - tree msg, res, nonzero, null_result, tmp; > + tree res, nonzero, null_result, tmp; > tree type = TREE_TYPE (mem); > > /* Only evaluate the size once. */ > @@ -1684,12 +1698,12 @@ gfc_call_realloc (stmtblock_t * block, tree mem, tree size) > build_int_cst (size_type_node, 0)); > null_result = fold_build2_loc (input_location, TRUTH_AND_EXPR, logical_type_node, > null_result, nonzero); > - msg = gfc_build_addr_expr (pchar_type_node, gfc_build_localized_cstring_const > - ("Allocation would exceed memory limit")); > tmp = fold_build3_loc (input_location, COND_EXPR, void_type_node, > null_result, > - build_call_expr_loc (input_location, > - gfor_fndecl_os_error, 1, msg), > + trans_os_error_at (NULL, > + "Error reallocating to %lu bytes", > + fold_convert > + (long_unsigned_type_node, size)), > build_empty_stmt (input_location)); > gfc_add_expr_to_block (block, tmp); > > diff --git a/gcc/fortran/trans.h b/gcc/fortran/trans.h > index a3726e84140..8082b414df1 100644 > --- a/gcc/fortran/trans.h > +++ b/gcc/fortran/trans.h > @@ -803,7 +803,7 @@ extern GTY(()) tree gfor_fndecl_error_stop_string; > extern GTY(()) tree gfor_fndecl_runtime_error; > extern GTY(()) tree gfor_fndecl_runtime_error_at; > extern GTY(()) tree gfor_fndecl_runtime_warning_at; > -extern GTY(()) tree gfor_fndecl_os_error; > +extern GTY(()) tree gfor_fndecl_os_error_at; > extern GTY(()) tree gfor_fndecl_generate_error; > extern GTY(()) tree gfor_fndecl_set_fpe; > extern GTY(()) tree gfor_fndecl_set_options; > diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog > index 7a11ca29fd3..23a4c579351 100644 > --- a/libgfortran/ChangeLog > +++ b/libgfortran/ChangeLog > @@ -1,3 +1,11 @@ > +2019-08-17 Janne Blomqvist <jb(a)gcc.gnu.org> > + > + PR fortran/68401 > + * gfortran.map: Add GFORTRAN_10 node, add _gfortran_os_error_at > + symbol. > + * libgfortran.h (os_error_at): New prototype. > + * runtime/error.c (os_error_at): New function. > + > 2019-08-13 Janne Blomqvist <jb(a)gcc.gnu.org> > > PR fortran/91414 > diff --git a/libgfortran/gfortran.map b/libgfortran/gfortran.map > index 2b2243b4fd4..3601bc24414 100644 > --- a/libgfortran/gfortran.map > +++ b/libgfortran/gfortran.map > @@ -1602,3 +1602,8 @@ GFORTRAN_9.2 { > _gfortran_mfindloc1_r10; > _gfortran_sfindloc1_r10; > } GFORTRAN_9; > + > +GFORTRAN_10 { > + global: > + _gfortran_os_error_at; > +} GFORTRAN_9.2; > diff --git a/libgfortran/libgfortran.h b/libgfortran/libgfortran.h > index c0db96f02a8..9f535b12e73 100644 > --- a/libgfortran/libgfortran.h > +++ b/libgfortran/libgfortran.h > @@ -728,6 +728,10 @@ internal_proto(gfc_xtoa); > extern _Noreturn void os_error (const char *); > iexport_proto(os_error); > > +extern _Noreturn void os_error_at (const char *, const char *, ...) > + __attribute__ ((format (gfc_printf, 2, 3))); > +iexport_proto(os_error_at); > + > extern void show_locus (st_parameter_common *); > internal_proto(show_locus); > > diff --git a/libgfortran/runtime/error.c b/libgfortran/runtime/error.c > index 0335a165edc..cbe0642f3f8 100644 > --- a/libgfortran/runtime/error.c > +++ b/libgfortran/runtime/error.c > @@ -403,7 +403,51 @@ os_error (const char *message) > estr_writev (iov, 5); > exit_error (1); > } > -iexport(os_error); > +iexport(os_error); /* TODO, DEPRECATED, ABI: Should not be exported > + anymore when bumping so version. */ > + > + > +/* Improved version of os_error with a printf style format string and > + a locus. */ > + > +void > +os_error_at (const char *where, const char *message, ...) > +{ > + char errmsg[STRERR_MAXSZ]; > + char buffer[STRERR_MAXSZ]; > + struct iovec iov[6]; > + va_list ap; > + recursion_check (); > + int written; > + > + iov[0].iov_base = (char*) where; > + iov[0].iov_len = strlen (where); > + > + iov[1].iov_base = (char*) ": "; > + iov[1].iov_len = strlen (iov[1].iov_base); > + > + va_start (ap, message); > + written = vsnprintf (buffer, STRERR_MAXSZ, message, ap); > + va_end (ap); > + iov[2].iov_base = buffer; > + if (written >= 0) > + iov[2].iov_len = written; > + else > + iov[2].iov_len = 0; > + > + iov[3].iov_base = (char*) ": "; > + iov[3].iov_len = strlen (iov[3].iov_base); > + > + iov[4].iov_base = gf_strerror (errno, errmsg, STRERR_MAXSZ); > + iov[4].iov_len = strlen (iov[4].iov_base); > + > + iov[5].iov_base = (char*) "\n"; > + iov[5].iov_len = 1; > + > + estr_writev (iov, 6); > + exit_error (1); > +} > +iexport(os_error_at); > > > /* void runtime_error()-- These are errors associated with an > </cut>

4 years, 5 months

1
0
0 0

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2_LTO - Build # 31 - Successful!

by ci_notify＠linaro.org

Successfully identified regression in *gcc* in CI configuration tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O2_LTO. So far, this commit has regressed CI configurations: - tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O2_LTO Culprit: <cut> commit 32955416d8040b1fa1ba21cd4179b3264e6c5bd6 Author: Richard Biener <rguenther(a)suse.de> Date: Mon May 3 12:07:58 2021 +0200 Improve PHI handling in DSE This improves handling of PHI defs when walking uses in dse_classify_store to track two PHI defs. This happens when there are CFG merges and one PHI feeds into another. If we decide to want more then using a sbitmap for this might be the way to go. 2021-05-03 Richard Biener <rguenther(a)suse.de> * tree-ssa-dse.c (dse_classify_store): Track two PHI defs. * gcc.dg/tree-ssa/ssa-dse-42.c: New testcase. * gcc.dg/pr81192.c: Disable DSE. </cut> Results regressed to (for first_bad == 32955416d8040b1fa1ba21cd4179b3264e6c5bd6) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO_marm -- artifacts/build-32955416d8040b1fa1ba21cd4179b3264e6c5bd6/results_id: 1 # 483.xalancbmk,Xalan_base.default regressed by 103 from (for last_good == ed3c43224cc4e378dbab066122bc63536ccb1276) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO_marm -- artifacts/build-ed3c43224cc4e378dbab066122bc63536ccb1276/results_id: 1 Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… Results ID of last_good: tk1_32/tcwg_bmk_gnu_tk1/bisect-gnu-master-arm-spec2k6-O2_LTO/458 Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… Results ID of first_bad: tk1_32/tcwg_bmk_gnu_tk1/bisect-gnu-master-arm-spec2k6-O2_LTO/480 Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… Configuration details: Reproduce builds: <cut> mkdir investigate-gcc-32955416d8040b1fa1ba21cd4179b3264e6c5bd6 cd investigate-gcc-32955416d8040b1fa1ba21cd4179b3264e6c5bd6 git clone https://git.linaro.org/toolchain/jenkins-scripts mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh cd gcc # Reproduce first_bad build git checkout --detach 32955416d8040b1fa1ba21cd4179b3264e6c5bd6 ../artifacts/test.sh # Reproduce last_good build git checkout --detach ed3c43224cc4e378dbab066122bc63536ccb1276 ../artifacts/test.sh cd .. </cut> History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-master-ar… Full commit (up to 1000 lines): <cut> commit 32955416d8040b1fa1ba21cd4179b3264e6c5bd6 Author: Richard Biener <rguenther(a)suse.de> Date: Mon May 3 12:07:58 2021 +0200 Improve PHI handling in DSE This improves handling of PHI defs when walking uses in dse_classify_store to track two PHI defs. This happens when there are CFG merges and one PHI feeds into another. If we decide to want more then using a sbitmap for this might be the way to go. 2021-05-03 Richard Biener <rguenther(a)suse.de> * tree-ssa-dse.c (dse_classify_store): Track two PHI defs. * gcc.dg/tree-ssa/ssa-dse-42.c: New testcase. * gcc.dg/pr81192.c: Disable DSE. --- gcc/testsuite/gcc.dg/pr81192.c | 4 +++- gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-42.c | 20 ++++++++++++++++++++ gcc/tree-ssa-dse.c | 23 ++++++++++++++--------- 3 files changed, 37 insertions(+), 10 deletions(-) diff --git a/gcc/testsuite/gcc.dg/pr81192.c b/gcc/testsuite/gcc.dg/pr81192.c index 71bbc13a0e9..6cab6056558 100644 --- a/gcc/testsuite/gcc.dg/pr81192.c +++ b/gcc/testsuite/gcc.dg/pr81192.c @@ -1,4 +1,4 @@ -/* { dg-options "-Os -fdump-tree-pre-details -fdisable-tree-evrp" } */ +/* { dg-options "-Os -fdump-tree-pre-details -fdisable-tree-evrp -fno-tree-dse" } */ /* Disable tree-evrp because the new version of evrp sees <bb 3> : @@ -16,6 +16,8 @@ produces # iftmp.2_12 = PHI <2147483647(3), iftmp.2_11(4)> which causes the situation being tested to dissapear before we get to PRE. */ +/* Likewise disable DSE which also elides the tail merging "opportunity". */ + #if __SIZEOF_INT__ == 2 #define unsigned __UINT32_TYPE__ #define int __INT32_TYPE__ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-42.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-42.c new file mode 100644 index 00000000000..34108c83828 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-42.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-dse1" } */ + +int a[2]; +void foo(int i, int k, int j) +{ + a[0] = i; + if (k) + a[0] = a[i] + k; + else + { + if (j) + a[1] = 1; + a[0] = a[i] + 3; + } + a[0] = 0; +} + +/* The last stores to a[0] and a[1] remain. */ +/* { dg-final { scan-tree-dump-times " = " 2 "dse1" } } */ diff --git a/gcc/tree-ssa-dse.c b/gcc/tree-ssa-dse.c index e0a944c704a..dfa6d314727 100644 --- a/gcc/tree-ssa-dse.c +++ b/gcc/tree-ssa-dse.c @@ -799,7 +799,8 @@ dse_classify_store (ao_ref *ref, gimple *stmt, return DSE_STORE_LIVE; auto_vec<gimple *, 10> defs; - gimple *phi_def = NULL; + gimple *first_phi_def = NULL; + gimple *last_phi_def = NULL; FOR_EACH_IMM_USE_STMT (use_stmt, ui, defvar) { /* Limit stmt walking. */ @@ -825,7 +826,9 @@ dse_classify_store (ao_ref *ref, gimple *stmt, SSA_NAME_VERSION (PHI_RESULT (use_stmt)))) { defs.safe_push (use_stmt); - phi_def = use_stmt; + if (!first_phi_def) + first_phi_def = use_stmt; + last_phi_def = use_stmt; } } /* If the statement is a use the store is not dead. */ @@ -889,6 +892,8 @@ dse_classify_store (ao_ref *ref, gimple *stmt, gimple *def = defs[i]; gimple *use_stmt; use_operand_p use_p; + tree vdef = (gimple_code (def) == GIMPLE_PHI + ? gimple_phi_result (def) : gimple_vdef (def)); /* If the path to check starts with a kill we do not need to process it further. ??? With byte tracking we need only kill the bytes currently @@ -901,8 +906,7 @@ dse_classify_store (ao_ref *ref, gimple *stmt, } /* If the path ends here we do not need to process it further. This for example happens with calls to noreturn functions. */ - else if (gimple_code (def) != GIMPLE_PHI - && has_zero_uses (gimple_vdef (def))) + else if (has_zero_uses (vdef)) { /* But if the store is to global memory it is definitely not dead. */ @@ -912,12 +916,13 @@ dse_classify_store (ao_ref *ref, gimple *stmt, } /* In addition to kills we can remove defs whose only use is another def in defs. That can only ever be PHIs of which - we track a single for simplicity reasons (we fail for multiple - PHIs anyways). We can also ignore defs that feed only into + we track two for simplicity reasons, the first and last in + {first,last}_phi_def (we fail for multiple PHIs anyways). + We can also ignore defs that feed only into already visited PHIs. */ - else if (gimple_code (def) != GIMPLE_PHI - && single_imm_use (gimple_vdef (def), &use_p, &use_stmt) - && (use_stmt == phi_def + else if (single_imm_use (vdef, &use_p, &use_stmt) + && (use_stmt == first_phi_def + || use_stmt == last_phi_def || (gimple_code (use_stmt) == GIMPLE_PHI && bitmap_bit_p (visited, SSA_NAME_VERSION </cut>

4 years, 5 months

3
2
0 0

[ACTIVITY] 14 - 25 June 2021

by Prathamesh Kulkarni

== This Week == * PR97906 (missed lowering to vac) - Committed patch. * PR66791 (replace builtins with vector extensions in neon intrinsics): - Committed patch for vceq - Submitted patch for vca - Submitted patch for vdup * PR98435 (missed opt in expanding vector constructor) - Patch conditionally approved by Kyrill == Next Week == - PR98435: Address changes and commit the fix. - PR66791: Continue with intrinsics.

4 years, 5 months

1
0
0 0

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O2 - Build # 21 - Successful!

by ci_notify＠linaro.org

Successfully identified regression in *gcc* in CI configuration tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2. So far, this commit has regressed CI configurations: - tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2 Culprit: <cut> commit 87a7d10c2e9ec34a276e6acb5d2282a35b9cfafb Author: GCC Administrator <gccadmin(a)gcc.gnu.org> Date: Sat May 15 00:16:27 2021 +0000 Daily bump. </cut> Results regressed to (for first_bad == 87a7d10c2e9ec34a276e6acb5d2282a35b9cfafb) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2 -- artifacts/build-87a7d10c2e9ec34a276e6acb5d2282a35b9cfafb/results_id: 1 # 459.GemsFDTD,GemsFDTD_base.default regressed by 103 from (for last_good == 0e3702f8daeec5897982d185650b78a5c1c53c25) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2 -- artifacts/build-0e3702f8daeec5897982d185650b78a5c1c53c25/results_id: 1 Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of last_good: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2/533 Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of first_bad: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2/530 Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Configuration details: Reproduce builds: <cut> mkdir investigate-gcc-87a7d10c2e9ec34a276e6acb5d2282a35b9cfafb cd investigate-gcc-87a7d10c2e9ec34a276e6acb5d2282a35b9cfafb git clone https://git.linaro.org/toolchain/jenkins-scripts mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh cd gcc # Reproduce first_bad build git checkout --detach 87a7d10c2e9ec34a276e6acb5d2282a35b9cfafb ../artifacts/test.sh # Reproduce last_good build git checkout --detach 0e3702f8daeec5897982d185650b78a5c1c53c25 ../artifacts/test.sh cd .. </cut> History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Full commit (up to 1000 lines): <cut> commit 87a7d10c2e9ec34a276e6acb5d2282a35b9cfafb Author: GCC Administrator <gccadmin(a)gcc.gnu.org> Date: Sat May 15 00:16:27 2021 +0000 Daily bump. --- contrib/ChangeLog | 14 +++++++++++ gcc/ChangeLog | 55 ++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 6 +++++ gcc/c-family/ChangeLog | 4 ++++ gcc/cp/ChangeLog | 21 +++++++++++++++++ gcc/fortran/ChangeLog | 25 ++++++++++++++++++++ gcc/testsuite/ChangeLog | 42 +++++++++++++++++++++++++++++++++ libgomp/ChangeLog | 4 ++++ libphobos/ChangeLog | 5 ++++ maintainer-scripts/ChangeLog | 4 ++++ 11 files changed, 181 insertions(+), 1 deletion(-) diff --git a/contrib/ChangeLog b/contrib/ChangeLog index f7c1e867879..8e393b7ed72 100644 --- a/contrib/ChangeLog +++ b/contrib/ChangeLog @@ -1,3 +1,17 @@ +2021-05-14 Martin Liska <mliska(a)suse.cz> + + * download_prerequisites: Use version 4.1.0. + +2021-05-14 Jakub Jelinek <jakub(a)redhat.com> + + * gcc-changelog/git_update_version.py: Remove releases/gcc-8 from + active_refs. + +2021-05-14 Martin Liska <mliska(a)suse.cz> + + * gcc-changelog/git_commit.py: Support Co-Authored-By before + a first ChangeLog entry. + 2021-05-13 Martin Liska <mliska(a)suse.cz> * mklog.py: Put PR entries before all ChangeLog entries diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3b937d4d66f..dfa8ae2824f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,58 @@ +2021-05-14 Jason Merrill <jason(a)redhat.com> + + * intl.h: Add comments. + +2021-05-14 Kyrylo Tkachov <kyrylo.tkachov(a)arm.com> + + * config/aarch64/aarch64-simd.md + (aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Split into... + (aarch64_sqdmlsl2_lane<mode>_internal): ... This... + (aarch64_sqdmlal2_lane<mode>_internal): ... And this. + (aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Split into ... + (aarch64_sqdmlsl2_laneq<mode>_internal): ... This... + (aarch64_sqdmlal2_laneq<mode>_internal): ... And this. + (aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal): Split into... + (aarch64_sqdmlsl2_n<mode>_internal): ... This... + (aarch64_sqdmlal2_n<mode>_internal): ... And this. + +2021-05-14 Prathamesh Kulkarni <prathamesh.kulkarni(a)linaro.org> + + PR target/66791 + * config/arm/arm_neon.h (vtst_s8): Replace call to vtst builtin with it's + boolean logic equivalent. + (vtst_s16): Likewise. + (vtst_s32): Likewise. + (vtst_u8): Likewise. + (vtst_u16): Likewise. + (vtst_u32): Likewise. + (vtst_p8): Likewise. + (vtst_p16): Likewise. + (vtstq_s8): Likewise. + (vtstq_s16): Likewise. + (vtstq_s32): Likewise. + (vtstq_u8): Likewise. + (vtstq_u16): Likewise. + (vtstq_u32): Likewise. + (vtstq_p8): Likewise. + (vtstq_p16): Likewise. + * config/arm/arm_neon_builtins.def: Remove entry for vtst. + * config/arm/neon.md (neon_vtst<mode>): Remove pattern. + +2021-05-14 Kyrylo Tkachov <kyrylo.tkachov(a)arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_sqdmlal2<mode>): Merge into... + (aarch64_sqdml<SBINQOPS:as>l2<mode>): ... This. + (aarch64_sqdmlsl2<mode>): Delete. + (aarch64_sqdmlal2_lane<mode>): Merge this... + (aarch64_sqdmlsl2_lane<mode>): ... And this... + (aarch64_sqdml<SBINQOPS:as>l2_lane<mode>): ... Into this. + (aarch64_sqdmlal2_laneq<mode>): Merge this... + (aarch64_sqdmlsl2_laneq<mode>): ... And this... + (aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>): ... Into this. + (aarch64_sqdmlal2_n<mode>): Merge this... + (aarch64_sqdmlsl2_n<mode>): ... And this... + (aarch64_sqdml<SBINQOPS:as>l2_n<mode>): ... Into this. + 2021-05-13 Martin Sebor <msebor(a)redhat.com> PR middle-end/100574 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 552c3b209c0..40eb1cad583 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20210514 +20210515 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 2279e46b775..514682006a7 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,9 @@ +2021-05-14 Martin Liska <mliska(a)suse.cz> + + * doc/Makefile: Add gnat-style target. + * doc/share/conf.py: Likewise. + * doc/gnat-style.rst: New file. + 2021-05-12 Bob Duff <duff(a)adacore.com> PR ada/100564 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index d33ad4a4c57..7fc64a513d5 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,7 @@ +2021-05-14 Martin Liska <mliska(a)suse.cz> + + * c.opt: Add Warning keyword for 2 options. + 2021-05-13 Martin Liska <mliska(a)suse.cz> PR middle-end/100504 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 5a8a650d3d7..48425b9dc67 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,24 @@ +2021-05-14 Jason Merrill <jason(a)redhat.com> + + PR c++/95870 + * pt.c (enclosing_instantiation_of): Just compare + DECL_SOURCE_LOCATION. + (regenerate_decl_from_template): Copy DECL_SOURCE_LOCATION. + +2021-05-14 Marek Polacek <polacek(a)redhat.com> + Jason Merrill <jason(a)redhat.com> + + PR c++/99032 + * cp-tree.h (any_non_type_attribute_p): Declare. + * decl.c (grokdeclarator): Diagnose when an attribute appertains to + a friend declaration that is not a definition. + * decl2.c (any_non_type_attribute_p): New. + * parser.c (cp_parser_decl_specifier_seq): Diagnose standard attributes + in the middle of decl-specifiers. + (cp_parser_elaborated_type_specifier): Diagnose when an attribute + appertains to a friend declaration that is not a definition. + (cp_parser_member_declaration): Likewise. + 2021-05-12 Marek Polacek <polacek(a)redhat.com> * pt.c (tsubst_copy_and_build): Add warn_int_in_bool_context diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 71cc3d86491..781dedd8220 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,28 @@ +2021-05-14 Tobias Burnus <tobias(a)codesourcery.com> + + * dump-parse-tree.c (show_omp_node, show_code_node): Handle + EXEC_OMP_PARALLEL_MASTER. + * frontend-passes.c (gfc_code_walker): Likewise. + * gfortran.h (enum gfc_statement): Add ST_OMP_PARALLEL_MASTER and + ST_OMP_END_PARALLEL_MASTER. + (enum gfc_exec_op): Add EXEC_OMP_PARALLEL_MASTER.. + * match.h (gfc_match_omp_parallel_master): Handle it. + * openmp.c (gfc_match_omp_parallel_master, resolve_omp_clauses, + omp_code_to_statement, gfc_resolve_omp_directive): Likewise. + * parse.c (decode_omp_directive, case_exec_markers, + gfc_ascii_statement, parse_omp_structured_block, + parse_executable): Likewise. + * resolve.c (gfc_resolve_blocks, gfc_resolve_code): Likewise. + * st.c (gfc_free_statement): Likewise. + * trans-openmp.c (gfc_trans_omp_parallel_master, + gfc_trans_omp_workshare, gfc_trans_omp_directive): Likewise. + * trans.c (trans_code): Likewise. + +2021-05-14 Tobias Burnus <tobias(a)codesourcery.com> + + * resolve.c (resolve_symbol): Handle implicit SAVE of main-program + for vars in 'omp threadprivate' and 'omp declare target'. + 2021-05-10 Martin Liska <mliska(a)suse.cz> * decl.c (variable_decl): Use startswith diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9dfab7b873d..564795068b0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,45 @@ +2021-05-14 Tobias Burnus <tobias(a)codesourcery.com> + + * gfortran.dg/gomp/parallel-master-1.f90: New test. + * gfortran.dg/gomp/parallel-master-2.f90: New test. + +2021-05-14 Tobias Burnus <tobias(a)codesourcery.com> + + * gfortran.dg/gomp/implicit-save.f90: New test. + +2021-05-14 Jakub Jelinek <jakub(a)redhat.com> + + PR c++/95226 + * g++.dg/cpp1y/pr95226.C: New test. + +2021-05-14 Jakub Jelinek <jakub(a)redhat.com> + + PR c++/94616 + * g++.dg/cpp0x/pr94616.C: New test. + +2021-05-14 Jakub Jelinek <jakub(a)redhat.com> + + PR c++/90019 + * g++.dg/cpp0x/sfinae68.C: New test. + +2021-05-14 Jakub Jelinek <jakub(a)redhat.com> + + * g++.dg/cpp1y/pr88872.C: New test. + +2021-05-14 Michael de Lang <kingoipo(a)gmail.com> + + * g++.dg/tsan/pthread_cond_clockwait.C: New test. + +2021-05-14 Marek Polacek <polacek(a)redhat.com> + Jason Merrill <jason(a)redhat.com> + + PR c++/99032 + * g++.dg/cpp0x/friend7.C: New test. + * g++.dg/cpp0x/gen-attrs-4.C: Add dg-error. + * g++.dg/cpp0x/gen-attrs-39-1.C: Likewise. + * g++.dg/cpp0x/gen-attrs-74.C: New test. + * g++.dg/ext/attrib63.C: New test. + 2021-05-13 Martin Sebor <msebor(a)redhat.com> PR tree-optimization/93100 diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog index 1daf0c82f2c..424c574dce8 100644 --- a/libgomp/ChangeLog +++ b/libgomp/ChangeLog @@ -1,3 +1,7 @@ +2021-05-14 Tobias Burnus <tobias(a)codesourcery.com> + + * testsuite/libgomp.fortran/parallel-master.f90: New test. + 2021-05-13 Martin Liska <mliska(a)suse.cz> PR testsuite/100569 diff --git a/libphobos/ChangeLog b/libphobos/ChangeLog index 7574416b9aa..7b57d92f64a 100644 --- a/libphobos/ChangeLog +++ b/libphobos/ChangeLog @@ -1,3 +1,8 @@ +2021-05-14 Bernd Edlinger <bernd.edlinger(a)hotmail.de> + + * src/std/process.d (unittest): Remove tmpname on exit. + * src/MERGE: Merge upstream phobos 63f4caa90. + 2021-05-13 Iain Buclaw <ibuclaw(a)gdcproject.org> * libdruntime/MERGE: Merge upstream druntime 98c6ff0c. diff --git a/maintainer-scripts/ChangeLog b/maintainer-scripts/ChangeLog index ab18cfd905d..8f306552396 100644 --- a/maintainer-scripts/ChangeLog +++ b/maintainer-scripts/ChangeLog @@ -1,3 +1,7 @@ +2021-05-14 Jakub Jelinek <jakub(a)redhat.com> + + * crontab: Stop doing gcc-8 snapshots. + 2021-04-20 Jakub Jelinek <jakub(a)redhat.com> * crontab: Snapshots from trunk are now GCC 12 related. </cut>

4 years, 5 months

1
0
0 0

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O2_LTO - Build # 18 - Successful!

by ci_notify＠linaro.org

Successfully identified regression in *glibc* in CI configuration tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO. So far, this commit has regressed CI configurations: - tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO Culprit: <cut> commit f79f2065817e080f65f3c3a2fee966f5a97f1746 Author: Florian Weimer <fweimer(a)redhat.com> Date: Wed Apr 21 19:49:50 2021 +0200 nptl: Move legacy unwinding implementation into libc It is still used internally. Since unwinding is now available unconditionally, avoid indirect calls through function pointers loaded from the stack by inlining the non-cancellation cleanup code. This avoids a regression in security hardening. The out-of-line __libc_cleanup_routine implementation is no longer needed because the inline definition is now static __always_inline. Reviewed-by: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> </cut> Results regressed to (for first_bad == f79f2065817e080f65f3c3a2fee966f5a97f1746) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO -- artifacts/build-f79f2065817e080f65f3c3a2fee966f5a97f1746/results_id: 1 # 410.bwaves,bwaves_base.default regressed by 104 from (for last_good == 5715c29e91076800418833f2196f2082f439da75) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO -- artifacts/build-5715c29e91076800418833f2196f2082f439da75/results_id: 1 Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of last_good: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2_LTO/461 Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of first_bad: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2_LTO/470 Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Configuration details: Reproduce builds: <cut> mkdir investigate-glibc-f79f2065817e080f65f3c3a2fee966f5a97f1746 cd investigate-glibc-f79f2065817e080f65f3c3a2fee966f5a97f1746 git clone https://git.linaro.org/toolchain/jenkins-scripts mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh cd glibc # Reproduce first_bad build git checkout --detach f79f2065817e080f65f3c3a2fee966f5a97f1746 ../artifacts/test.sh # Reproduce last_good build git checkout --detach 5715c29e91076800418833f2196f2082f439da75 ../artifacts/test.sh cd .. </cut> History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Full commit (up to 1000 lines): <cut> commit f79f2065817e080f65f3c3a2fee966f5a97f1746 Author: Florian Weimer <fweimer(a)redhat.com> Date: Wed Apr 21 19:49:50 2021 +0200 nptl: Move legacy unwinding implementation into libc It is still used internally. Since unwinding is now available unconditionally, avoid indirect calls through function pointers loaded from the stack by inlining the non-cancellation cleanup code. This avoids a regression in security hardening. The out-of-line __libc_cleanup_routine implementation is no longer needed because the inline definition is now static __always_inline. Reviewed-by: Adhemerval Zanella <adhemerval.zanella(a)linaro.org> --- nptl/Versions | 2 ++ nptl/cleanup_defer_compat.c | 56 ++--------------------------------- nptl/libc-cleanup.c | 64 ++++++++++++++++++++++++++++++++++++++-- nptl/nptl-init.c | 2 -- sysdeps/nptl/libc-lock.h | 59 ++++++++++++++++++------------------ sysdeps/nptl/libc-lockP.h | 26 +--------------- sysdeps/nptl/pthread-functions.h | 4 --- 7 files changed, 97 insertions(+), 116 deletions(-) diff --git a/nptl/Versions b/nptl/Versions index 60202b4969..2e5a964b11 100644 --- a/nptl/Versions +++ b/nptl/Versions @@ -87,6 +87,8 @@ libc { __futex_abstimed_wait64; __futex_abstimed_wait_cancelable64; __libc_alloca_cutoff; + __libc_cleanup_pop_restore; + __libc_cleanup_push_defer; __libc_dl_error_tsd; __libc_pthread_init; __lll_clocklock_elision; diff --git a/nptl/cleanup_defer_compat.c b/nptl/cleanup_defer_compat.c index 49ef53ea60..1957318208 100644 --- a/nptl/cleanup_defer_compat.c +++ b/nptl/cleanup_defer_compat.c @@ -17,41 +17,15 @@ <https://www.gnu.org/licenses/>. */ #include "pthreadP.h" - +#include <libc-lock.h> void _pthread_cleanup_push_defer (struct _pthread_cleanup_buffer *buffer, void (*routine) (void *), void *arg) { - struct pthread *self = THREAD_SELF; - buffer->__routine = routine; buffer->__arg = arg; - buffer->__prev = THREAD_GETMEM (self, cleanup); - - int cancelhandling = THREAD_GETMEM (self, cancelhandling); - - /* Disable asynchronous cancellation for now. */ - if (__glibc_unlikely (cancelhandling & CANCELTYPE_BITMASK)) - while (1) - { - int curval = THREAD_ATOMIC_CMPXCHG_VAL (self, cancelhandling, - cancelhandling - & ~CANCELTYPE_BITMASK, - cancelhandling); - if (__glibc_likely (curval == cancelhandling)) - /* Successfully replaced the value. */ - break; - - /* Prepare for the next round. */ - cancelhandling = curval; - } - - buffer->__canceltype = (cancelhandling & CANCELTYPE_BITMASK - ? PTHREAD_CANCEL_ASYNCHRONOUS - : PTHREAD_CANCEL_DEFERRED); - - THREAD_SETMEM (self, cleanup, buffer); + __libc_cleanup_push_defer (buffer); } strong_alias (_pthread_cleanup_push_defer, __pthread_cleanup_push_defer) @@ -60,31 +34,7 @@ void _pthread_cleanup_pop_restore (struct _pthread_cleanup_buffer *buffer, int execute) { - struct pthread *self = THREAD_SELF; - - THREAD_SETMEM (self, cleanup, buffer->__prev); - - int cancelhandling; - if (__builtin_expect (buffer->__canceltype != PTHREAD_CANCEL_DEFERRED, 0) - && ((cancelhandling = THREAD_GETMEM (self, cancelhandling)) - & CANCELTYPE_BITMASK) == 0) - { - while (1) - { - int curval = THREAD_ATOMIC_CMPXCHG_VAL (self, cancelhandling, - cancelhandling - | CANCELTYPE_BITMASK, - cancelhandling); - if (__glibc_likely (curval == cancelhandling)) - /* Successfully replaced the value. */ - break; - - /* Prepare for the next round. */ - cancelhandling = curval; - } - - CANCELLATION_P (self); - } + __libc_cleanup_pop_restore (buffer); /* If necessary call the cleanup routine after we removed the current cleanup block from the list. */ diff --git a/nptl/libc-cleanup.c b/nptl/libc-cleanup.c index 61f97eceda..14ccfe9285 100644 --- a/nptl/libc-cleanup.c +++ b/nptl/libc-cleanup.c @@ -17,11 +17,69 @@ <https://www.gnu.org/licenses/>. */ #include "pthreadP.h" +#include <tls.h> +#include <libc-lock.h> +void +__libc_cleanup_push_defer (struct _pthread_cleanup_buffer *buffer) +{ + struct pthread *self = THREAD_SELF; + + buffer->__prev = THREAD_GETMEM (self, cleanup); + + int cancelhandling = THREAD_GETMEM (self, cancelhandling); + + /* Disable asynchronous cancellation for now. */ + if (__glibc_unlikely (cancelhandling & CANCELTYPE_BITMASK)) + while (1) + { + int curval = THREAD_ATOMIC_CMPXCHG_VAL (self, cancelhandling, + cancelhandling + & ~CANCELTYPE_BITMASK, + cancelhandling); + if (__glibc_likely (curval == cancelhandling)) + /* Successfully replaced the value. */ + break; + + /* Prepare for the next round. */ + cancelhandling = curval; + } + + buffer->__canceltype = (cancelhandling & CANCELTYPE_BITMASK + ? PTHREAD_CANCEL_ASYNCHRONOUS + : PTHREAD_CANCEL_DEFERRED); + + THREAD_SETMEM (self, cleanup, buffer); +} +libc_hidden_def (__libc_cleanup_push_defer) void -__libc_cleanup_routine (struct __pthread_cleanup_frame *f) +__libc_cleanup_pop_restore (struct _pthread_cleanup_buffer *buffer) { - if (f->__do_it) - f->__cancel_routine (f->__cancel_arg); + struct pthread *self = THREAD_SELF; + + THREAD_SETMEM (self, cleanup, buffer->__prev); + + int cancelhandling; + if (__builtin_expect (buffer->__canceltype != PTHREAD_CANCEL_DEFERRED, 0) + && ((cancelhandling = THREAD_GETMEM (self, cancelhandling)) + & CANCELTYPE_BITMASK) == 0) + { + while (1) + { + int curval = THREAD_ATOMIC_CMPXCHG_VAL (self, cancelhandling, + cancelhandling + | CANCELTYPE_BITMASK, + cancelhandling); + if (__glibc_likely (curval == cancelhandling)) + /* Successfully replaced the value. */ + break; + + /* Prepare for the next round. */ + cancelhandling = curval; + } + + CANCELLATION_P (self); + } } +libc_hidden_def (__libc_cleanup_pop_restore) diff --git a/nptl/nptl-init.c b/nptl/nptl-init.c index 2c7e2222d4..43e2564e59 100644 --- a/nptl/nptl-init.c +++ b/nptl/nptl-init.c @@ -95,8 +95,6 @@ static const struct pthread_functions pthread_functions = .ptr___pthread_key_create = __pthread_key_create, .ptr___pthread_getspecific = __pthread_getspecific, .ptr___pthread_setspecific = __pthread_setspecific, - .ptr__pthread_cleanup_push_defer = __pthread_cleanup_push_defer, - .ptr__pthread_cleanup_pop_restore = __pthread_cleanup_pop_restore, .ptr_nthreads = &__nptl_nthreads, .ptr___pthread_unwind = &__pthread_unwind, .ptr__nptl_deallocate_tsd = __nptl_deallocate_tsd, diff --git a/sysdeps/nptl/libc-lock.h b/sysdeps/nptl/libc-lock.h index dea96121b3..e8a5e68a12 100644 --- a/sysdeps/nptl/libc-lock.h +++ b/sysdeps/nptl/libc-lock.h @@ -143,39 +143,40 @@ typedef struct __libc_lock_recursive_opaque__ __libc_lock_recursive_t; __libc_maybe_call (__pthread_mutex_unlock, (&(NAME).mutex), 0) #endif -/* Note that for I/O cleanup handling we are using the old-style - cancel handling. It does not have to be integrated with C++ since - no C++ code is called in the middle. The old-style handling is - faster and the support is not going away. */ -extern void _pthread_cleanup_push_defer (struct _pthread_cleanup_buffer *buffer, - void (*routine) (void *), void *arg); -extern void _pthread_cleanup_pop_restore (struct _pthread_cleanup_buffer *buffer, - int execute); +/* Put the unwind buffer BUFFER on the per-thread callback stack. The + caller must fill BUFFER->__routine and BUFFER->__arg before calling + this function. */ +void __libc_cleanup_push_defer (struct _pthread_cleanup_buffer *buffer); +libc_hidden_proto (__libc_cleanup_push_defer) +/* Remove BUFFER from the unwind callback stack. The caller must invoke + the callback if desired. */ +void __libc_cleanup_pop_restore (struct _pthread_cleanup_buffer *buffer); +libc_hidden_proto (__libc_cleanup_pop_restore) /* Start critical region with cleanup. */ -#define __libc_cleanup_region_start(DOIT, FCT, ARG) \ - { struct _pthread_cleanup_buffer _buffer; \ - int _avail; \ - if (DOIT) { \ - _avail = PTFAVAIL (_pthread_cleanup_push_defer); \ - if (_avail) { \ - __libc_ptf_call_always (_pthread_cleanup_push_defer, (&_buffer, FCT, \ - ARG)); \ - } else { \ - _buffer.__routine = (FCT); \ - _buffer.__arg = (ARG); \ - } \ - } else { \ - _avail = 0; \ - } +#define __libc_cleanup_region_start(DOIT, FCT, ARG) \ + { bool _cleanup_start_doit; \ + struct _pthread_cleanup_buffer _buffer; \ + /* Non-addressable copy of FCT, so that we avoid indirect calls on \ + the non-unwinding path. */ \ + void (*_cleanup_routine) (void *) = (FCT); \ + _buffer.__arg = (ARG); \ + if (DOIT) \ + { \ + _cleanup_start_doit = true; \ + _buffer.__routine = _cleanup_routine; \ + __libc_cleanup_push_defer (&_buffer); \ + } \ + else \ + _cleanup_start_doit = false; /* End critical region with cleanup. */ -#define __libc_cleanup_region_end(DOIT) \ - if (_avail) { \ - __libc_ptf_call_always (_pthread_cleanup_pop_restore, (&_buffer, DOIT));\ - } else if (DOIT) \ - _buffer.__routine (_buffer.__arg); \ - } +#define __libc_cleanup_region_end(DOIT) \ + if (_cleanup_start_doit) \ + __libc_cleanup_pop_restore (&_buffer); \ + if (DOIT) \ + _cleanup_routine (_buffer.__arg); \ + } /* matches __libc_cleanup_region_start */ /* Hide the definitions which are only supposed to be used inside libc in diff --git a/sysdeps/nptl/libc-lockP.h b/sysdeps/nptl/libc-lockP.h index 63b605dee2..2c928b7a76 100644 --- a/sysdeps/nptl/libc-lockP.h +++ b/sysdeps/nptl/libc-lockP.h @@ -251,32 +251,12 @@ _Static_assert (LLL_LOCK_INITIALIZER == 0, "LLL_LOCK_INITIALIZER != 0"); /* Get once control variable. */ #define __libc_once_get(ONCE_CONTROL) ((ONCE_CONTROL) != PTHREAD_ONCE_INIT) -/* Note that for I/O cleanup handling we are using the old-style - cancel handling. It does not have to be integrated with C++ snce - no C++ code is called in the middle. The old-style handling is - faster and the support is not going away. */ -extern void _pthread_cleanup_push (struct _pthread_cleanup_buffer *buffer, - void (*routine) (void *), void *arg); -extern void _pthread_cleanup_pop (struct _pthread_cleanup_buffer *buffer, - int execute); -extern void _pthread_cleanup_push_defer (struct _pthread_cleanup_buffer *buffer, - void (*routine) (void *), void *arg); -extern void _pthread_cleanup_pop_restore (struct _pthread_cleanup_buffer *buffer, - int execute); - -/* Sometimes we have to exit the block in the middle. */ -#define __libc_cleanup_end(DOIT) \ - if (_avail) { \ - __libc_ptf_call_always (_pthread_cleanup_pop_restore, (&_buffer, DOIT));\ - } else if (DOIT) \ - _buffer.__routine (_buffer.__arg) - /* __libc_cleanup_push and __libc_cleanup_pop depend on exception handling and stack unwinding. */ #ifdef __EXCEPTIONS /* Normal cleanup handling, based on C cleanup attribute. */ -__extern_inline void +static __always_inline void __libc_cleanup_routine (struct __pthread_cleanup_frame *f) { if (f->__do_it) @@ -388,8 +368,6 @@ weak_extern (__pthread_once) weak_extern (__pthread_initialize) weak_extern (__pthread_atfork) weak_extern (__pthread_setcancelstate) -weak_extern (_pthread_cleanup_push_defer) -weak_extern (_pthread_cleanup_pop_restore) # else # pragma weak __pthread_mutex_init # pragma weak __pthread_mutex_destroy @@ -412,8 +390,6 @@ weak_extern (_pthread_cleanup_pop_restore) # pragma weak __pthread_initialize # pragma weak __pthread_atfork # pragma weak __pthread_setcancelstate -# pragma weak _pthread_cleanup_push_defer -# pragma weak _pthread_cleanup_pop_restore # endif #endif diff --git a/sysdeps/nptl/pthread-functions.h b/sysdeps/nptl/pthread-functions.h index 97a5c48939..4268084b66 100644 --- a/sysdeps/nptl/pthread-functions.h +++ b/sysdeps/nptl/pthread-functions.h @@ -57,10 +57,6 @@ struct pthread_functions int (*ptr___pthread_key_create) (pthread_key_t *, void (*) (void *)); void *(*ptr___pthread_getspecific) (pthread_key_t); int (*ptr___pthread_setspecific) (pthread_key_t, const void *); - void (*ptr__pthread_cleanup_push_defer) (struct _pthread_cleanup_buffer *, - void (*) (void *), void *); - void (*ptr__pthread_cleanup_pop_restore) (struct _pthread_cleanup_buffer *, - int); #define HAVE_PTR_NTHREADS unsigned int *ptr_nthreads; void (*ptr___pthread_unwind) (__pthread_unwind_buf_t *) </cut>

4 years, 5 months

3
3
0 0

[ACTIVITY] week ending Jun. 27 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - spent some time trying to get Xen working on MachiatoBin again - almost working, need SMC/HVC passthrough for platform [STR-9] <https://projects.linaro.org/browse/STR-9> QEMU Upstream Work ([UM-2]) =========================== - posted [[PATCH v3 0/2] semihosting/next (SYS_HEAPINFO)] - posted [PULL 0/7] misc fixes (docs, plugins, tests) Message-Id: <20210625091355.25673-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [[PATCH v3 0/2] semihosting/next (SYS_HEAPINFO)] <gnus:nntp+news.gmane.io:gmane.comp.emulators.qemu#20210615165800.23265-1-alex.bennee@linaro.org> [RFC PATCH] semihosting/arm-compat: remove heuristic softmmu SYS_HEAPINFO Message-Id: <20210601090715.22330-1-alex.bennee(a)linaro.org> Other ===== - ARM CCA Announcement Event - Rust Training Completed Reviews [9/9] ======================= [PATCH 00/11] softfloat: Improve denormal handling Message-Id: <20210527041405.391567-1-richard.henderson(a)linaro.org> [PATCH v2 00/28] Convert floatx80 and float128 to FloatParts Message-Id: <20210525150706.294968-1-richard.henderson(a)linaro.org> [PATCH 00/11] softfloat: Improve denormal handling Message-Id: <20210527041405.391567-1-richard.henderson(a)linaro.org> [PATCH v3 00/28] tcg: Clean up code_gen_buffer allocation Message-Id: <20210502231844.1977630-1-richard.henderson(a)linaro.org> Re: [PATCH] replay: fix watchpoint processing for reverse debugging Message-Id: <fc75c7b5-e99c-f558-d24f-519041aa8d46(a)ispras.ru> [Email from Richard Henderson: [PATCH v2 0/8] configure: Change to -std=gnu11] [Email from Richard Henderson: [PATCH v2 0/8] configure: Change to -std=gnu11] <gnus:nntp+news.gmane.io:gmane.comp.emulators.qemu#20210614233143.1221879-1-richard.henderson@linaro.org> [PATCH] i386: load kernel on xen using DMA Message-Id: <20210426034709.595432-1-marmarek(a)invisiblethingslab.com> [PATCH v2 0/2] execlog TCG plugin to log instructions Message-Id: <20210618091101.2802534-1-erdnaxe(a)crans.org> [RFC PATCH v3 0/4] Cache TCG plugin & symbol-resolution API Message-Id: <20210608040532.56449-1-ma.mandourr(a)gmail.com> Absences ======== Current Review Queue ==================== TODO [PATCH 00/26] accel/tcg: Introduce translator_use_goto_tb Message-Id: <20210621013439.1791385-1-richard.henderson(a)linaro.org> ================================================================================================================================= TODO [Email from Mathieu Poirier: [PATCH v2 0/5] virtio: Add vhost-user based RNG] ================================================================================== [Email from Mathieu Poirier: [PATCH v2 0/5] virtio: Add vhost-user based RNG] <gnus:nntp+news.gmane.io:gmane.comp.emulators.qemu#20210614202842.581640-1-mathieu.poirier@linaro.org> TODO [PATCH 0/5] virtio: Add vhost-user based RNG service Message-Id: <20210601200305.1772391-1-mathieu.poirier(a)linaro.org> ========================================================================================================================== TODO [RFC PATCH 0/5] ebpf: Added ebpf helper for libvirtd. -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 25 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Not much this week. Reviewed rth's bswap improvement/cleanup series * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Implemented logical-immediate insns; various vector shifts; VADDLV; some of the scalar shifts that work on general-purpose registers + Fixed a few bugs in already-implemented insns (widening/narrowing load/store, and VRMLALDAVH, VRMLSLDAVH) + Progress: 102/210 (48%) -- PMM

4 years, 5 months

1
0
0 0

[CI-NOTIFY]: TCWG Bisect tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-O2_LTO - Build # 16 - Successful!

by ci_notify＠linaro.org

Successfully identified regression in *gcc* in CI configuration tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO. So far, this commit has regressed CI configurations: - tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO Culprit: <cut> commit de56f95afaaa22c67cbeec780921d63e8b34514e Author: Xionghu Luo <luoxhu(a)linux.ibm.com> Date: Tue May 18 21:34:18 2021 -0500 Run pass_sink_code once more before store_merging Gimple sink code pass runs quite early, there may be some new oppertunities exposed by later gimple optmization passes, this patch runs the sink code pass once more before store_merging. For detailed discussion, please refer to: https://gcc.gnu.org/pipermail/gcc-patches/2020-December/562352.html Tested the SPEC2017 performance on P8LE, 544.nab_r is improved by 2.43%, but no big changes to other cases, GEOMEAN is improved quite small with 0.25%. gcc/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * passes.def: Add sink_code pass before store_merging. * tree-ssa-sink.c (pass_sink_code:clone): New. gcc/testsuite/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * gcc.dg/tree-ssa/ssa-sink-1.c: Adjust. * gcc.dg/tree-ssa/ssa-sink-2.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-3.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-4.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-5.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-6.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-7.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-8.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-9.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-10.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-13.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-14.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-16.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-17.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-18.c: New. </cut> Results regressed to (for first_bad == de56f95afaaa22c67cbeec780921d63e8b34514e) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO -- artifacts/build-de56f95afaaa22c67cbeec780921d63e8b34514e/results_id: 1 # 447.dealII,dealII_base.default regressed by 103 from (for last_good == 39ed6a88c74db5412652f0167d03f71eca4f02fc) # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer: -8 # build_abe linux: -7 # build_abe glibc: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer: -5 # true: 0 # benchmark -O2_LTO -- artifacts/build-39ed6a88c74db5412652f0167d03f71eca4f02fc/results_id: 1 Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of last_good: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2_LTO/381 Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Results ID of first_bad: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2_LTO/350 Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Configuration details: Reproduce builds: <cut> mkdir investigate-gcc-de56f95afaaa22c67cbeec780921d63e8b34514e cd investigate-gcc-de56f95afaaa22c67cbeec780921d63e8b34514e git clone https://git.linaro.org/toolchain/jenkins-scripts mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh cd gcc # Reproduce first_bad build git checkout --detach de56f95afaaa22c67cbeec780921d63e8b34514e ../artifacts/test.sh # Reproduce last_good build git checkout --detach 39ed6a88c74db5412652f0167d03f71eca4f02fc ../artifacts/test.sh cd .. </cut> History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/… Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… Full commit (up to 1000 lines): <cut> commit de56f95afaaa22c67cbeec780921d63e8b34514e Author: Xionghu Luo <luoxhu(a)linux.ibm.com> Date: Tue May 18 21:34:18 2021 -0500 Run pass_sink_code once more before store_merging Gimple sink code pass runs quite early, there may be some new oppertunities exposed by later gimple optmization passes, this patch runs the sink code pass once more before store_merging. For detailed discussion, please refer to: https://gcc.gnu.org/pipermail/gcc-patches/2020-December/562352.html Tested the SPEC2017 performance on P8LE, 544.nab_r is improved by 2.43%, but no big changes to other cases, GEOMEAN is improved quite small with 0.25%. gcc/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * passes.def: Add sink_code pass before store_merging. * tree-ssa-sink.c (pass_sink_code:clone): New. gcc/testsuite/ChangeLog: 2021-05-18 Xionghu Luo <luoxhu(a)linux.ibm.com> * gcc.dg/tree-ssa/ssa-sink-1.c: Adjust. * gcc.dg/tree-ssa/ssa-sink-2.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-3.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-4.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-5.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-6.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-7.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-8.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-9.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-10.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-13.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-14.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-16.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-17.c: Ditto. * gcc.dg/tree-ssa/ssa-sink-18.c: New. --- gcc/passes.def | 1 + gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c | 212 ++++++++++++++++++++++++++++ gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c | 15 -- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c | 2 +- gcc/tree-ssa-sink.c | 1 + 17 files changed, 229 insertions(+), 30 deletions(-) diff --git a/gcc/passes.def b/gcc/passes.def index de39fa48b3d..945d2bc797c 100644 --- a/gcc/passes.def +++ b/gcc/passes.def @@ -348,6 +348,7 @@ along with GCC; see the file COPYING3. If not see NEXT_PASS (pass_phiopt, false /* early_p */); NEXT_PASS (pass_fold_builtins); NEXT_PASS (pass_optimize_widening_mul); + NEXT_PASS (pass_sink_code); NEXT_PASS (pass_store_merging); NEXT_PASS (pass_tail_calls); /* If DCE is not run before checking for uninitialized uses, diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c index 411585a6dc4..57b501681f3 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-1.c @@ -7,4 +7,4 @@ foo (int a, int b, int c) return c ? x : a; } /* We should sink the x = a * b calculation into the branch that returns x. */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c index 37e4d2fe687..535cb3208f5 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-10.c @@ -16,4 +16,4 @@ void foo (void) } } -/* { dg-final { scan-tree-dump-times "Sinking # VUSE" 4 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking # VUSE" 4 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c index a65ba35d4ba..584fd91f43a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-13.c @@ -21,5 +21,5 @@ void test () /* We should sink/merge all stores and end up with a single BB. */ -/* { dg-final { scan-tree-dump-times "MEM\[^\n\r\]* = 0;" 3 "sink" } } */ -/* { dg-final { scan-tree-dump-times "<bb " 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "MEM\[^\n\r\]* = 0;" 3 "sink1" } } */ +/* { dg-final { scan-tree-dump-times "<bb " 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c index 771cd4420c4..f5418b06deb 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-14.c @@ -13,5 +13,5 @@ void foo (int b) /* We should have sunk the store and inserted a PHI to merge the stored values. */ -/* { dg-final { scan-tree-dump-times " = PHI" 1 "sink" } } */ -/* { dg-final { scan-tree-dump-times "x = " 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times " = PHI" 1 "sink1" } } */ +/* { dg-final { scan-tree-dump-times "x = " 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c index 610c8d60ebe..012b165fbab 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-16.c @@ -10,5 +10,5 @@ int f(int n) return j; } -/* { dg-final { scan-tree-dump "Sinking j_. = __builtin_ffs" "sink" } } */ +/* { dg-final { scan-tree-dump "Sinking j_. = __builtin_ffs" "sink1" } } */ /* { dg-final { scan-tree-dump "return 2;" "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c index cf2e2a0f766..d0aeeb312cc 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-17.c @@ -12,4 +12,4 @@ int my_f(int a, int b) } /* We should sink the call to pure_f to the if block. */ -/* { dg-final { scan-tree-dump "Sinking # VUSE" "sink" } } */ +/* { dg-final { scan-tree-dump "Sinking # VUSE" "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c new file mode 100644 index 00000000000..421c78eba50 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c @@ -0,0 +1,212 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-sink-stats" } */ + +#include <stdint.h> + +#define HLOG 16 +#define MAX_LIT (1 << 5) +typedef const uint8_t *LZF_HSLOT; +typedef LZF_HSLOT LZF_STATE[1 << (HLOG)]; + +int +compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) +{ + LZF_STATE htab; + + uint8_t *ip = in_data; + uint8_t *op = out_data; + uint8_t *in_end = ip + in_len; + uint8_t *out_end = op + out_len; + uint8_t *ref; + + unsigned long off; + unsigned int hval; + int lit; + + if (!in_len || !out_len) + return 0; + + lit = 0; + op++; + hval = (((ip[0]) << 8) | ip[1]); + + while (ip < in_end - 2) + { + uint8_t *hslot; + + hval = (((hval) << 8) | ip[2]); + hslot = (uint8_t*)(htab + (((hval >> (3 * 8 - 16)) - hval * 5) & ((1 << (16)) - 1))); + + ref = *hslot + in_data; + *hslot = ip - in_data; + + if (1 && (off = ip - ref - 1) < (1 << 13) && ref > in_data + && ref[2] == ip[2] + && ((ref[1] << 8) | ref[0]) == ((ip[1] << 8) | ip[0])) + { + unsigned int len = 2; + unsigned int maxlen = in_end - ip - len; + maxlen + = maxlen > ((1 << 8) + (1 << 3)) ? ((1 << 8) + (1 << 3)) : maxlen; + + if ((op + 3 + 1 >= out_end) != 0) + if (op - !lit + 3 + 1 >= out_end) + return 0; + + op[-lit - 1] = lit - 1; + op -= !lit; + + for (;;) + { + if (maxlen > 16) + { + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + len++; + if (ref[len] != ip[len]) + break; + } + + do + { + len++; + } + while (len < maxlen && ip[len] == ref[len]); + + break; + } + + len -= 2; + ip++; + + if (len < 7) + { + *op++ = (off >> 8) + (len << 5); + } + else + { + *op++ = (off >> 8) + (7 << 5); + *op++ = len - 7; + } + *op++ = off; + lit = 0; + op++; + ip += len + 1; + + if (ip >= in_end - 2) + break; + + --ip; + --ip; + + hval = (((ip[0]) << 8) | ip[1]); + hval = (((hval) << 8) | ip[2]); + htab[(((hval >> (3 * 8 - 16)) - hval * 5) & ((1 << (16)) - 1))] + = (LZF_HSLOT)(ip - in_data); + ip++; + + hval = (((hval) << 8) | ip[2]); + htab[(((hval >> (3 * 8 - 16)) - hval * 5) & ((1 << (16)) - 1))] + = (LZF_HSLOT)(ip - in_data); + ip++; + } + else + { + if (op >= out_end) + return 0; + + lit++; + *op++ = *ip++; + + if (lit == (1 << 5)) + { + op[-lit - 1] = lit - 1; + lit = 0; + op++; + } + } + } + if (op + 3 > out_end) /* at most 3 bytes can be missing here */ + return 0; + + while (ip < in_end) + { + lit++; + *op++ = *ip++; + if (lit == MAX_LIT) + { + op[-lit - 1] = lit - 1; /* stop run */ + lit = 0; + op++; /* start run */ + } + } + + op[-lit - 1] = lit - 1; /* end run */ + op -= !lit; /* undo run if length is zero */ + + return op - out_data; + } + + /* For this case, pass sink2 sinks statements from hot loop header to loop + exits after gimple loop optimizations, which generates instructions executed + each iteration in loop, but the results are used outside of loop: + With -m64, + "Sinking _367 = (uint8_t *) _320; + from bb 31 to bb 90 + Sinking _320 = _321 + ivtmp.25_326; + from bb 31 to bb 90 + Sinking _321 = (unsigned long) ip_229; + from bb 31 to bb 90 + Sinking len_158 = _322 + 4294967295; + from bb 31 to bb 33" + When -m32, Power and X86 will sink 3 instructions, but arm ilp32 couldn't + sink due to ivopts chooses two IV candidates instead of one, which is + expected, so this case is restricted to lp64 only so far. */ + + /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c index 6aa5a182a3a..a0b4734b1e0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-2.c @@ -9,4 +9,4 @@ bar (int a, int b, int c) return y; } /* We should sink the x = a * b calculation into the else branch */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c index 599997e0e6b..e69de29bb2d 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-3.c @@ -1,15 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-sink-stats" } */ -extern void foo(int a); -int -main (int argc) -{ - int a; - a = argc + 1; - if (argc + 3) - { - foo (a); - } -} -/* We should sink the a = argc + 1 calculation into the if branch */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c index 784edd2fc87..1e3cfa93fa8 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-4.c @@ -17,4 +17,4 @@ main (int argc) foo2 (a); } /* We should sink the first a = b + c calculation into the else branch */ -/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements: 1" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c index dbdde39add6..f04da5da9b0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-5.c @@ -44,4 +44,4 @@ void foo(int16_t runs[], uint8_t alpha[], int x, int count) } /* We should not sink the next_runs = runs + x calculation after the loop. */ -/* { dg-final { scan-tree-dump-times "Sunk statements:" 0 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sunk statements:" 0 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c index 1abae9f7943..31f5af330f9 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-6.c @@ -14,4 +14,4 @@ int foo(int *a, int r) /* *a = 1 should be sunk to the else block. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c index ec3288f4e69..bd748442edc 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-7.c @@ -15,4 +15,4 @@ int foo(int *a, int r, short *b) /* *a = 1 should be sunk to the else block. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c index 48af4218fc0..4b23b567fd0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-8.c @@ -24,4 +24,4 @@ int foo(int *a, int r, short *b) /* *a = 1 should be sunk into the default case. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c index 509a76330a4..32bfc81741a 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-9.c @@ -15,4 +15,4 @@ int foo(int *a, int r, int *b) /* *a = 1 should be sunk to the else block. */ -/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink" } } */ +/* { dg-final { scan-tree-dump-times "Sinking" 1 "sink1" } } */ diff --git a/gcc/tree-ssa-sink.c b/gcc/tree-ssa-sink.c index d33e56ef915..d252cbb5c51 100644 --- a/gcc/tree-ssa-sink.c +++ b/gcc/tree-ssa-sink.c @@ -819,6 +819,7 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { return flag_tree_sink != 0; } virtual unsigned int execute (function *); + opt_pass *clone (void) { return new pass_sink_code (m_ctxt); } }; // class pass_sink_code </cut>

4 years, 5 months

1
0
0 0

Flang buildbot workers

by Andrzej Warzynski

Hi, I've just noticed that all of Flang's buildbot workers managed by Linaro are offline: https://lab.llvm.org/buildbot/#/builders (type "flang" in the search box). As 8 out of 10 Flang's workers are managed by Linaro, in practice this means that we have almost no testing :( Please, could you look into this or let me know who to get in touch with? Thank you, -Andrzej IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 5 months

3
8
0 0

[ACTIVITY] week ending 20 Jun 2021

by Richard Henderson

[UM-2] * Version 2 of signal trampolines, * Version 1 of vdso, * RFC patch set for #360 (unaligned mmio), * Beginning on #404 (breakpoint slowdown), - convert cris, nios2, avr to translator loop. - translator_use_goto_tb Both of these, working toward improving the recognition of pc's with bp's, and avoiding the need for any tb flushing at all. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] 14-18 June 2021

by Christophe Lyon

== Progress == * GCC - MVE/vectorization: committed patches for vec_pack / vec_unpack - handling feedback on patch for PR 100757 * GCC upstream validation: - reported a couple of regressions == Next == Now leaving Linaro, hopefully I can continue to work on: * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M Thanks for the great time at Linaro!

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 18 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Usual code review and pull request wrangling (nothing major this week) + Added information to our documentation about what Arm architecture features our emulation supports (we get asked this from time to time, and users shouldn't have to dig through back issues of the Changelogs or decipher the ID register updates in the source code...) + Investigated some bugs in v8.1M VLDR/VSTR sysreg detected by trying to run some gcc test cases under QEMU: sent patches + KVM Forum programme committee meeting & voting on talk abstracts * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Fixed various issues in the first-part-of-MVE patchset; it's now through code review and ready to go in + Started looking at the logical-immediate insns + Progress meter: 74/210 (35%) (still) -- PMM

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending 13 Jun 2021

by Richard Henderson

[UM-2] Upstream bugs: #390, fix posted #403, fix posted #360, lots of investigation, and work on updating a patch from 2017. I have a workable change, which ought to be improved. Reorg for tcg bswap opcode. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] 7-11 June 2021

by Christophe Lyon

== Progress == * GCC - MVE/vectorization: committed patches for vhadd/vrhadd and vclz - handling feedback on patch for vec_pack / vec_unpack - PR 100757 * GCC upstream validation: - reported a couple of regressions == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 10 June

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] + Code review: + v4 of Shashi's ITS series. I think this is getting pretty close to good to go in now. * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Completed implementation of PSR.ECI handling + Implemented VADDV + Sent out an interim patchset for early code review (55 patches, ~3400 lines, covers about 35% of the ISA) + Started working through the code review comments from rth + Progress meter: 74/210 (35%) -- PMM

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending 6 June 2021

by Richard Henderson

[UM-2] * Refresh tci patch set. * Review: - target/s390 vector enhancements - arm refactor * Knocked up a tcg patch for Peter's MVE work. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] 31 May - 4 June 2021

by Prathamesh Kulkarni

== This Week == * GCC (1) PR66791 (replace builtins with gcc vector extensions): - Waiting for feedback on vmul_n patch - Created patch for vector comparison ops. (2) PR97906 (missed lowering to vacge) - Submitted patch upstream. (3) PR98435 (missed optimization in expanding vec constructor) - Submitted patch upstream. * Sick leave - Off on thursday. == Next Week == - Continue with PR66791 - Address comments for PR97906 and PR98435

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending Jun. 6 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted [RFC PATCH] configure: allow the overriding of default-config in the build Message-Id: <20210528163116.31902-1-alex.bennee(a)linaro.org> - posted [PATCH v16 00/99] arm tcg/kvm refactor and split with kvm only support Message-Id: <20210604155312.15902-1-alex.bennee(a)linaro.org> [STR-9] <https://projects.linaro.org/browse/STR-9> QEMU Device and Machine Models ([QEMU-418]) =========================================== - started prepping v3 of the kvm-unit-tests [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] semihosting/arm-compat: remove heuristic softmmu SYS_HEAPINFO Message-Id: <20210601090715.22330-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [5/5] ======================= [RFC PATCH 0/3] Cache modelling TCG plugin Message-Id: <20210529152203.40358-1-ma.mandourr(a)gmail.com> [PATCH v2 00/28] Convert floatx80 and float128 to FloatParts Message-Id: <20210525150706.294968-1-richard.henderson(a)linaro.org> [PATCH v7 00/27] TCI fixes and cleanups Message-Id: <20210601150106.12761-1-richard.henderson(a)linaro.org> [PATCH v8 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210526170432.343588-1-philmd(a)redhat.com> [PATCH v2 00/12] hw: Various Kconfig fixes Message-Id: <20210515173716.358295-1-philmd(a)redhat.com> Absences ======== Current Review Queue ==================== TODO [PATCH 0/5] virtio: Add vhost-user based RNG service Message-Id: <20210601200305.1772391-1-mathieu.poirier(a)linaro.org> ========================================================================================================================== TODO [PATCH v2 00/11] linux-user changes to run docker Message-Id: <20210531055019.10149-1-yamamoto(a)midokura.com> ================================================================================================================ TODO [PATCH V5 0/2] Virtio support for toolstack on Arm (Was "IOREQ feature (+ virtio-mmio) on Arm") Message-Id: <1621603005-5799-1-git-send-email-olekstysh(a)gmail.com> ====================================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== -- Alex Bennée

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 4 Jun

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] + Code review: - reviewed the easy half of the "aarch64 support for osx hvf accelerator" patchseries - RTH's bfloat16 support series + Misc bugs: - Sent a patchset fixing a compile failure reported by MS when the 'virt' board is not enabled (requires a custom local config) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Working through the details of how PSR.ECI works for resuming half-executed insns (annoyingly awkward to implement for a subfeature that will almost never get used...). I have most of an implementation now but it needs a bit of new functionality in TCG ("throw away any TCG ops we just generated and rewind to point X") which RTH hasn't written yet :-) + None of that work corresponds to adding more insn patterns, so no change on the Progress meter: 73/210 (34%) -- PMM

4 years, 6 months

1
0
0 0

[ACTIVITY] 31 May - 4 June 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - reported a couple of regressions * GCC - MVE/vectorization: committed patches for vans - submitted patch for vhadd/vrhadd - WIP on vclz / vec_pack / vec_unpack - PR 100757 == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

4 years, 6 months

1
0
0 0

[ACTIVITY] 24-28 May 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - reported a couple of regressions * GCC - MVE/vectorization: committed patches for vld2/vst2, vld4/st4, vaddv - WIP on vhadd/vrhadd == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending May. 30 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - more work on getting [arm refactor] ready for posting - posted [RFC PATCH] configure: allow the overriding of default-config in the build Message-Id: <20210528163116.31902-1-alex.bennee(a)linaro.org> [arm refactor] <https://github.com/stsquad/qemu/tree/arm/refactor-tcg-accel-split-v16> QEMU Device and Machine Models ([QEMU-418]) =========================================== - posted [kvm-unit-tests PATCH v2 0/4] enable LPI and ITS for TCG Message-Id: <20210525172628.2088-4-alex.bennee(a)linaro.org> [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 1/7] gitlab: explicitly reference the upstream registry Message-Id: <20210525112431.22005-1-alex.bennee(a)linaro.org> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Completed Reviews [5/5] ======================= [PATCH 0/5] linux-user changes to run docker Message-Id: <20210524045412.15152-1-yamamoto(a)midokura.com> [PATCH 0/4] gitlab-ci: Allow using FreeBSD runners Message-Id: <20210510152254.2543047-1-f4bug(a)amsat.org> [RFC PATCH 0/5] Use ccache in the gitlab-CI Message-Id: <20210414081907.871437-1-thuth(a)redhat.com> [PATCH 0/9] gitlab-ci: Make mainstream CI green again Message-Id: <20210525082556.4011380-1-f4bug(a)amsat.org> [PATCH] HMP: added cpustats to removed_features.rst Message-Id: <20210527191028.24febe7e(a)bahia.lan> Absences ======== Current Review Queue ==================== TODO [PATCH V5 0/2] Virtio support for toolstack on Arm (Was "IOREQ feature (+ virtio-mmio) on Arm") Message-Id: <1621603005-5799-1-git-send-email-olekstysh(a)gmail.com> ====================================================================================================================================================================== TODO [PATCH v2 00/12] hw: Various Kconfig fixes Message-Id: <20210515173716.358295-1-philmd(a)redhat.com> ====================================================================================================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== -- Alex Bennée

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 27 May

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] + Code review: - SVE2 series v7 (now finally done) - RTH's tlb_flush range refactoring - A few other minor patchsets + Arm pullrequest: SVE2 emulation support is now upstream + Misc bugs: - sent some patches fixing a few coverity nits in our test suite code * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Implemented: - VQDMULL, VRHADD, VADC, VSBC, VCADD, VHCADD - LCTP, LETP, WLSTP, DLSTP (the tail-predicating loop insns) - Progress meter: 73/210 (34%) -- PMM

4 years, 6 months

1
0
0 0

[ACTIVITY] 17 - 21 May 2021

by Prathamesh Kulkarni

== This Week == * PR66791 (Replace builtins with C operations in intrinsics) - vtst: Committed patch to trunk. - vshl_n: Patch results in worse code-gen, abandoned. - vmul_n: Created patch, looking into testsuite fallout * PR97906 (Missed lowering abs(x) >= abs(y) to vcage x, y) - Investigated PR and have a WIP fix. == Next Week == - Continue with PR66791, PR97906

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 21 May

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review: - bfloat16 support patchset - v3 of ITS emulation patchset + Misc bugs: - sent a patch fixing a bug where we sometimes selected the wrong stack pointer when doing a v8M exception return in a case involving tail-chaining (needed by an upcoming Arm TF-M change) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Sent a small patchset which implements a few preliminary MVE things (VPR register, FPSCR.QC bit, fixing checks for existing insns which now need to be "FP or MVE" rather than just "FP") + Implemented: - VADD VSUB VMULL VHADD VHSUB VQADD VQSUB VQDMULH VQRDMULH scalar - VBRSR, VPST, VQDMULH, VQRDMULH, VQADD, VQSUB - VQSHL VQRSHL VSHL VRSHL vector forms - VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH Progress meter: 63/210 (30%) -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending May. 23 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - worked with Viresh on getting more reliable Xen up and running - formally took over Caludio's arm branch as I need it for mine - preparing [my version] for posting [my version] <https://github.com/stsquad/qemu/tree/arm/refactor-tcg-accel-split-v16> QEMU Upstream Work ([UM-2]) =========================== - finally got [PULL v2 00/29] testing and plugin updates Message-Id: <20210518090720.21915-1-alex.bennee(a)linaro.org> merged - posted [PATCH v1 0/8] various misc fixes (gitlab, gdbstub, plugins) Message-Id: <20210520174303.12310-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Other ===== - [Blog post on QEMU went live] [Blog post on QEMU went live] <https://www.linaro.org/blog/many-uses-of-qemu/> Current Review Queue ==================== TODO [PATCH v2 00/12] hw: Various Kconfig fixes Message-Id: <20210515173716.358295-1-philmd(a)redhat.com> ====================================================================================================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] 17-21 May 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - reported a couple of regressions * GCC - MVE/vectorization: committed patches for vcmp, waiting for feedback on the remaining patches for vld2/vst2, vld4/st4 - started work on vaddv support - committed a few testsuite improvement patches - committed patch for PR 42579 * Misc - looking at gdb issue with register names in target description == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending 16 May 2021

by Richard Henderson

3 day week. [UM-2 # QEMU Upstream] * Refresh target/i386 translate user/sysemu cleanup. * Pull request for half of my softfloat reorg. * Tiny pull request for collected tcg patches. [QEMU-349 # SVE2] * Processing Peter's review comments. Another 3 day week this week. r~

4 years, 7 months

1
0
0 0

[ACTIVITY] 10-14 May 2021

by Christophe Lyon

Short week (2.5 days off) == Progress == * GCC upstream validation: - discussing update of the list of configs * GCC - MVE/vectorization: committing cleanup patches for vcmp, waiting for feedback on the remaining patches for vcmp, vld2/vst2, vld4/st4 * Misc - scripts patch reviews - looking at gdb issue with register names in target description == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * GDB/cortex-M

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 14 May

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review: - Managed to review all of RTH's 82-patch SVE2 patchset... + Misc bugs: - fixed some errors in modelling of SRAM in AN547 board - fixed a bug in GICv3 EOI (EL3 should be able to handle Group 1 NS IRQs) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] + Implemented multiply-add-long-dual-accumulate insns (VMLALDAV, VMLSLDAV, VRMLALDAVH, VRMLSLDAVH) Progress meter: 40/210 (19%) -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending May. 16 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - did some investigation on getting [Gunyah hypervisor] up and running - debugging xl domU launch under QEMU - got reverse debugging working on virtio ;-) [STR-9] <https://projects.linaro.org/browse/STR-9> [Gunyah hypervisor] <https://github.com/quic/gunyah-hypervisor> QEMU Upstream Work ([UM-2]) =========================== - reviewed a large chunk of rth's FloatParts opus Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org> - posted [PATCH v3 00/31] testing/next pre-PR (hexagon, tricore, misc) Message-Id: <20210512102051.12134-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Other ===== [Linaro JIRA Issues] Updates for LBO-99: QEMU's usage in Linaro Message-Id: <01000178a38e5f60-4b7149b0-b71b-4952-869f-cabdfb9078a6-000000(a)email.amazonses.com> Completed Reviews [1/1] ======================= [PATCH 00/72] Convert floatx80 and float128 to FloatParts Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org> Absences ======== - Bank Holiday on Monday Current Review Queue ==================== TODO [PATCH v3 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210429234201.125565-1-shashi.mallela(a)linaro.org> =========================================================================================================================== TODO [PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS Message-Id: <20210505030443.25310-1-rebecca(a)nuviainc.com> ==================================================================================================================================== TODO [PATCH v6 00/82] target/arm: Implement SVE2 Message-Id: <20210430202610.1136687-1-richard.henderson(a)linaro.org> =================================================================================================================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== -- Alex Bennée

4 years, 7 months

1
0
0 0

Bootstrap-O3 broken on 32-bit ARM

by Maxim Kuvyrkov

Hi Richard, Your patch a076632e274abe344ca7648b7c7f299273d4cbe0 appears to have broken bootstrap-O3 for 32-bit armhf. Do you have an AArch32-capable machine to reproduce/investigate this on? Let me know if not, and I'll make a proper bug report with a testcase. ICE: 00:33:32 In function ‘syscall.forkExec’: 00:33:32 go1: error: address taken, but ADDRESSABLE bit not set 00:33:32 PHI argument 00:33:32 &go..C479; 00:33:32 for PHI node 00:33:32 err$__object_78 = PHI <err$__object_76(58), &go..C479(59)> 00:33:32 during GIMPLE pass: fre 00:33:32 go1: internal compiler error: verify_ssa failed 00:33:32 0x9c18d7 verify_ssa(bool, bool) 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/tree-ssa.c:1214 00:33:32 0x6f8d5b execute_function_todo 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2049 00:33:32 0x6f9abf do_per_function 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:1687 00:33:32 0x6f9abf execute_todo 00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2096 00:33:32 Please submit a full bug report, 00:33:32 with preprocessed source if appropriate. 00:33:32 Please include the complete backtrace with any bug report. 00:33:32 See <https://gcc.gnu.org/bugs/> for instructions. 00:33:32 Makefile:3001: recipe for target 'syscall.lo' failed Full build log: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… Regards, -- Maxim Kuvyrkov https://www.linaro.org > On May 11, 2021, at 8:15 AM, tcwg-jira (Jira) <projects(a)linaro.org> wrote: > > There is 1 comment. > > > GNU Toolchain / <Mail Attachment.png> GNU-692 IN PROGRESS > Regressions from tcwg_binutils/tcwg_cross/tcwg_gnu CI > > View issue · Add comment > > 1 comment > > tcwg-jira on 11/May/21 5:04 AM > > Successfully identified regression in gcc in CI configuration tcwg_gnu/gnu-master-arm-bootstrap_O3. So far, this commit has regressed CI configurations: > • tcwg_gnu/gnu-master-arm-bootstrap_O3 > Culprit: > <cut> > commit a076632e274abe344ca7648b7c7f299273d4cbe0 > Author: Richard Biener <rguenther(a)suse.de> > Date: Fri May 7 09:51:18 2021 +0200 > middle-end/100464 - avoid spurious TREE_ADDRESSABLE in folding debug stmts > canonicalize_constructor_val was setting TREE_ADDRESSABLE on bases > of ADDR_EXPRs but that's futile when we're dealing with CTOR values > in debug stmts. This rips out the code which was added for Java > and should have been an assertion when we didn't have debug stmts. > To not regress g++.dg/tree-ssa/array-temp1.C we have to adjust the > testcase to not look for a no longer applied invalid optimization. > 2021-05-10 Richard Biener <rguenther(a)suse.de> > PR middle-end/100464 > PR c++/100468 > gcc/ > • gimple-fold.c (canonicalize_constructor_val): Do not set > TREE_ADDRESSABLE. > gcc/cp/ > • call.c (set_up_extended_ref_temp): Mark the temporary > addressable if the TARGET_EXPR was. > gcc/testsuite/ > • gcc.dg/pr100464.c: New testcase. > • g++.dg/tree-ssa/array-temp1.C: Adjust. > </cut> > Details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… > Even more details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar… > > > This message was sent by Atlassian Jira (v8.11.1#811002-sha1:94cd716) > Jira is improving email notifications, share your feedback! > Get Jira notifications on your phone! Download the Jira Server app for Android or iOS.

4 years, 7 months

2
1
0 0

[ACTIVITY] 3 - 7 May 2021

by Prathamesh Kulkarni

== This Week == * GCC - PR97903 (missed lowering to vtst): Committed fix to trunk, - PR66791: Submitted patch to replace vtst* (a, b) by (a & b) != 0 in arm_neon.h. - Committed fix for build failure in trunk. * Validation - vect metric: Pushed all pending patches. == Next Week == - PR66791: Continue working on more intrinsics - Validation: Monitor vect metric

4 years, 7 months

1
0
0 0

[ACTIVITY] 3-7 May 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions - discussing update of the list of configs - tried qemu-6.0, issue with hwasan testing on aarch64 * GCC - MVE/vectorization: waiting for feedback on patches for vcmp, vld2/vst2, vld4/st4 * Misc - scripts patch reviews - looking at gdb issue with register names in target description == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending May. 9 2021

by Alex Bennée

QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v2 00/30] testing/next (hexagon, tricore, ppc, signals, cirrus) Message-Id: <20210504100223.25427-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/7] plugins/next (windows, leaks, tcg tracing) Message-Id: <20210505092259.8202-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> [Linaro JIRA Issues] Updates for LBO-99: QEMU's usage in Linaro Message-Id: <01000178a38e5f60-4b7149b0-b71b-4952-869f-cabdfb9078a6-000000(a)email.amazonses.com> ============================================================================================================================================================= Completed Reviews [3/3] ======================= [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> [PATCH 0/5] misc: Replace alloca() by g_malloc() Message-Id: <20210505170055.1415360-6-philmd(a)redhat.com> [PATCH v2 0/9] misc: Replace alloca() by g_malloc() Message-Id: <CANCZdfqiHxQoG+g3bq_KL01yWCHUbF5qxJWN=sD37h7UJFMZ7g(a)mail.gmail.com> Absences ======== - Bank Holiday on Monday Current Review Queue ==================== TODO [PATCH v6 00/82] target/arm: Implement SVE2 Message-Id: <20210430202610.1136687-1-richard.henderson(a)linaro.org> =================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 6 May

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] - sent some small patches: fixing Coverity issues; converting a few users of a legacy API to the new function * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - Implemented more insns: VMUL, VSTRB/H/W, VMAX, VMIN, VABD, VHADD, VHSUB, VMULL, VRMULH. Progress meter: 36/210 (17%) -- PMM

4 years, 7 months

1
0
0 0

Flakey LLVM buildbot builds on clang-cmake-armv7-quick

by Christian Kühnel

Hi folks, I just noticed that your builds on clang-cmake-armv7-quick seem to be flakey from time to time: https://lab.llvm.org/buildbot/#/builders/107/builds/7394 https://lab.llvm.org/buildbot/#/builders/107/builds/7390 https://lab.llvm.org/buildbot/#/builders/107/builds/7369 https://lab.llvm.org/buildbot/#/builders/107/builds/7359 I just got hit by one of the flakes with a documentation-only change. I looks like the build is timing out... Best, Christian

4 years, 7 months

1
1
0 0

[ACTIVITY] week ending 2 May 2021

by Richard Henderson

[um-2] Patch review: power10, arm. Fixes for Alex's new signals.c test: sparc, s390. [qemu-349] Refreshed sve2 patch set. r~

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending May. 2 2021

by Alex Bennée

QEMU Device and Machine Models ([QEMU-418]) =========================================== - posted [kvm-unit-tests PATCH v1 0/4] enable LPI and ITS for TCG Message-Id: <20210428101844.22656-1-alex.bennee(a)linaro.org> [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - updated [testing/next branch] we some more fixes [UM-2] <https://projects.linaro.org/browse/UM-2> [testing/next branch] <https://github.com/stsquad/qemu/tree/testing/next> Other ===== - Spent more time on blog post for [LBO-99] [LBO-99] <https://projects.linaro.org/browse/LBO-99> Completed Reviews [3/3] ======================= [PATCH v3 0/2] tests/docker: tests/tcg/ppc64le: Newer toolchain to build tests for PowerISA v3.1 instructions Message-Id: <20210423205757.1752480-1-matheus.ferst(a)eldorado.org.br> [PATCH 0/2] plugins: Freeing allocated values in hash tables. Message-Id: <20210421140934.7561-1-ma.mandourr(a)gmail.com> [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210401024152.203896-1-shashi.mallela(a)linaro.org> Absences ======== - Bank Holiday on Monday Current Review Queue ==================== TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels' Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com> =================================================================================================================================================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== TODO [RFC v14 00/80] arm cleanup experiment for kvm-only build Message-Id: <20210416162824.25131-1-cfontana(a)suse.de> =================================================================================================================== -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 30 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - release work: rc5 Monday, and then 6.0 final release on Thursday. - sent a pullreq with some accumulated arm patches now 6.1 is open - fixed a trivial bug where WFI in the usermode emulator crashed * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - Implemented more instructions: logic ops, VCLS, VCLZ, VREV, VMVN, VABS, VNEG, VADD, VDUP, VSUB, VMULH, and widening VLDR. (These are all simple "always call an out-of-line helper" versions. We'll want an optimised "we know we have no predication" version for many of them, but I plan to do that afterwards.) - Worked through the v8M Arm ARM identifying which insns we must implement. There are 210 insn patterns in total, of which I have currently implemented 23, so we can produce a rough-and-ready progress meter: 23/210 (11%) (There is of course work to do beyond just the insns, but they form the bulk of it, so the meter has some utility.) -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] 26-30 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions * GCC - committed cleanup patches - sent a few testsuite improvement patches - MVE/vectorization: Send patches for vcmp, vld2/vst2, vld4/st4 * Misc - scripts patch reviews == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending Apr. 25 2021

by Alex Bennée

QEMU Support for Xen ([STR-20]) =============================== - continued reviewing [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> - this is looking pretty solid now - cut new version of [arm build clean-ups based on Claudio's series] - testing reveals some breakage to track down next week [STR-20] <https://projects.linaro.org/browse/STR-20> [arm build clean-ups based on Claudio's series] <https://github.com/stsquad/qemu/tree/xen/arm-build-cleanups-v3> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/11] rc2 fixes (check-tcg, gitlab, gdbstub) Message-Id: <20210406150041.28753-1-alex.bennee(a)linaro.org> - some time trying to debug last weeks PR, eventually merged - posted [PATCH for post 6.0 v1 00/25] testing/next (hexagon/tricore/test cc) Message-Id: <20210419145435.14083-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/tcg: add a multiarch signals test to stress test signal delivery Message-Id: <20210421132931.11127-1-alex.bennee(a)linaro.org> - hunting for RC failure in s390x - posted [PATCH] target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability Message-Id: <20210422154427.13038-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> GSoC/Intern Mentoring ===================== GSoC 2021 proposal initiation for AGL Message-Id: <CAC+yH-Z_KZKuQ0nmAgk-+B+HW88sNjztObtWwazof+cAGJGuuQ(a)mail.gmail.com> GSoC: cache modelling plugin inquiry Message-Id: <CAD-LL6hLk1XAB5VWwHgMOWQV=bT1+FCnf8f-q9MVw5e5A4RMqg(a)mail.gmail.com> GSoC - QEMU Ideas Message-Id: <CALpwMJz0kb2BDreTWBbt945FR+sLX=sKzHSv8pMb5LkLwXqEJA(a)mail.gmail.com> Synced up with potential AGL Jailhouse/VirtIO GSoC applicant Other ===== - bit more write-up of blog post for [LBO-99] [LBO-99] <https://projects.linaro.org/browse/LBO-99> Completed Reviews [8/8] ======================= [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document Message-Id: <72bc8020-2028-82db-219c-a6ae311e26df(a)redhat.com> [PATCH v4 00/12] target/arm mte fixes Message-Id: <20210406174031.64299-4-richard.henderson(a)linaro.org> [PATCH 0/4] Acceptance Tests: update assets location and cancel tests if missing Message-Id: <20200907042000.415931-1-crosa(a)redhat.com> Added: <2020-09-07 Mon> [RFC PATCH 0/3] tests/tcg/ppc64le: paddi tests Message-Id: <20210415214138.563795-1-matheus.ferst(a)eldorado.org.br> [RFC PATCH 00/15] gitlab-ci: Allow forks to use different pipelines than mainstream Message-Id: <20210418233448.1267991-11-f4bug(a)amsat.org> [PATCH 0/2] gdbstub: implement support for blocking interrupts on single stepping Message-Id: <20210401144152.1031282-1-mlevitsk(a)redhat.com> [PATCH v2 0/7] linux-user: sigaction fixes/cleanups Message-Id: <20210422230227.314751-1-richard.henderson(a)linaro.org> testing/next - hexagon toolchain update Message-Id: <BN7PR02MB4194DF5752EF3BADE858018DB8799(a)BN7PR02MB4194.namprd02.prod.outlook.com> [PATCH] tests/tcg: Run tests on arch variants again Message-Id: <20210312152105.1836543-1-f4bug(a)amsat.org> [PATCH 0/1] libbpf dependecy for docker containers. Message-Id: <20210406082947.672708-1-andrew(a)daynix.com> [PATCH v3 00/15] tests/tcg: Add TriCore tests Message-Id: <20210305170045.869437-1-kbastian(a)mail.uni-paderborn.de> Absences ======== Current Review Queue ==================== TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com> ============================================================================================================================== TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com> ======================================================================================================================================== TODO [RFC v14 00/80] arm cleanup experiment for kvm-only build Message-Id: <20210416162824.25131-1-cfontana(a)suse.de> =================================================================================================================== TODO [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210401024152.203896-1-shashi.mallela(a)linaro.org> =========================================================================================================================== -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 23 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - code review: + Shashi's ITS emulation patchset + RTH's remaining fixes for MTE + RTH's patchset to implement alignment checking - release work: sadly we found a pretty nasty crasher bug at the last minute, so we'll release rc5 on Monday and final release Thursday (with luck) * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - useful discussions with RTH about how to implement MVE and in particular how to handle its various flavours of insn predication - some progress in writing code to implement the first insn (VLDR) thanks -- PMM

4 years, 8 months

1
0
0 0

[ACTIVITY] 19-23 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions * GCC - committed further fix for testcase for PR96770 - sent a few testsuite improvement patches - resumed work on MVE/auto-vectorization. Added support for vcmp.f16. Checking fp16 support in previous patches. * Misc - scripts patch reviews == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 8 months

1
0
0 0

[ACTIVITY] 12-16 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported a few regressions - Reduced build frequency on release branches, now same as trunk: daily bump and arm/aarch64 "interesting" commits * GCC - pinged further fix for testcase for PR96770 - preparing cortex-m55 validation setup - looking at cmse tests vs qemu - Linaro BZ 5755/upstream 100049 * GDB - uploaded cleaned up last known-to-work branch to sourceware so that maintainers can have a look at it - uploaded latest wip based on 8.2 branch too * Misc - scripts patch reviews == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes

4 years, 8 months

1
0
0 0

[ACTIVITY] report week ending Apr 16

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Finished and posted patches implementing remap support for AN524 - Release work for rc3 - Sent a set of refactoring patches that split out some files we were previously #including into translate.c so they are separate compilation units. - Thought a bit more about reset handling (in the course of writing the AN524 remap patches I again ran into some of the deficiencies of our current reset implementation; I really must take some time this release cycle to try to improve things here...) - Fixed bug where our AN547 board model accidentally disabled the FPU on the Cortex-M55... - ...and one where we were accidentally giving it an M33 rather than an M55 ! - Respun and extended some patches from Paolo which fix our use of QEMU and system headers in the 2 C++ files in the codebase (which were broken by a change in new versions of glib) - started looking at some of the for-6.1 patch review queue, which I had been postponing in favour of for-6.0 stuff * QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)] - re-read the MVE portions of the v8M Arm ARM, sketched out a plan of where to start with the QEMU implementation thanks -- PMM

4 years, 8 months

1
0
0 0

qemu bfloat16 branch

by Richard Henderson

https://gitlab.com/rth7680/qemu/-/commits/tgt-arm-bf16 It isn't a large extension, so all done. I added aarch64 simd, aarch32 neon, and sve support all at once. I've tested it via risu vs FVP. I've based this on my SVE2 branch, since there are some cleanups that made that easier. I'll post patches to qemu-devel next week. r~

4 years, 8 months

2
1
0 0

[ACTIVITY] 5-9 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - No regression to report this week. Issues on gcc-9 and gcc-10 release branches had already been reported by other people. * GCC - pinged further fix for testcase for PR96770 - Looking at failures for cortex-M, only found testisms so far * Misc - Fixed benchmarking jobs on stm32 == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 8 months

1
0
0 0

[ACTIVITY] week ending 11 Apr 2021

by Richard Henderson

[UM-2] * Patch review. Lots. [QEMU-389 # Bfloat16 ] * Implemented. Will post patches next week. r~

4 years, 8 months

1
0
0 0

[ACTIVITY] week ending Apr. 11 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - had sync-up with Akashi-san/Vincent about approaches for the Zephyr demo - need to write-up on Monday [STR-9] <https://projects.linaro.org/browse/STR-9> QEMU Support for Xen ([STR-20]) =============================== - continued reviewing [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> - this is looking pretty solid now - cut new version of [arm build clean-ups based on Claudio's series] - testing reveals some breakage to track down next week [STR-20] <https://projects.linaro.org/browse/STR-20> [arm build clean-ups based on Claudio's series] <https://github.com/stsquad/qemu/tree/xen/arm-build-cleanups-v3> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/11] rc2 fixes (check-tcg, gitlab, gdbstub) Message-Id: <20210406150041.28753-1-alex.bennee(a)linaro.org> - some time trying to debug last weeks PR, eventually merged [UM-2] <https://projects.linaro.org/browse/UM-2> GSoC/Intern Mentoring ===================== GSoC 2021 proposal initiation for AGL Message-Id: <CAC+yH-Z_KZKuQ0nmAgk-+B+HW88sNjztObtWwazof+cAGJGuuQ(a)mail.gmail.com> GSoC: cache modelling plugin inquiry Message-Id: <CAD-LL6hLk1XAB5VWwHgMOWQV=bT1+FCnf8f-q9MVw5e5A4RMqg(a)mail.gmail.com> GSoC - QEMU Ideas Message-Id: <CALpwMJz0kb2BDreTWBbt945FR+sLX=sKzHSv8pMb5LkLwXqEJA(a)mail.gmail.com> Synced up with potential AGL Jailhouse/VirtIO GSoC applicant Completed Reviews [3/3] ======================= [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document Message-Id: <72bc8020-2028-82db-219c-a6ae311e26df(a)redhat.com> [PATCH v4 00/12] target/arm mte fixes Message-Id: <20210406174031.64299-4-richard.henderson(a)linaro.org> Absences ======== Current Review Queue ==================== TODO [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> ================================================================================================================== TODO [RFC 0/8] virtio: Improve boot time of virtio-scsi-pci and virtio-blk-pci Message-Id: <20210325150735.1098387-1-groug(a)kaod.org> =================================================================================================================================== TODO [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> =========================================================================================================================== TODO [PATCH v2 00/29] tcg: Workaround macOS 11.2 mprotect bug Message-Id: <20210314212724.1917075-1-richard.henderson(a)linaro.org> ================================================================================================================================ -- Alex Bennée

4 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 9 Apr

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] - more release work, bug triage, etc - started implementing the memory-remapping feature of the AN524 FPGA image (which allows the BRAM and QSPI to be swapped either at startup or dynamically under guest control). Some guests (like ARM TF-M) assume the QSPI mapping. thanks -- PMM

4 years, 8 months

1
0
0 0

[ACTIVITY] 29 March-2 April 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Reported minor testsuite issues (eg failures with -mabi=ilp32 on aarch64) - re-started looking at validation for cortex-m55, realized that qemu does not support MVE yet * GCC - posted further fix for testcase for PR96770 - fixed PR 99786 - committed fix for PR 99773 * Misc == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 8 months

1
0
0 0

[ACTIVITY] week ending Apr. 4 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted virtio-scmi backend on Zephyr as both Xen DomU and Jailhouse Partition demo suggestion Message-Id: <87ft0cyiqi.fsf(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 6.0-rc2? v1 0/6] check-tcg for non-x86 hosts Message-Id: <20210329110303.15235-1-alex.bennee(a)linaro.org> - posted [PATCH for 6.0-rc2 v2 00/11] various fixes, pre-PR (check-tcg, gdbstub, gitlab) Message-Id: <20210401102530.12030-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [7/7] ======================= [PATCH v1 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210323041238.133835-1-shashi.mallela(a)linaro.org> [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> [PATCH V2 0/6] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1617278395.git.viresh.kumar(a)linaro.org> [0/0] tcg/mips: Fix SoftTLB comparison on mips backend Message-Id: <20210401100457.191458-1-kele.hwang(a)gmail.com> [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> [PATCH] docs: Add a QEMU Code of Conduct and Conflict Resolution Policy document Message-Id: <72bc8020-2028-82db-219c-a6ae311e26df(a)redhat.com> Current Review Queue ==================== TODO [RFC v12 00/65] arm cleanup experiment for kvm-only build Message-Id: <20210326193701.5981-1-cfontana(a)suse.de> ================================================================================================================== TODO [RFC 0/8] virtio: Improve boot time of virtio-scsi-pci and virtio-blk-pci Message-Id: <20210325150735.1098387-1-groug(a)kaod.org> =================================================================================================================================== TODO [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> =========================================================================================================================== TODO [PATCH v2 00/29] tcg: Workaround macOS 11.2 mprotect bug Message-Id: <20210314212724.1917075-1-richard.henderson(a)linaro.org> ================================================================================================================================ -- Alex Bennée

4 years, 8 months

1
0
0 0

[ACTIVITY] week ending 28 Mar 2021

by Richard Henderson

[UM-2] * Fix exec-vary.c vs gcc -flto. * Fix ppc tb->flags usage. * Patch review: - v11 of claudio's arm accel work - hexagon stuff - arm pcmr settings r~

4 years, 8 months

1
0
0 0

[ACTIVITY] week ending Mar. 28 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - attended the [Stratos sync-call] - more talk about rust-vmm for daemons QEMU Upstream Work ([UM-2]) =========================== - posted [PULL v2 00/15] misc fixes (strtoz, plugins, guest-loader) Message-Id: <20210317072216.16316-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] gitlab: extend timeouts for CFI builds Message-Id: <20210322142110.4766-1-alex.bennee(a)linaro.org> - posted [PATCH for 6.0 v2 00/22] fixes for rc1 pre-PR (kernel-doc, semihosting, testing) Message-Id: <20210323165308.15244-1-alex.bennee(a)linaro.org> - posted [PULL for 6.0 00/22] various fixes (kernel-doc, semihosting, testing) Message-Id: <20210324143021.8560-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Other ===== - Provisioning new aarch64 CI machine for QEMU project Completed Reviews [7/7] ======================= [PATCH] FreeBSD: Upgrade to 12.2 release Message-Id: <20210319165138.117225-1-thuth(a)redhat.com> [PATCH] tests/meson: Only build softfloat objects if TCG is selected Message-Id: <20210322114739.4078408-1-f4bug(a)amsat.org> [PATCH v28 00/23] i386 cleanup PART 2 Message-Id: <20210322132800.7470-1-cfontana(a)suse.de> [RFC v10 00/49] arm cleanup experiment for kvm-only build Message-Id: <20210322140206.9513-1-cfontana(a)suse.de> [RFC v11 00/55] arm cleanup experiment for kvm-only build Message-Id: <20210323151749.21299-5-cfontana(a)suse.de> [PATCH 0/2] Fix atomic test in "configure" + bump FreeBSD CI to 12.2 Message-Id: <20210317110512.583747-1-thuth(a)redhat.com> [PATCH v1 0/8] GICv3 LPI and ITS feature implementation Message-Id: <20210323041238.133835-1-shashi.mallela(a)linaro.org> Absences ======== - Linaro Connect Sessions Current Review Queue ==================== TODO [RFC 0/8] virtio: Improve boot time of virtio-scsi-pci and virtio-blk-pci Message-Id: <20210325150735.1098387-1-groug(a)kaod.org> =================================================================================================================================== TODO [PATCH RESEND] docs: clarify absence of set_features in vhost-user Message-Id: <20210325144846.17520-1-hi(a)alyssa.is> ======================================================================================================================== TODO [PATCH 0/5] virtio: Implement generic vhost-user-i2c backend Message-Id: <cover.1616570702.git.viresh.kumar(a)linaro.org> =========================================================================================================================== TODO [PATCH v2 00/29] tcg: Workaround macOS 11.2 mprotect bug Message-Id: <20210314212724.1917075-1-richard.henderson(a)linaro.org> ================================================================================================================================ -- Alex Bennée

4 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 26 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - tagged rc0 - various bug investigation/patches for 6.0-ish stuff: + machines with a 'platform bus' incorrectly treated all sysbus devices as hotpluggable: wrote and sent patchseries + respin of gpex pci-host "don't fault for unmapped MMIO/PIO window accesses" patch + document how to use gdbstub/gdb for a multi-cluster machine where the clusters are different gdb inferiors + looked for workarounds for macos Appkit bug where Apple broke menubars for apps that start off as console apps and programmatically switch themselves to being GUI apps; various online suggestions don't seem to help, except for "when app starts, force the Dock to become active and then grab back focus 200ms later". Maybe we'll do that, but it's pretty ugly... thanks -- PMM

4 years, 8 months

1
0
0 0

[ACTIVITY] 22-26 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - No regression to report this week * GCC - testsuite cleanup: committed a patch series - fixed PR 99727 - filed / discussed PR 99773 - WIP PR 99786 * Misc == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 8 months

1
0
0 0

[ACTIVITY] 15-19 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Small improvement to pre-commit testing scripts to allow running a subset of the tests (and thus save a lot of time) * GCC - MVE autovectorization: - vcmp support of FP types OK. - testsuite cleanup: looking at current failures, only found issues with tests so far. Testing several small testsuite patches is taking a long time due to the number of configurations * Misc == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * Resume GDB/FDPIC work

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 19 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - softfreeze was this week, lots of pullreq processing - spun v2 of "fix M-profile load of PC/SP from ELF images via memory aliases" thanks -- PMM

4 years, 9 months

1
0
0 0

Please use staging for your new bots; clang-cmake-aarch64-full is red for a month

by Galina Kistanova

Hello Linaro Toolchain Working Group, Please connect your new bots to the staging first and make them reliably green there: linaro-aarch64-flang-debug linaro-aarch64-flang-latest-clang linaro-aarch64-flang-latest-gcc clang-cmake-aarch64-full is red for a month. https://lab.llvm.org/buildbot/#/builders/7?numbuilds=700 Could you move linaro-aarch64-full to the staging and make it green again, please? Please let me know if I could help or you have questions. Thanks Galina

4 years, 9 months

3
4
0 0

Re: Clang targetting x64 linker

by Maxim Kuvyrkov

Hi Joel, Indeed, LLD is not configured to be used by default in LLVM-12.0.0-rc1. You need to add -fuse-ld=lld option for it to work. We’ll fix this in the final LLVM-12 release for WoA, which is expected in around 2 weeks. Thanks for catching this! c:\Users\tcwg\source\maxim>..\llvm-12.0.0-rc1\bin\clang-cl.exe hello.c clang-cl: error: unable to execute command: Couldn't execute program 'C:\BuildTools\VC\Tools\MSVC\14.28.29333\bin\Hostx64\arm64\link.exe': Unknown error (0xD8) clang-cl: error: linker command failed with exit code 1 (use -v to see invocation) c:\Users\tcwg\source\maxim>..\llvm-12.0.0-rc1\bin\clang-cl.exe -fuse-ld=lld hello.c c:\Users\tcwg\source\maxim>hello.exe Hello c:\Users\tcwg\source\maxim>..\llvm-12.0.0-rc1\bin\clang.exe -fuse-ld=lld hello.c c:\Users\tcwg\source\maxim>hello.exe Hello -- Maxim Kuvyrkov https://www.linaro.org > On 4 Mar 2021, at 19:43, Joel Cox <Joel.Cox(a)arm.com> wrote: > > Hi > > I was trying "clang hello.c" from command line, but "clang-cl hello.c" gives me the same error. I am unsure if this is what you mean but neither work. > > Thanks, > Joel > > -----Original Message----- > From: Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org> > Sent: 04 March 2021 16:40 > To: Joel Cox <Joel.Cox(a)arm.com> > Cc: linaro-toolchain(a)lists.linaro.org > Subject: Re: Clang targetting x64 linker > > Hi Joel, > > Are you using clang-cl.exe as compiler/linker driver? It’s easiest to use clang-cl.exe as it aims to be a direct replacement for MSVC’s cl.exe, but will use LLVM tools. In particular, when clang-cl.exe uses LLVM Linker (LLD) by default. > > If you are using linux-style clang.exe as the driver, then you need to specify -fuse-ld=lld to use LLD. > > Does this help? > > Regards, > > -- > Maxim Kuvyrkov > https://www.linaro.org > >> On 4 Mar 2021, at 19:11, Joel Cox <Joel.Cox(a)arm.com> wrote: >> >> Hi >> >> I've been trying to run clang on a Windows on Arm machine, but it keeps trying to using the link.exe located in "Visual studio/..../Host64/arm64", which is (seemingly) an x64 tool and as such doesn't run, and crashes the process. >> Is there a way to set clang to look at VS's x86 link.exe? Or if there is an arm64 version that clang should be using instead? >> >> Thanks, >> Joel >> IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. >> _______________________________________________ >> linaro-toolchain mailing list >> linaro-toolchain(a)lists.linaro.org >> https://lists.linaro.org/mailman/listinfo/linaro-toolchain > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 9 months

1
2
0 0

[ACTIVITY] week ending 14 Mar 2021

by Richard Henderson

[UM-2] * Clean up tcg code_gen_buffer mapping. * Clean up ppc tb->flags madness. * Rebase tci clean up. * Random patch review. [VIRT-349] * Send v4 of sve2 patch set. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Mar. 14 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - attended the [rust-vmm sync call] [rust-vmm sync call] <https://etherpad.opendev.org/p/rust-vmm-sync-2021> VirtIO RPMB ([STR-5]) - followed more of [RFC PATCH 0/5] RPMB internal and user-space API + WIP virtio-rpmb frontend Message-Id: <CACRpkda9f-BNmu-CaNsghnDoOcSXvvvji=tag2Xos+tg_nNZ0w(a)mail.gmail.com> [STR-5] <https://projects.linaro.org/browse/STR-5> [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [qemu-web PATCH] pages: update deprecation policy links to "official" manual Message-Id: <20210308103049.3653-1-alex.bennee(a)linaro.org> - posted [qemu-web RFC PATCH] _download/source.html: show the GPG fingerprint for releases Message-Id: <20210308111649.14898-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/4] semihosting/next (SYS_HEAPINFO fix) Message-Id: <20210309141727.12522-1-alex.bennee(a)linaro.org> - posted [PULL 00/18] testing, docs, semihosting move and guest-loader Message-Id: <20210308135104.24903-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/15] testing, docs, semihosting move and guest-loader Message-Id: <20210310160002.11659-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/7] testing/next (hexagon 2, electric boogaloo) Message-Id: <20210310192331.29284-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/15] testing, docs, semihosting move and guest-loader Message-Id: <20210310160002.11659-1-alex.bennee(a)linaro.org> - posted [PATCH v3 0/4] semihosting/next (SYS_HEAPINFO) Message-Id: <20210309172127.20470-1-alex.bennee(a)linaro.org> - posted [PATCH v5 0/5] semihosting/next (SYS_HEAPINFO) Message-Id: <20210312102029.17017-1-alex.bennee(a)linaro.org> - posted [PATCH v1 00/14] plugins/next (phys addr, syscalls, lots of docs) Message-Id: <20210312172821.31647-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH v2] linux-user: Fix executable page of /proc/self/maps Message-Id: <20210308091959.986540-1-nsurbayrole(a)quarkslab.com> [PATCH] plugins: new syscalls plugin Message-Id: <20200812115816.4454-1-matthias(a)weckbecker.name> Added: <2020-08-12 Wed> [PATCH v2] plugins: Expose physical addresses instead of device offsets Message-Id: <20210309202802.211756-1-aaron(a)os.amperecomputing.com> Absences ======== - Lockdown 3: Half day schooling - ends soon! Current Review Queue ==================== TODO [PATCH 0/4] Upgrade Meson to 0.57.x Message-Id: <20210310104937.253532-1-pbonzini(a)redhat.com> ================================================================================================= TODO [RFC v3 00/23] arm cleanup experiment for kvm-only build Message-Id: <20210303114053.20305-1-cfontana(a)suse.de> ================================================================================================================== Added: <2021-03-04 Thu> TODO [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> =================================================================================================================== Added: <2021-02-16 Tue> TODO [PATCH v2 00/15] tcg/arm: host neon support -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] 8-12 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Bisected last week regressions, but there had already been reported/fixed. * GCC - MVE autovectorization: - vcmp support mostly complete. support of FP types looks OK, though trickier than expected. - vld2/vst2 and vld4/vst4 done. * Misc - stm32 benchmarking harness: good speed up after removing useless toolchain multilib builds (7 minutes vs 1h+) - fixed GCC bisect Jenkins job == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * Resume GDB/FDPIC work * Troubleshoot Jenkins problems

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 12 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Mostly caught up on code review now: have done all the patches that are targeting 6.0 - Sent out some pullreqs with for-6.0 material - Wrote a patch to make us emulate the right number of counters for the PMU according to what each CPU should have, rather than always 4 - Had a go at fixing the M-profile vector table load on reset to handle aliased memory regions * QEMU-364 [QEMU support for ARMv8.1-M extensions] - mps3-an524 and -an547 patchseries now in master: this epic is done! thanks -- PMM

4 years, 9 months

1
0
0 0

Pre-commit CI with libc++

by Louis Dionne

Folks, I am pleased to announce the move of libc++ to pre-commit CI. Over the past few months, we have set up Buildkite jobs on top of the Phabricator integration built by Mikhail and Christian, and we now run almost all of the libc++ build bots whenever a Phabricator review is created. The bots also run when a commit is pushed to the master branch, similarly to the existing Buildbot setup. You can see the libc++ pipeline in action here: https://buildkite.com/llvm-project/libcxx-ci. This is great -- we’ve been waiting to set up pre-commit CI for a long time, and we’ve seen a giant productivity gain since it’s up. I think everyone who contributes to libc++ greatly benefits, seeing how reviews are now used to trigger CI and improve our confidence in changes. This change does have an impact on existing build bots that are not owned by one of the libc++ maintainers. While I transferred the build bots that we owned (which Eric had set up) to Buildkite, the remaining build bots will have to be moved to Buildkite by their respective owners. These builds bots are (owners in CC): libcxx-libcxxabi-x86_64-linux-debian libcxx-libcxxabi-x86_64-linux-debian-noexceptions libcxx-libcxxabi-libunwind-x86_64-linux-debian libcxx-libcxxabi-singlethreaded-x86_64-linux-debian libcxx-libcxxabi-libunwind-armv7-linux libcxx-libcxxabi-libunwind-armv8-linux libcxx-libcxxabi-libunwind-armv7-linux-noexceptions libcxx-libcxxabi-libunwind-armv8-linux-noexceptions libcxx-libcxxabi-libunwind-aarch64-linux libcxx-libcxxabi-libunwind-aarch64-linux-noexceptions The process of moving these bots over to Buildkite is really easy. Please take a look at the documentation at https://libcxx.llvm.org/docs/AddingNewCIJobs.html#addingnewcijobs and contact me if you need additional help. To make sure we get the full benefits of pre-commit CI soon, I would like to put a cutoff date on supporting the old libc++ builders at http://lab.llvm.org:8011/builders. I would propose that after January 1st 2021 (approx. 1 month from now), the libc++ specific build bots at lab.llvm.org be removed in favor of the Buildkite ones. If you currently own a bot, please make sure to add an equivalent Buildkite bot by that cutoff date to make sure your configuration is still supported, or let me know if you need an extension. Furthermore, with the ease of creating new CI jobs with this infrastructure, we will consider any libc++ configuration not covered by a pre-commit bot as not explicitly supported. It doesn’t mean that such configurations won’t work -- it just means that we won’t be making bold claims about supporting configurations we’re unable to actually test. So if you care about a configuration, please open a discussion and let’s see how we can make sure it's tested properly! I am thrilled to be moving into the pre-commit CI era. The benefits we see so far are huge, and we're loving it. Thanks, Louis PS: This has nothing to do with a potential move or non-move to GitHub. The current pre-commit CI works with Phabricator, and would work with GitHub if we decided to switch. Let’s try to keep those discussions separate :-). PPS: We’re still aiming to support non libc++ specific Buildbots. For example, if something in libc++ breaks a Clang bot, we’ll still be monitoring that. I’m just trying to move the libc++-specific configurations to pre-commit.

4 years, 9 months

5
6
0 0

[ACTIVITY] week ending 7 Mar 2021

by Richard Henderson

[VIRT-349 # QEMU SVE2 Support ] I have a working FVP SVE2 install! I used a new FVP version (11.13.36) from the last time that I tried (11.13.21 on Jan 27). I used a debian-testing snapshot from 1-MAR, which has linux 5.10 bundled, and fvp revc dtb installed. I used https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.gi… (which is linked to by one of the howtos that Peter forwarded) and chose the "pre-built uefi" version. I need to report a bug on this build script -- the "build from source" option does not work on a system that has all python3 and no python2. I've rebuilt all of the risu trace files for vq=4 (512-bit). I'm now refreshing my qemu branch to test. [UM-61 # TCG Core Maintainership ] PR for patch queue; aa64 fixes, tci fixes, tb_lookup cleanups. [UM-2 # Upstream Maintainership ] Patch review, mostly v8.1m board stuff. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Mar. 7 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted [PATCH v2] vhost-user.rst: add clarifying language about protocol negotiation Message-Id: <20210303145011.14547-1-alex.bennee(a)linaro.org> Linux Userspace ABI for RPMB devices ([STR-31]) ----------------------------------------------- - posted [RFC PATCH 0/5] RPMB internal and user-space API + WIP virtio-rpmb frontend Message-Id: <20210303135500.24673-1-alex.bennee(a)linaro.org> - has stimulated discussion on the thread, will see next posting from Thomas QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/9] testing/next (docs, hexagon, cfi, docker) Message-Id: <20210305092328.31792-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/3] semihosting/next (move from hw, heapinfo) Message-Id: <20210305135451.15427-1-alex.bennee(a)linaro.org> - optimising tb lookup ---------------------- - CLOSING NOTE [2021-03-05 Fri 17:22] rth merged my changes plus a pre-compute of cflags. Completed Reviews [8/8] ======================= [PATCH v3 0/2] gitlab-ci.yml: Add jobs to test CFI Message-Id: <20210304030948.9367-1-dbuono(a)linux.vnet.ibm.com> [PATCH 0/4] hexagon: Add Docker image & testing to gitlab-ci Message-Id: <20210228222314.304787-1-f4bug(a)amsat.org> - CLOSING NOTE [2021-03-04 Thu 20:04] Queued to my tree Added: <2021-03-02 Tue> [PATCH v2] tests/docker: Use --arch-only when building Debian cross image Message-Id: <20210223211115.2971565-1-f4bug(a)amsat.org> [PATCH] linux-user: Adjust pgd_find_hole_fallback result with guest_loaddr Message-Id: <20210303094919.x6wnlh6qulx72fz6(a)titan.localdomain> - CLOSING NOTE [2021-03-05 Fri 14:12] Added: <2021-03-03 Wed> [PATCH 00/44] hw/arm: New board model mps3-an547 Message-Id: <20210219144617.4782-1-peter.maydell(a)linaro.org> - CLOSING NOTE [2021-03-05 Fri 14:14] Looks like others have already looked over it. ADDED: <2021-03-04 Thu> [PATCH v3 00/70] TCI fixes and cleanups Message-Id: <20210208023752.270606-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2021-03-05 Fri 16:59] v4 released, wish I'd noticed earlier ;-) Added: <2021-02-08 Mon> [PATCH 00/27] tcg patch queue Message-Id: <20210302175741.1079851-1-richard.henderson(a)linaro.org> [PATCH 0/3] docs: replace master/slave with more accurate wording Message-Id: <20210226143413.188046-1-pbonzini(a)redhat.com> Absences ======== - Lockdown 3: Half day schooling - ends soon! Current Review Queue ==================== TODO [RFC v3 00/23] arm cleanup experiment for kvm-only build Message-Id: <20210303114053.20305-1-cfontana(a)suse.de> ================================================================================================================== Added: <2021-03-04 Thu> TODO [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> =================================================================================================================== Added: <2021-02-16 Tue> TODO [PATCH v2 00/15] tcg/arm: host neon support Message-Id: <20210208024625.271018-1-richard.henderson(a)linaro.org> ================================================================================================================== Added: <2021-02-08 Mon> -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 5 Mar

by Peter Maydell

Progress (short week, 2 days): * Some time spent on setting up new work laptop * Started in on the pile of code review that had built up while I was on holiday... made a bit of progress and sent out one pullreq. Queue length now: 16 series. thanks -- PMM

4 years, 9 months

1
0
0 0

What does suffix ' ... isra.0' mean in compiled symbols in GCC 10.2?

by Guodong Xu

Hi, all Does anybody know what does '.....isra.0' mean in GCC 10.2 compiled objects? I just noticed this issue when using bcc/eBPF tools. I submitted the detail into * https://github.com/iovisor/bcc/issues/3293 Simply put, when building a linux kernel with GCC 10.2, the symbol 'finish_task_switch' becomes 'finish_task_switch.isra.0' in the object (as reported by 'nm') Because a lot of kernel tracers (such as bcc) use 'finish_task_switch' as the probe point, this change in the compilation result can make all result such tools fail. Thanks. Best regards, Guodong Xu

4 years, 9 months

2
2
0 0

[ACTIVITY] 1-5 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a couple of regressions to bisect. - minor testcase fix - reported a couple of new failures * GCC - MVE autovectorization: - vcmp support mostly complete. Minor update needed to support FP types. - working on interleaved vector load/store support * Misc - fixed stm32 benchmarking harness, it's working again. - submitted patches to reduce the toolchain build time (for benchmarking we don't need all multilibs which take ages to build) == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 9 months

1
0
0 0

Clang targetting x64 linker

by Joel Cox

Hi I've been trying to run clang on a Windows on Arm machine, but it keeps trying to using the link.exe located in "Visual studio/..../Host64/arm64", which is (seemingly) an x64 tool and as such doesn't run, and crashes the process. Is there a way to set clang to look at VS's x86 link.exe? Or if there is an arm64 version that clang should be using instead? Thanks, Joel IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 9 months

2
1
0 0

LLVM12 Clang doesn't start

by Joel Cox

Hi, I've been trying to use clang on Windows on Arm machine (Samsung Galaxy Book S), but whenever I try to use it, I get either nothing (in powershell) or an error popup: "The application was unable to start correctly (0x000007b)". The release I'm using is LLVM-12.0.0-rc1-woa64.exe<https://github.com/llvm/llvm-project/releases/download/llvmorg-12.0.0-rc1/L…> from https://github.com/llvm/llvm-project/releases/tag/llvmorg-12.0.0-rc1 I have a feeling there might be a library or dependency I am missing. Any help with how to resolve this issue would be appreciated. Thanks, Joel IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 9 months

2
1
0 0

[ACTIVITY] week ending 28 Feb 2021

by Richard Henderson

[UM-2 # QEMU Upstream Work] * A lot of patch review. * Some target/i386 cleanup, as followup to said patch review. * Collecting patches for tcg-next. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Feb. 28 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - some planning discussion around STR-26/STR-7 - posted vhost reply_ack negotiation (a.k.a differences in vhost-user behaviour with libvhost-user and vhost-user-backend.rs) Message-Id: <8735xskm7j.fsf(a)linaro.org> - posted [vhost.rs PR] - posted [VHOST USER SPEC PATCH] vhost-user.rst: add clarifying language about protocol negotiation Message-Id: <20210226111619.21178-1-alex.bennee(a)linaro.org> [vhost.rs PR] <https://github.com/rust-vmm/vhost/pull/24> [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v2 0/6] testing/next (meson check-tcg, fedora bump, docs) Message-Id: <20210222101455.12640-1-alex.bennee(a)linaro.org> - posted [PULL 0/7] testing updates (build, docs, dumps) Message-Id: <20210224114926.6303-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Other ===== - some kernel/QEMU debugging for LKFT folks Completed Reviews [4/4] ======================= [PATCH v20 00/17] i386 cleanup PART 2 Message-Id: <20210218172156.25520-1-cfontana(a)suse.de> - CLOSING NOTE [2021-02-22 Mon 13:28] Only glanced over, mainly in prep for ARM series which is based on this Added: <2021-02-19 Fri> [PATCH] tests/docker: Use --arch-only when building Debian cross images Message-Id: <20210223170910.2916721-1-f4bug(a)amsat.org> [PATCH v5 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20210219215838.752547-4-crosa(a)redhat.com> [PATCH 0/3] gitlab-pipeline-status script: provide more information on errors Message-Id: <20210222193240.921250-2-crosa(a)redhat.com> Absences ======== - Lockdown 3: Half home-schooling Current Review Queue ==================== * [PATCH 0/2] semihosting: Move it out of hw/ Message-Id: <20210226131356.3964782-1-f4bug(a)amsat.org> Added: <2021-02-26 Fri> * [RFC v1 00/38] arm cleanup experiment for kvm-only build Message-Id: <20210221092449.7545-1-cfontana(a)suse.de> Added: <2021-02-21 Sun> * [PATCH 00/44] hw/arm: New board model mps3-an547 Message-Id: <20210219144617.4782-1-peter.maydell(a)linaro.org> Added: <2021-02-20 Sat> * [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> Added: <2021-02-16 Tue> -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] 22-26 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a few regressions to bisect. Fixed a minor testcase issue * GCC - MVE autovectorization: Working on vcmp. After some cleanup & factorization, the cmp operators work on GCC vectors. I will now resume work on auto-vectorization. * Misc - fixes in stm32 benchmarking harness == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending 21 Feb 2021

by Richard Henderson

* After proving that the aarch64 host problem with booting s390x with virtio was lack of barriers for the guest memory model, I've spent some time working on a ld-acq/st-rel optimizer for tcg. * Minor rev of tci rewrite. * Some patch review on claudio's kvm/tcg split. r~

4 years, 10 months

1
0
0 0

[ACTIVITY] week ending Feb. 21 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Wrote a short pitch deck for Stratos - AGL Follow-up sync discussion - lead to thinking about measuring the impact of buffer copy for virtio-gpu guests Message-Id: <87y2fmsrxw.fsf(a)linaro.org> - [Stratos Sync - this week discussing virtio-i2c] - spent some time discussing firmer requirements for the work [Stratos Sync - this week discussing virtio-i2c] <https://collaborate.linaro.org/display/STR/2021-02-18+Project+Stratos+Sync+…> VirtIO RPMB ([STR-5]) - More work on the [Rust version of virtio-rpmb] - after debugging vhost reply_ack negotiation issues Message-Id: <8735xskm7j.fsf(a)linaro.org> now can boot kernel - next step processing the actual RPMB frames [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/15] testing and gdbstub updates Message-Id: <20210215094244.12716-1-alex.bennee(a)linaro.org> - posted [PATCH v2] meson.build: expose TCG cross compiler information in summary Message-Id: <20210216102522.6279-1-alex.bennee(a)linaro.org> - posted [PATCH v3 00/23] plugins/next pre-PR (hwprofile, regression fixes, icount count fix) Message-Id: <20210213130325.14781-1-alex.bennee(a)linaro.org> - posted [PULL 00/23] plugin updates (hwprofile, CF_NOCACHE, io_recompile) Message-Id: <20210218094706.23038-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/6] my current testing/next queue (meson/gitlab/fedora bump) Message-Id: <20210217121932.19986-4-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [8/8] ======================= [PATCH] linux-user/elfload: munmap proper address in pgd_find_hole_fallback Message-Id: <20210131061849.12615-1-vfazio(a)xes-inc.com> [PATCH] linux-user/elfload: do not assume MAP_FIXED_NOREPLACE kernel support Message-Id: <20210131061930.14554-1-vfazio(a)xes-inc.com> [RFC v18 00/15] i386 cleanup PART 2 Message-Id: <20210212123622.15834-1-cfontana(a)suse.de> [PATCH v2] target/mips: fetch code with translator_ld Message-Id: <20210125105818.2707067-1-f4bug(a)amsat.org> [PATCH] travis.yml: Limit simultaneous jobs to 3 Message-Id: <20210217102531.1441557-1-thuth(a)redhat.com> [PATCH] gitlab-ci: Display Avocado log content when tests timeout Message-Id: <20210215171438.935665-1-philmd(a)redhat.com> [PATCH] gitlab-ci.yml: Run check-tcg with TCI Message-Id: <20210127055903.40148-1-thuth(a)redhat.com> [PATCH] docker: Bump Fedora images to release 33 Message-Id: <20210118181255.314672-1-philmd(a)redhat.com> Absences ======== - Lockdown 3: No schooling, just half term distractions! Current Review Queue ==================== * [PATCH v20 00/17] i386 cleanup PART 2 Message-Id: <20210218172156.25520-1-cfontana(a)suse.de> Added: <2021-02-19 Fri> * [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> Added: <2021-02-16 Tue> * [PATCH v2 00/15] tcg/arm: host neon support Message-Id: <20210208024625.271018-1-richard.henderson(a)linaro.org> Added: <2021-02-08 Mon> -- Alex Bennée

4 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 19 Feb

by Peter Maydell

Progress: * QEMU-364 [QEMU support for ARMv8.1-M extensions] + sent out v2 of the MPS3-AN524 series (minor changes only) + discovered that I need to implement the SSE-300's System Counter + implemented the system counter, did some final testing and reviewing, and sent out v1 of the MPS3-AN547 series to the list + once these patches are reviewed and in master the QEMU-413 epic will be complete -- PMM

4 years, 10 months

1
0
0 0

Many of your builders are red for long time

by Galina Kistanova

Hello Linaro Toolchain Working Group, libcxx-libcxxabi-libunwind-armv8-linux has been red for 5 days. clang-cmake-aarch64-global-isel has been red for 10 days. clang-cmake-aarch64-quick has been red for 10 days. clang-cmake-armv7-global-isel has been red for 10 days. clang-cmake-armv7-lnt has been red for 10 days. clang-cmake-aarch64-lld has been red for 11 days. clang-cmake-armv8-lld has been red for 11 days. clang-cmake-thumbv7-full-sh has been red for 11 days. clang-cmake-armv7-full has been red for 11 days. Is anybody looking at this? I also noticed that some of your workers are less reliable than others. For example, inaro-tk1-09 worker was last time producing a green build 2 months ago - http://lab.llvm.org:8011/#/workers/2?numbuilds=500 I'm removing the linaro-tk1-09 worker from the production buildbot for now. Please feel free to connect it to the staging and make the builder reliably green. Then it could be returned back to the production. linaro-armv8-windows-msvc-01 and linaro-armv8-windows-msvc-02 have been red for the least 4 months. I'm removing them from the production buildbot. You can return them back to production after they are reliably green in the staging. Please feel free to ask if you have questions. Thanks Galina

4 years, 10 months

3
7
0 0

[ACTIVITY] 8-12 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a few regressions to bisect. Fixed a minor testcase issue - native validation in Linaro's lab: we still see a few random results * GCC - MVE autovectorization: Working on vcmp. * Misc - fixes in stm32 benchmarking harness == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking Holidays next week, back Monday 22nd Feb

4 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 12 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + sent out a small code-cleanup patchset for some arm display device models to remove no-longer-needed support for non-32bpp outputs + tracked down (with the aid of Paolo) why our build system had started building the documentation every time you run 'make'; sent a fix + code review todo queue status: 12 items, but the oldest was only sent to the list on Monday... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + An MPS3 Cortex-M55 FPGA image is now publicly available: the AN547. We'll provide a model of this in QEMU. Started working on the patchseries to implement it (relatively small changes on top of the SSE-300 work I've already done but not sent out, and the mps3-an524 series I sent out for review last week). This is basically code-complete but I need to do some more testing and ideally I'd like the AN524 series to get reviewed before I send out another 40-patch series that would have to be based on top of that one. thanks -- PMM

4 years, 10 months

1
0
0 0

Re: [lldb-dev] 12.0.0-rc1 Release has been tagged

by Diana Picus

Hello, I've uploaded binaries for Windows on Arm: 081373cc76e88224020fea42eba2161d972f03bb83ebc055fb3cd4f2cfcdfb95 LLVM-12.0.0-rc1-woa64.exe It was built from the current release/12.x branch (commit b46924ee) with two patches applied on top: - https://reviews.llvm.org/D96259 - https://reviews.llvm.org/D96498 It contains "clang;clang-tools-extra;lld;compiler-rt” projects. Compiler-RT has sanitizers disabled (MEMPROF and XRAY use sanitizer infrastucture). I.e., === + -DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;lld;compiler-rt" ^ + -DCOMPILER_RT_BUILD_SANITIZERS=OFF ^ + -DCOMPILER_RT_BUILD_MEMPROF=OFF ^ + -DCOMPILER_RT_BUILD_XRAY=OFF ^ === I've attached the changes we had to make to llvm/utils/releases/build_llvm_package.bat. @Maxim Kuvyrkov is going to clean them up and post a patch in the next couple of weeks (he's been doing all the hard work, I'm just uploading). This is the first time we're trying to provide a release for Windows on Arm, so if anyone has any comments or questions, feel free to send an email :) Cheers, Diana On Thu, 28 Jan 2021 at 05:05, Tom Stellard via lldb-dev < lldb-dev(a)lists.llvm.org> wrote: > Hi, > > I've tagged the 12.0.0-rc1 release. Testers can begin testing and upload > binaries. > > -Tom > > _______________________________________________ > lldb-dev mailing list > lldb-dev(a)lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-dev >

4 years, 10 months

1
0
0 0

[ACTIVITY] week ending Feb. 7 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - TSC Stratos next cycle presentation - [Stratos Sync - this week discussing Rust] - Followed up on Rust presentation and sketched out some areas of interest [STR-9] <https://projects.linaro.org/browse/STR-9> [Stratos Sync - this week discussing Rust] <https://collaborate.linaro.org/display/STR/2021-02-04+Project+Stratos+Sync+…> QEMU Support for Xen ([STR-20]) =============================== - latest iteration of [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> - while re-basing [my Xen loader and fixes tree] - realised that [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Message-Id: <20200929224355.1224017-1-philmd(a)redhat.com> would be useful - which awaits [PATCH v14 00/22] i386 cleanup PART 2 Message-Id: <20210128092814.8676-1-cfontana(a)suse.de> being merged - bunch of related review of pre-cursor stuff [STR-20] <https://projects.linaro.org/browse/STR-20> [my Xen loader and fixes tree] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Upstream Work ([UM-2]) =========================== - caught up on a bunch of review - got about halfway through rth's mega TCI series - posted [PATCH v1 00/15] testing/gdbstub/docs pre-PR Message-Id: <20210202134001.25738-1-alex.bennee(a)linaro.org> - will roll PR on Monday - some discussion on Detecting Faulting Instructions From Plugins Message-Id: <YBTRSK4/F5KLH+FZ(a)strawberry.localdomain> - looks like we need special handling for instrumentation on recompiled IO ops [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [5/5] ======================= [PATCH 00/10] target: Provide target-specific Kconfig Message-Id: <20210131111316.232778-1-f4bug(a)amsat.org> [PATCH v3 0/5] Fix some style problems in contrib Message-Id: <20210118031004.1662363-1-zhouyang789(a)huawei.com> [PATCH v15 00/23] i386 cleanup PART 2 Message-Id: <20210201100903.17309-1-cfontana(a)suse.de> [PATCH 00/22] Acceptance Test: introduce base class for Linux based tests Message-Id: <20210203172357.1422425-9-crosa(a)redhat.com> [PATCH v2 0/5] Move remaining x86 Travis jobs to the gitlab-CI Message-Id: <20210205091857.845389-1-thuth(a)redhat.com> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v6 00/11] Support disabling TCG on ARM (part 2) Message-Id: <20210131115022.242570-1-f4bug(a)amsat.org> Added: <2021-01-31 Sun> * [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-29 Fri> * [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Message-Id: <20210124025306.3949-1-leif(a)nuviainc.com> Added: <2021-01-25 Mon> -- Alex Bennée

4 years, 10 months

1
0
0 0

[ACTIVITY] 1-5 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - not really catching up, now ~15 days late due to the numerous commits. Manually fast-forwarded the latest build to today. I'll bisect manually for regressions if needed. - re-enabled native validation in Linaro's lab: we are sending test results again * GCC - MVE autovectorization: vorn patch committed. Working on vcmp. == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 5 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + lots of code review this week, including another round of rth's MTE user-mode patchset * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Sent out an RFC proposing some more Clock API changes (since it'll be a while before I'm ready to post the series with the new timer device that requires them) + The SSE-200 Cortex-M33-based MPS3 AN524 FPGA image is a useful target to model: the Zephyr folks would like it, and it is a good stepping stone to an MPS3 FPGA image with a Cortex-M55/SSE-300 in it. Wrote a patchset for an mps3-an524 board model, and sent it out for review. -- PMM

4 years, 10 months

1
0
0 0

an Ubuntu test rebuild with LTO turned on

by Matthias Klose

Please see https://lists.ubuntu.com/archives/ubuntu-devel/2021-January/041341.html https://wiki.ubuntu.com/ToolChain/LTO Some builds only fail on AArch64, these are: buildlog_ubuntu-hirsute-arm64.abiword_3.0.4~dfsg-2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.adabrowse_4.0.3-12_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.adacontrol_1.21r6b-5_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.armnn_19.11.1-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.cctools_7.1.2-2ubuntu3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.csound_1:6.14.0~dfsg-6build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.dh-ada-library_6.20_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.dietlibc_0.34~cvs20160606-12_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.entropybroker_2.9-3build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.fpc_3.2.0+dfsg-8build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.grcompiler_5.2-2.1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.haskell-hopenpgp-tools_0.23.1-1build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ignition-common_3.5.0+dfsg1-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.lazarus_2.0.10+dfsg-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.lepton-eda_1.9.13-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.libcxx-serial_1.2.1-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.minetest_5.3.0+repack-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ogre-1.12_1.12.5+dfsg1-1ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.openmsx_16.0-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.parsinsert_1.04-7ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.prometheus-alertmanager_0.21.0+ds-2build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.pyqt5_5.15.2+dfsg-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.racon_1.4.13-2build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.rampler_1.1.1-3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ruby-http-parser.rb_0.6.0-5_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.shasta_0.6.0-4build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.snd_20.9-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.sogo_4.3.2-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.swiglpk_4.65.0-2build3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.synfig_1.2.2+dfsg-3build3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.synfigstudio_1.2.2-1build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.tcc_0.9.27+git20200814.62c30a4a-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.unar_1.10.1-2build9_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.valgrind_1:3.16.1-1ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.vulkan-tools_1.2.154.0+dfsg1-1_BUILDING.txt.gz arm64 Note that some of those like the Ada related ones are false positives, and I didn't look at the arm64 specific issues yet. All builds were done using the GCC 10 branch. Matthias

4 years, 10 months

2
2
0 0

[ACTIVITY] week ending Jan. 31 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - some prep for next weeks TSC QEMU Device and Machine Models ([QEMU-418]) =========================================== - added a bunch of new cards for ARMv8.7 features using ARMs new feature type QEMU Support for Xen ([STR-20]) =============================== - latest iteration of [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> - while re-basing [my Xen loader and fixes tree] - realised that [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Message-Id: <20200929224355.1224017-1-philmd(a)redhat.com> would be useful - which awaits [PATCH v14 00/22] i386 cleanup PART 2 Message-Id: <20210128092814.8676-1-cfontana(a)suse.de> being merged [STR-20] <https://projects.linaro.org/browse/STR-20> [my Xen loader and fixes tree] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/2] meson fixups for check-tcg/softfloat Message-Id: <20210126145356.7860-1-alex.bennee(a)linaro.org> - posted some documentation patches while helping LKFT team get up and running - [PATCH] docs/system: document an example vexpress-a15 invocation Message-Id: <20210128185300.2875-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH v4 0/4] meson: Try to clarify TCG / TCI options for new users Message-Id: <8f1f2dc6-5ad2-7d48-c2f9-9afa1e4d4065(a)weilnetz.de> [PATCH 00/23] TCI fixes and cleanups Message-Id: <20210128082331.196801-1-richard.henderson(a)linaro.org> [PATCH] accel/tcg: Add URL of clang bug to comment about our workaround Message-Id: <20210129130330.30820-1-peter.maydell(a)linaro.org> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-29 Fri> * [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Message-Id: <20210124025306.3949-1-leif(a)nuviainc.com> Added: <2021-01-25 Mon> * [PATCH v3 00/21] target-arm: Implement ARMv8.5-MemTag, user mode Message-Id: <20210115224645.1196742-1-richard.henderson(a)linaro.org> Added: <2021-01-18 Mon> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> -- Alex Bennée

4 years, 10 months

1
0
0 0

[ACTIVITY] 25-29 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - not really catching up, now ~10 days late due to the numerous commits * GCC - Neon intrinsics: vceqzq improvement (PR98730) commited - MVE autovectorization: vorn patch submitted - opened PR98891 about Neon vectorization regression * infra: - reviewed patches. - ABE's make-check-gcc is currently broken == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 29 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + usual upstream maintenance, code review, etc * QEMU-364 [QEMU support for ARMv8.1-M extensions] + CMSDK Clock changes now upstream + When integrating those with the SSE timer model, found what seem like some more clock API changes we could use; patches in progress Some Arm-internal training and similar admin tasks this week. thanks -- PMM

4 years, 10 months

1
0
0 0

[ACTIVITY] week ending 24 Jan 2021

by Richard Henderson

[UM-61 TCG Maint] 3 different attempts at fixing the out-of-temps failure produced by the tcg-constant patch set. The last, longjmp to restart w/ a smaller tb, seems unlikely to have unanticipated side effects. [UM-2 QEMU Maint] Refresh two patches toward cortex-a76. Misc patch review. Partial fix for target/ppc mis-use of tb->flags. r~

4 years, 11 months

1
0
0 0

[ACTIVITY] week ending Jan. 24 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted Project Stratos planning priorities for the next development cycle (-> Oct2021) Message-Id: <87im7rtpyq.fsf(a)linaro.org> - baring feedback from members during voting I think this is what we are doing - attended [AGL discussion] on zero-copy for virtio-gpu with Peter Griffin - more meetings on other collaboration opportunities, drew more slide ware - bootstrapped my RB5 rig, just need to figure out how to update the kernel [STR-9] <https://projects.linaro.org/browse/STR-9> [AGL discussion] <https://confluence.automotivelinux.org/display/VE/Meeting+Agenda?src=contex…> QEMU Device and Machine Models ([QEMU-418]) =========================================== - flurry of syncing and card creation, solidified [QEMU-414] [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> [QEMU-414] <https://projects.linaro.org/browse/QEMU-414> QEMU Support for Xen ([STR-20]) =============================== - continued looking at [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> [STR-20] <https://projects.linaro.org/browse/STR-20> QEMU Upstream Work ([UM-2]) =========================== - respun [PULL v2 00/30] testing, gdbstub and semihosting Message-Id: <20210118111745.20104-1-alex.bennee(a)linaro.org> to fix NetBSD issue - posted [PATCH v1 0/6] testing/next (docker binfmt tests) Message-Id: <20210119175208.763-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/8] testing/next (docker, binfmt, gdb version) Message-Id: <20210122181854.23105-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [4/4] ======================= [PATCH] util/log: flush TB cache when log level changes Message-Id: <161130982491.1038646.15688151175539344664.stgit@pasha-ThinkPad-X280> [PATCH v3] hw/core/qdev-properties-system: Rewrite set_pci_host_devaddr using GLib Message-Id: <20201125083300.861206-1-philmd(a)redhat.com> [RFC PATCH] tests/docker: Allow passing --network option when building images Message-Id: <20210119054502.531451-1-f4bug(a)amsat.org> [PATCH] tcg: Increase the static number of temporaries Message-Id: <20210121025439.1120405-1-richard.henderson(a)linaro.org> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v3 00/21] target-arm: Implement ARMv8.5-MemTag, user mode Message-Id: <20210115224645.1196742-1-richard.henderson(a)linaro.org> Added: <2021-01-18 Mon> * [PATCH 0/6] accel: Restrict TCG-specific code Message-Id: <20210117164813.4101761-1-f4bug(a)amsat.org> Added: <2021-01-18 Mon> * [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-13 Wed> * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> -- Alex Bennée

4 years, 11 months

1
0
0 0

[ACTIVITY] 18-22 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - catching up, still ~1 week late due to the numerous commits * GCC - Neon intrinsics: looking at vceqzq improvement (PR98730) - MVE autovectorization: WIP on vorn and vcmp. - helping with cortex-m0 libgcc patch validation. Opened PR98779 about issues in libgcc wrt -mpure-code. * infra: - reviewed patches. - ABE's make-check-gcc is currently broken == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 22 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review (including RTH's MTE-for-user-mode-emulation) + Investigating an intermittent failure of a test case involving an s390 guest on aarch64 hosts... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Converted the ARMSSE (IoTKit/SSE-200) code over to use the Clock framework, which was added to QEMU after ARMSSE was first written. (This is a prereq for adding the new-in-SSE-300 timer device, which will use Clocks.) Sent the patches out for review. I'm currently experimenting with a schedule of: Mon: JIRA task work; Tue: code review; Thu: JIRA task work; Fri: misc upstream thanks -- PMM

4 years, 11 months

1
0
0 0

[ACTIVITY] week ending 17 Jan 2021

by Richard Henderson

[UM-61 TCG Maint] Refresh tcg backend constraints. Pull request for tcg constants. -- which caused reported failures. [UM-2 QEMU Maint] Refresh sve pred_desc fixes. Refresh arm alignment fixes. Misc review. [QEMU-344 ARMv8.5-MemTag] Refresh mte user-only patch set. r~

4 years, 11 months

1
0
0 0

Re: Compilation issue with Linaro ARM toolchain

by Mathieu Poirier

Adding the Linaro toolchain group mailing list. On Mon, Jan 18, 2021 at 05:49:39PM +0300, Sergey Suloev wrote: > Hi, guys, > > I am having an issue builduing kernel 5.11 (rc4) with Linaro ARM toolchain. > The issue seems to be related to CC plugins sources. > Here is my build log: https://pastebin.com/DTn7Szax. I have never seen this > before with versions 5.10 and below. > > Thank you, > Sergey > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel(a)lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

4 years, 11 months

3
2
0 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

linaro-toolchain