- linaro-toolchain - lists.linaro.org

[ACTIVITY] week ending 14 Mar 2021

by Richard Henderson

[UM-2] * Clean up tcg code_gen_buffer mapping. * Clean up ppc tb->flags madness. * Rebase tci clean up. * Random patch review. [VIRT-349] * Send v4 of sve2 patch set. r~

4 years, 3 months

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[ACTIVITY] week ending Mar. 14 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - attended the [rust-vmm sync call] [rust-vmm sync call] <https://etherpad.opendev.org/p/rust-vmm-sync-2021> VirtIO RPMB ([STR-5]) - followed more of [RFC PATCH 0/5] RPMB internal and user-space API + WIP virtio-rpmb frontend Message-Id: <CACRpkda9f-BNmu-CaNsghnDoOcSXvvvji=tag2Xos+tg_nNZ0w(a)mail.gmail.com> [STR-5] <https://projects.linaro.org/browse/STR-5> [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [qemu-web PATCH] pages: update deprecation policy links to "official" manual Message-Id: <20210308103049.3653-1-alex.bennee(a)linaro.org> - posted [qemu-web RFC PATCH] _download/source.html: show the GPG fingerprint for releases Message-Id: <20210308111649.14898-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/4] semihosting/next (SYS_HEAPINFO fix) Message-Id: <20210309141727.12522-1-alex.bennee(a)linaro.org> - posted [PULL 00/18] testing, docs, semihosting move and guest-loader Message-Id: <20210308135104.24903-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/15] testing, docs, semihosting move and guest-loader Message-Id: <20210310160002.11659-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/7] testing/next (hexagon 2, electric boogaloo) Message-Id: <20210310192331.29284-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/15] testing, docs, semihosting move and guest-loader Message-Id: <20210310160002.11659-1-alex.bennee(a)linaro.org> - posted [PATCH v3 0/4] semihosting/next (SYS_HEAPINFO) Message-Id: <20210309172127.20470-1-alex.bennee(a)linaro.org> - posted [PATCH v5 0/5] semihosting/next (SYS_HEAPINFO) Message-Id: <20210312102029.17017-1-alex.bennee(a)linaro.org> - posted [PATCH v1 00/14] plugins/next (phys addr, syscalls, lots of docs) Message-Id: <20210312172821.31647-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH v2] linux-user: Fix executable page of /proc/self/maps Message-Id: <20210308091959.986540-1-nsurbayrole(a)quarkslab.com> [PATCH] plugins: new syscalls plugin Message-Id: <20200812115816.4454-1-matthias(a)weckbecker.name> Added: <2020-08-12 Wed> [PATCH v2] plugins: Expose physical addresses instead of device offsets Message-Id: <20210309202802.211756-1-aaron(a)os.amperecomputing.com> Absences ======== - Lockdown 3: Half day schooling - ends soon! Current Review Queue ==================== TODO [PATCH 0/4] Upgrade Meson to 0.57.x Message-Id: <20210310104937.253532-1-pbonzini(a)redhat.com> ================================================================================================= TODO [RFC v3 00/23] arm cleanup experiment for kvm-only build Message-Id: <20210303114053.20305-1-cfontana(a)suse.de> ================================================================================================================== Added: <2021-03-04 Thu> TODO [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> =================================================================================================================== Added: <2021-02-16 Tue> TODO [PATCH v2 00/15] tcg/arm: host neon support -- Alex Bennée

4 years, 3 months

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[ACTIVITY] 8-12 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - Bisected last week regressions, but there had already been reported/fixed. * GCC - MVE autovectorization: - vcmp support mostly complete. support of FP types looks OK, though trickier than expected. - vld2/vst2 and vld4/vst4 done. * Misc - stm32 benchmarking harness: good speed up after removing useless toolchain multilib builds (7 minutes vs 1h+) - fixed GCC bisect Jenkins job == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * Resume GDB/FDPIC work * Troubleshoot Jenkins problems

4 years, 3 months

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[ACTIVITY] report week ending 12 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Mostly caught up on code review now: have done all the patches that are targeting 6.0 - Sent out some pullreqs with for-6.0 material - Wrote a patch to make us emulate the right number of counters for the PMU according to what each CPU should have, rather than always 4 - Had a go at fixing the M-profile vector table load on reset to handle aliased memory regions * QEMU-364 [QEMU support for ARMv8.1-M extensions] - mps3-an524 and -an547 patchseries now in master: this epic is done! thanks -- PMM

4 years, 3 months

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Pre-commit CI with libc++

by Louis Dionne

Folks, I am pleased to announce the move of libc++ to pre-commit CI. Over the past few months, we have set up Buildkite jobs on top of the Phabricator integration built by Mikhail and Christian, and we now run almost all of the libc++ build bots whenever a Phabricator review is created. The bots also run when a commit is pushed to the master branch, similarly to the existing Buildbot setup. You can see the libc++ pipeline in action here: https://buildkite.com/llvm-project/libcxx-ci. This is great -- we’ve been waiting to set up pre-commit CI for a long time, and we’ve seen a giant productivity gain since it’s up. I think everyone who contributes to libc++ greatly benefits, seeing how reviews are now used to trigger CI and improve our confidence in changes. This change does have an impact on existing build bots that are not owned by one of the libc++ maintainers. While I transferred the build bots that we owned (which Eric had set up) to Buildkite, the remaining build bots will have to be moved to Buildkite by their respective owners. These builds bots are (owners in CC): libcxx-libcxxabi-x86_64-linux-debian libcxx-libcxxabi-x86_64-linux-debian-noexceptions libcxx-libcxxabi-libunwind-x86_64-linux-debian libcxx-libcxxabi-singlethreaded-x86_64-linux-debian libcxx-libcxxabi-libunwind-armv7-linux libcxx-libcxxabi-libunwind-armv8-linux libcxx-libcxxabi-libunwind-armv7-linux-noexceptions libcxx-libcxxabi-libunwind-armv8-linux-noexceptions libcxx-libcxxabi-libunwind-aarch64-linux libcxx-libcxxabi-libunwind-aarch64-linux-noexceptions The process of moving these bots over to Buildkite is really easy. Please take a look at the documentation at https://libcxx.llvm.org/docs/AddingNewCIJobs.html#addingnewcijobs and contact me if you need additional help. To make sure we get the full benefits of pre-commit CI soon, I would like to put a cutoff date on supporting the old libc++ builders at http://lab.llvm.org:8011/builders. I would propose that after January 1st 2021 (approx. 1 month from now), the libc++ specific build bots at lab.llvm.org be removed in favor of the Buildkite ones. If you currently own a bot, please make sure to add an equivalent Buildkite bot by that cutoff date to make sure your configuration is still supported, or let me know if you need an extension. Furthermore, with the ease of creating new CI jobs with this infrastructure, we will consider any libc++ configuration not covered by a pre-commit bot as not explicitly supported. It doesn’t mean that such configurations won’t work -- it just means that we won’t be making bold claims about supporting configurations we’re unable to actually test. So if you care about a configuration, please open a discussion and let’s see how we can make sure it's tested properly! I am thrilled to be moving into the pre-commit CI era. The benefits we see so far are huge, and we're loving it. Thanks, Louis PS: This has nothing to do with a potential move or non-move to GitHub. The current pre-commit CI works with Phabricator, and would work with GitHub if we decided to switch. Let’s try to keep those discussions separate :-). PPS: We’re still aiming to support non libc++ specific Buildbots. For example, if something in libc++ breaks a Clang bot, we’ll still be monitoring that. I’m just trying to move the libc++-specific configurations to pre-commit.

4 years, 3 months

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[ACTIVITY] week ending 7 Mar 2021

by Richard Henderson

[VIRT-349 # QEMU SVE2 Support ] I have a working FVP SVE2 install! I used a new FVP version (11.13.36) from the last time that I tried (11.13.21 on Jan 27). I used a debian-testing snapshot from 1-MAR, which has linux 5.10 bundled, and fvp revc dtb installed. I used https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.gi… (which is linked to by one of the howtos that Peter forwarded) and chose the "pre-built uefi" version. I need to report a bug on this build script -- the "build from source" option does not work on a system that has all python3 and no python2. I've rebuilt all of the risu trace files for vq=4 (512-bit). I'm now refreshing my qemu branch to test. [UM-61 # TCG Core Maintainership ] PR for patch queue; aa64 fixes, tci fixes, tb_lookup cleanups. [UM-2 # Upstream Maintainership ] Patch review, mostly v8.1m board stuff. r~

4 years, 3 months

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[ACTIVITY] week ending Mar. 7 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted [PATCH v2] vhost-user.rst: add clarifying language about protocol negotiation Message-Id: <20210303145011.14547-1-alex.bennee(a)linaro.org> Linux Userspace ABI for RPMB devices ([STR-31]) ----------------------------------------------- - posted [RFC PATCH 0/5] RPMB internal and user-space API + WIP virtio-rpmb frontend Message-Id: <20210303135500.24673-1-alex.bennee(a)linaro.org> - has stimulated discussion on the thread, will see next posting from Thomas QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/9] testing/next (docs, hexagon, cfi, docker) Message-Id: <20210305092328.31792-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/3] semihosting/next (move from hw, heapinfo) Message-Id: <20210305135451.15427-1-alex.bennee(a)linaro.org> - optimising tb lookup ---------------------- - CLOSING NOTE [2021-03-05 Fri 17:22] rth merged my changes plus a pre-compute of cflags. Completed Reviews [8/8] ======================= [PATCH v3 0/2] gitlab-ci.yml: Add jobs to test CFI Message-Id: <20210304030948.9367-1-dbuono(a)linux.vnet.ibm.com> [PATCH 0/4] hexagon: Add Docker image & testing to gitlab-ci Message-Id: <20210228222314.304787-1-f4bug(a)amsat.org> - CLOSING NOTE [2021-03-04 Thu 20:04] Queued to my tree Added: <2021-03-02 Tue> [PATCH v2] tests/docker: Use --arch-only when building Debian cross image Message-Id: <20210223211115.2971565-1-f4bug(a)amsat.org> [PATCH] linux-user: Adjust pgd_find_hole_fallback result with guest_loaddr Message-Id: <20210303094919.x6wnlh6qulx72fz6(a)titan.localdomain> - CLOSING NOTE [2021-03-05 Fri 14:12] Added: <2021-03-03 Wed> [PATCH 00/44] hw/arm: New board model mps3-an547 Message-Id: <20210219144617.4782-1-peter.maydell(a)linaro.org> - CLOSING NOTE [2021-03-05 Fri 14:14] Looks like others have already looked over it. ADDED: <2021-03-04 Thu> [PATCH v3 00/70] TCI fixes and cleanups Message-Id: <20210208023752.270606-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2021-03-05 Fri 16:59] v4 released, wish I'd noticed earlier ;-) Added: <2021-02-08 Mon> [PATCH 00/27] tcg patch queue Message-Id: <20210302175741.1079851-1-richard.henderson(a)linaro.org> [PATCH 0/3] docs: replace master/slave with more accurate wording Message-Id: <20210226143413.188046-1-pbonzini(a)redhat.com> Absences ======== - Lockdown 3: Half day schooling - ends soon! Current Review Queue ==================== TODO [RFC v3 00/23] arm cleanup experiment for kvm-only build Message-Id: <20210303114053.20305-1-cfontana(a)suse.de> ================================================================================================================== Added: <2021-03-04 Thu> TODO [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> =================================================================================================================== Added: <2021-02-16 Tue> TODO [PATCH v2 00/15] tcg/arm: host neon support Message-Id: <20210208024625.271018-1-richard.henderson(a)linaro.org> ================================================================================================================== Added: <2021-02-08 Mon> -- Alex Bennée

4 years, 3 months

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[ACTIVITY] report week ending 5 Mar

by Peter Maydell

Progress (short week, 2 days): * Some time spent on setting up new work laptop * Started in on the pile of code review that had built up while I was on holiday... made a bit of progress and sent out one pullreq. Queue length now: 16 series. thanks -- PMM

4 years, 3 months

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What does suffix ' ... isra.0' mean in compiled symbols in GCC 10.2?

by Guodong Xu

Hi, all Does anybody know what does '.....isra.0' mean in GCC 10.2 compiled objects? I just noticed this issue when using bcc/eBPF tools. I submitted the detail into * https://github.com/iovisor/bcc/issues/3293 Simply put, when building a linux kernel with GCC 10.2, the symbol 'finish_task_switch' becomes 'finish_task_switch.isra.0' in the object (as reported by 'nm') Because a lot of kernel tracers (such as bcc) use 'finish_task_switch' as the probe point, this change in the compilation result can make all result such tools fail. Thanks. Best regards, Guodong Xu

4 years, 3 months

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[ACTIVITY] 1-5 March 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a couple of regressions to bisect. - minor testcase fix - reported a couple of new failures * GCC - MVE autovectorization: - vcmp support mostly complete. Minor update needed to support FP types. - working on interleaved vector load/store support * Misc - fixed stm32 benchmarking harness, it's working again. - submitted patches to reduce the toolchain build time (for benchmarking we don't need all multilibs which take ages to build) == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 3 months

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Clang targetting x64 linker

by Joel Cox

Hi I've been trying to run clang on a Windows on Arm machine, but it keeps trying to using the link.exe located in "Visual studio/..../Host64/arm64", which is (seemingly) an x64 tool and as such doesn't run, and crashes the process. Is there a way to set clang to look at VS's x86 link.exe? Or if there is an arm64 version that clang should be using instead? Thanks, Joel IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 3 months

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LLVM12 Clang doesn't start

by Joel Cox

Hi, I've been trying to use clang on Windows on Arm machine (Samsung Galaxy Book S), but whenever I try to use it, I get either nothing (in powershell) or an error popup: "The application was unable to start correctly (0x000007b)". The release I'm using is LLVM-12.0.0-rc1-woa64.exe<https://github.com/llvm/llvm-project/releases/download/llvmorg-12.0.0-rc1/L…> from https://github.com/llvm/llvm-project/releases/tag/llvmorg-12.0.0-rc1 I have a feeling there might be a library or dependency I am missing. Any help with how to resolve this issue would be appreciated. Thanks, Joel IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

4 years, 4 months

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[ACTIVITY] week ending 28 Feb 2021

by Richard Henderson

[UM-2 # QEMU Upstream Work] * A lot of patch review. * Some target/i386 cleanup, as followup to said patch review. * Collecting patches for tcg-next. r~

4 years, 4 months

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[ACTIVITY] week ending Feb. 28 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - some planning discussion around STR-26/STR-7 - posted vhost reply_ack negotiation (a.k.a differences in vhost-user behaviour with libvhost-user and vhost-user-backend.rs) Message-Id: <8735xskm7j.fsf(a)linaro.org> - posted [vhost.rs PR] - posted [VHOST USER SPEC PATCH] vhost-user.rst: add clarifying language about protocol negotiation Message-Id: <20210226111619.21178-1-alex.bennee(a)linaro.org> [vhost.rs PR] <https://github.com/rust-vmm/vhost/pull/24> [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v2 0/6] testing/next (meson check-tcg, fedora bump, docs) Message-Id: <20210222101455.12640-1-alex.bennee(a)linaro.org> - posted [PULL 0/7] testing updates (build, docs, dumps) Message-Id: <20210224114926.6303-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Other ===== - some kernel/QEMU debugging for LKFT folks Completed Reviews [4/4] ======================= [PATCH v20 00/17] i386 cleanup PART 2 Message-Id: <20210218172156.25520-1-cfontana(a)suse.de> - CLOSING NOTE [2021-02-22 Mon 13:28] Only glanced over, mainly in prep for ARM series which is based on this Added: <2021-02-19 Fri> [PATCH] tests/docker: Use --arch-only when building Debian cross images Message-Id: <20210223170910.2916721-1-f4bug(a)amsat.org> [PATCH v5 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20210219215838.752547-4-crosa(a)redhat.com> [PATCH 0/3] gitlab-pipeline-status script: provide more information on errors Message-Id: <20210222193240.921250-2-crosa(a)redhat.com> Absences ======== - Lockdown 3: Half home-schooling Current Review Queue ==================== * [PATCH 0/2] semihosting: Move it out of hw/ Message-Id: <20210226131356.3964782-1-f4bug(a)amsat.org> Added: <2021-02-26 Fri> * [RFC v1 00/38] arm cleanup experiment for kvm-only build Message-Id: <20210221092449.7545-1-cfontana(a)suse.de> Added: <2021-02-21 Sun> * [PATCH 00/44] hw/arm: New board model mps3-an547 Message-Id: <20210219144617.4782-1-peter.maydell(a)linaro.org> Added: <2021-02-20 Sat> * [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> Added: <2021-02-16 Tue> -- Alex Bennée

4 years, 4 months

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[ACTIVITY] 22-26 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a few regressions to bisect. Fixed a minor testcase issue * GCC - MVE autovectorization: Working on vcmp. After some cleanup & factorization, the cmp operators work on GCC vectors. I will now resume work on auto-vectorization. * Misc - fixes in stm32 benchmarking harness == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 4 months

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[ACTIVITY] week ending 21 Feb 2021

by Richard Henderson

* After proving that the aarch64 host problem with booting s390x with virtio was lack of barriers for the guest memory model, I've spent some time working on a ld-acq/st-rel optimizer for tcg. * Minor rev of tci rewrite. * Some patch review on claudio's kvm/tcg split. r~

4 years, 4 months

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[ACTIVITY] week ending Feb. 21 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Wrote a short pitch deck for Stratos - AGL Follow-up sync discussion - lead to thinking about measuring the impact of buffer copy for virtio-gpu guests Message-Id: <87y2fmsrxw.fsf(a)linaro.org> - [Stratos Sync - this week discussing virtio-i2c] - spent some time discussing firmer requirements for the work [Stratos Sync - this week discussing virtio-i2c] <https://collaborate.linaro.org/display/STR/2021-02-18+Project+Stratos+Sync+…> VirtIO RPMB ([STR-5]) - More work on the [Rust version of virtio-rpmb] - after debugging vhost reply_ack negotiation issues Message-Id: <8735xskm7j.fsf(a)linaro.org> now can boot kernel - next step processing the actual RPMB frames [Rust version of virtio-rpmb] <https://github.com/stsquad/virtio-rpmb> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/15] testing and gdbstub updates Message-Id: <20210215094244.12716-1-alex.bennee(a)linaro.org> - posted [PATCH v2] meson.build: expose TCG cross compiler information in summary Message-Id: <20210216102522.6279-1-alex.bennee(a)linaro.org> - posted [PATCH v3 00/23] plugins/next pre-PR (hwprofile, regression fixes, icount count fix) Message-Id: <20210213130325.14781-1-alex.bennee(a)linaro.org> - posted [PULL 00/23] plugin updates (hwprofile, CF_NOCACHE, io_recompile) Message-Id: <20210218094706.23038-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/6] my current testing/next queue (meson/gitlab/fedora bump) Message-Id: <20210217121932.19986-4-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [8/8] ======================= [PATCH] linux-user/elfload: munmap proper address in pgd_find_hole_fallback Message-Id: <20210131061849.12615-1-vfazio(a)xes-inc.com> [PATCH] linux-user/elfload: do not assume MAP_FIXED_NOREPLACE kernel support Message-Id: <20210131061930.14554-1-vfazio(a)xes-inc.com> [RFC v18 00/15] i386 cleanup PART 2 Message-Id: <20210212123622.15834-1-cfontana(a)suse.de> [PATCH v2] target/mips: fetch code with translator_ld Message-Id: <20210125105818.2707067-1-f4bug(a)amsat.org> [PATCH] travis.yml: Limit simultaneous jobs to 3 Message-Id: <20210217102531.1441557-1-thuth(a)redhat.com> [PATCH] gitlab-ci: Display Avocado log content when tests timeout Message-Id: <20210215171438.935665-1-philmd(a)redhat.com> [PATCH] gitlab-ci.yml: Run check-tcg with TCI Message-Id: <20210127055903.40148-1-thuth(a)redhat.com> [PATCH] docker: Bump Fedora images to release 33 Message-Id: <20210118181255.314672-1-philmd(a)redhat.com> Absences ======== - Lockdown 3: No schooling, just half term distractions! Current Review Queue ==================== * [PATCH v20 00/17] i386 cleanup PART 2 Message-Id: <20210218172156.25520-1-cfontana(a)suse.de> Added: <2021-02-19 Fri> * [RFC PATCH 0/5] target/arm: Add MTE support to KVM guest Message-Id: <cover.1612747873.git.haibo.xu(a)linaro.org> Added: <2021-02-16 Tue> * [PATCH v2 00/15] tcg/arm: host neon support Message-Id: <20210208024625.271018-1-richard.henderson(a)linaro.org> Added: <2021-02-08 Mon> -- Alex Bennée

4 years, 4 months

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[ACTIVITY] report week ending 19 Feb

by Peter Maydell

Progress: * QEMU-364 [QEMU support for ARMv8.1-M extensions] + sent out v2 of the MPS3-AN524 series (minor changes only) + discovered that I need to implement the SSE-300's System Counter + implemented the system counter, did some final testing and reviewing, and sent out v1 of the MPS3-AN547 series to the list + once these patches are reviewed and in master the QEMU-413 epic will be complete -- PMM

4 years, 4 months

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Many of your builders are red for long time

by Galina Kistanova

Hello Linaro Toolchain Working Group, libcxx-libcxxabi-libunwind-armv8-linux has been red for 5 days. clang-cmake-aarch64-global-isel has been red for 10 days. clang-cmake-aarch64-quick has been red for 10 days. clang-cmake-armv7-global-isel has been red for 10 days. clang-cmake-armv7-lnt has been red for 10 days. clang-cmake-aarch64-lld has been red for 11 days. clang-cmake-armv8-lld has been red for 11 days. clang-cmake-thumbv7-full-sh has been red for 11 days. clang-cmake-armv7-full has been red for 11 days. Is anybody looking at this? I also noticed that some of your workers are less reliable than others. For example, inaro-tk1-09 worker was last time producing a green build 2 months ago - http://lab.llvm.org:8011/#/workers/2?numbuilds=500 I'm removing the linaro-tk1-09 worker from the production buildbot for now. Please feel free to connect it to the staging and make the builder reliably green. Then it could be returned back to the production. linaro-armv8-windows-msvc-01 and linaro-armv8-windows-msvc-02 have been red for the least 4 months. I'm removing them from the production buildbot. You can return them back to production after they are reliably green in the staging. Please feel free to ask if you have questions. Thanks Galina

4 years, 4 months

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[ACTIVITY] 8-12 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - a few regressions to bisect. Fixed a minor testcase issue - native validation in Linaro's lab: we still see a few random results * GCC - MVE autovectorization: Working on vcmp. * Misc - fixes in stm32 benchmarking harness == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking Holidays next week, back Monday 22nd Feb

4 years, 4 months

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[ACTIVITY] report week ending 12 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + sent out a small code-cleanup patchset for some arm display device models to remove no-longer-needed support for non-32bpp outputs + tracked down (with the aid of Paolo) why our build system had started building the documentation every time you run 'make'; sent a fix + code review todo queue status: 12 items, but the oldest was only sent to the list on Monday... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + An MPS3 Cortex-M55 FPGA image is now publicly available: the AN547. We'll provide a model of this in QEMU. Started working on the patchseries to implement it (relatively small changes on top of the SSE-300 work I've already done but not sent out, and the mps3-an524 series I sent out for review last week). This is basically code-complete but I need to do some more testing and ideally I'd like the AN524 series to get reviewed before I send out another 40-patch series that would have to be based on top of that one. thanks -- PMM

4 years, 4 months

1
0
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Re: [lldb-dev] 12.0.0-rc1 Release has been tagged

by Diana Picus

Hello, I've uploaded binaries for Windows on Arm: 081373cc76e88224020fea42eba2161d972f03bb83ebc055fb3cd4f2cfcdfb95 LLVM-12.0.0-rc1-woa64.exe It was built from the current release/12.x branch (commit b46924ee) with two patches applied on top: - https://reviews.llvm.org/D96259 - https://reviews.llvm.org/D96498 It contains "clang;clang-tools-extra;lld;compiler-rt” projects. Compiler-RT has sanitizers disabled (MEMPROF and XRAY use sanitizer infrastucture). I.e., === + -DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;lld;compiler-rt" ^ + -DCOMPILER_RT_BUILD_SANITIZERS=OFF ^ + -DCOMPILER_RT_BUILD_MEMPROF=OFF ^ + -DCOMPILER_RT_BUILD_XRAY=OFF ^ === I've attached the changes we had to make to llvm/utils/releases/build_llvm_package.bat. @Maxim Kuvyrkov is going to clean them up and post a patch in the next couple of weeks (he's been doing all the hard work, I'm just uploading). This is the first time we're trying to provide a release for Windows on Arm, so if anyone has any comments or questions, feel free to send an email :) Cheers, Diana On Thu, 28 Jan 2021 at 05:05, Tom Stellard via lldb-dev < lldb-dev(a)lists.llvm.org> wrote: > Hi, > > I've tagged the 12.0.0-rc1 release. Testers can begin testing and upload > binaries. > > -Tom > > _______________________________________________ > lldb-dev mailing list > lldb-dev(a)lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-dev >

4 years, 4 months

1
0
0 0

[ACTIVITY] week ending Feb. 7 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - TSC Stratos next cycle presentation - [Stratos Sync - this week discussing Rust] - Followed up on Rust presentation and sketched out some areas of interest [STR-9] <https://projects.linaro.org/browse/STR-9> [Stratos Sync - this week discussing Rust] <https://collaborate.linaro.org/display/STR/2021-02-04+Project+Stratos+Sync+…> QEMU Support for Xen ([STR-20]) =============================== - latest iteration of [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> - while re-basing [my Xen loader and fixes tree] - realised that [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Message-Id: <20200929224355.1224017-1-philmd(a)redhat.com> would be useful - which awaits [PATCH v14 00/22] i386 cleanup PART 2 Message-Id: <20210128092814.8676-1-cfontana(a)suse.de> being merged - bunch of related review of pre-cursor stuff [STR-20] <https://projects.linaro.org/browse/STR-20> [my Xen loader and fixes tree] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Upstream Work ([UM-2]) =========================== - caught up on a bunch of review - got about halfway through rth's mega TCI series - posted [PATCH v1 00/15] testing/gdbstub/docs pre-PR Message-Id: <20210202134001.25738-1-alex.bennee(a)linaro.org> - will roll PR on Monday - some discussion on Detecting Faulting Instructions From Plugins Message-Id: <YBTRSK4/F5KLH+FZ(a)strawberry.localdomain> - looks like we need special handling for instrumentation on recompiled IO ops [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [5/5] ======================= [PATCH 00/10] target: Provide target-specific Kconfig Message-Id: <20210131111316.232778-1-f4bug(a)amsat.org> [PATCH v3 0/5] Fix some style problems in contrib Message-Id: <20210118031004.1662363-1-zhouyang789(a)huawei.com> [PATCH v15 00/23] i386 cleanup PART 2 Message-Id: <20210201100903.17309-1-cfontana(a)suse.de> [PATCH 00/22] Acceptance Test: introduce base class for Linux based tests Message-Id: <20210203172357.1422425-9-crosa(a)redhat.com> [PATCH v2 0/5] Move remaining x86 Travis jobs to the gitlab-CI Message-Id: <20210205091857.845389-1-thuth(a)redhat.com> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v6 00/11] Support disabling TCG on ARM (part 2) Message-Id: <20210131115022.242570-1-f4bug(a)amsat.org> Added: <2021-01-31 Sun> * [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-29 Fri> * [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Message-Id: <20210124025306.3949-1-leif(a)nuviainc.com> Added: <2021-01-25 Mon> -- Alex Bennée

4 years, 4 months

1
0
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[ACTIVITY] 1-5 February 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - not really catching up, now ~15 days late due to the numerous commits. Manually fast-forwarded the latest build to today. I'll bisect manually for regressions if needed. - re-enabled native validation in Linaro's lab: we are sending test results again * GCC - MVE autovectorization: vorn patch committed. Working on vcmp. == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 4 months

1
0
0 0

[ACTIVITY] report week ending 5 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + lots of code review this week, including another round of rth's MTE user-mode patchset * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Sent out an RFC proposing some more Clock API changes (since it'll be a while before I'm ready to post the series with the new timer device that requires them) + The SSE-200 Cortex-M33-based MPS3 AN524 FPGA image is a useful target to model: the Zephyr folks would like it, and it is a good stepping stone to an MPS3 FPGA image with a Cortex-M55/SSE-300 in it. Wrote a patchset for an mps3-an524 board model, and sent it out for review. -- PMM

4 years, 4 months

1
0
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an Ubuntu test rebuild with LTO turned on

by Matthias Klose

Please see https://lists.ubuntu.com/archives/ubuntu-devel/2021-January/041341.html https://wiki.ubuntu.com/ToolChain/LTO Some builds only fail on AArch64, these are: buildlog_ubuntu-hirsute-arm64.abiword_3.0.4~dfsg-2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.adabrowse_4.0.3-12_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.adacontrol_1.21r6b-5_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.armnn_19.11.1-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.cctools_7.1.2-2ubuntu3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.csound_1:6.14.0~dfsg-6build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.dh-ada-library_6.20_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.dietlibc_0.34~cvs20160606-12_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.entropybroker_2.9-3build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.fpc_3.2.0+dfsg-8build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.grcompiler_5.2-2.1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.haskell-hopenpgp-tools_0.23.1-1build2_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ignition-common_3.5.0+dfsg1-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.lazarus_2.0.10+dfsg-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.lepton-eda_1.9.13-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.libcxx-serial_1.2.1-4_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.minetest_5.3.0+repack-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ogre-1.12_1.12.5+dfsg1-1ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.openmsx_16.0-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.parsinsert_1.04-7ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.prometheus-alertmanager_0.21.0+ds-2build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.pyqt5_5.15.2+dfsg-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.racon_1.4.13-2build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.rampler_1.1.1-3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.ruby-http-parser.rb_0.6.0-5_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.shasta_0.6.0-4build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.snd_20.9-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.sogo_4.3.2-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.swiglpk_4.65.0-2build3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.synfig_1.2.2+dfsg-3build3_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.synfigstudio_1.2.2-1build1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.tcc_0.9.27+git20200814.62c30a4a-1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.unar_1.10.1-2build9_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.valgrind_1:3.16.1-1ubuntu1_BUILDING.txt.gz arm64 buildlog_ubuntu-hirsute-arm64.vulkan-tools_1.2.154.0+dfsg1-1_BUILDING.txt.gz arm64 Note that some of those like the Ada related ones are false positives, and I didn't look at the arm64 specific issues yet. All builds were done using the GCC 10 branch. Matthias

4 years, 5 months

2
2
0 0

[ACTIVITY] week ending Jan. 31 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - some prep for next weeks TSC QEMU Device and Machine Models ([QEMU-418]) =========================================== - added a bunch of new cards for ARMv8.7 features using ARMs new feature type QEMU Support for Xen ([STR-20]) =============================== - latest iteration of [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> - while re-basing [my Xen loader and fixes tree] - realised that [PATCH v4 00/12] Support disabling TCG on ARM (part 2) Message-Id: <20200929224355.1224017-1-philmd(a)redhat.com> would be useful - which awaits [PATCH v14 00/22] i386 cleanup PART 2 Message-Id: <20210128092814.8676-1-cfontana(a)suse.de> being merged [STR-20] <https://projects.linaro.org/browse/STR-20> [my Xen loader and fixes tree] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/2] meson fixups for check-tcg/softfloat Message-Id: <20210126145356.7860-1-alex.bennee(a)linaro.org> - posted some documentation patches while helping LKFT team get up and running - [PATCH] docs/system: document an example vexpress-a15 invocation Message-Id: <20210128185300.2875-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH v4 0/4] meson: Try to clarify TCG / TCI options for new users Message-Id: <8f1f2dc6-5ad2-7d48-c2f9-9afa1e4d4065(a)weilnetz.de> [PATCH 00/23] TCI fixes and cleanups Message-Id: <20210128082331.196801-1-richard.henderson(a)linaro.org> [PATCH] accel/tcg: Add URL of clang bug to comment about our workaround Message-Id: <20210129130330.30820-1-peter.maydell(a)linaro.org> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH V6 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1611884932-1851-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-29 Fri> * [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Message-Id: <20210124025306.3949-1-leif(a)nuviainc.com> Added: <2021-01-25 Mon> * [PATCH v3 00/21] target-arm: Implement ARMv8.5-MemTag, user mode Message-Id: <20210115224645.1196742-1-richard.henderson(a)linaro.org> Added: <2021-01-18 Mon> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] 25-29 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - not really catching up, now ~10 days late due to the numerous commits * GCC - Neon intrinsics: vceqzq improvement (PR98730) commited - MVE autovectorization: vorn patch submitted - opened PR98891 about Neon vectorization regression * infra: - reviewed patches. - ABE's make-check-gcc is currently broken == Next == * MVE auto-vectorization/intrinsics improvements * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 29 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + usual upstream maintenance, code review, etc * QEMU-364 [QEMU support for ARMv8.1-M extensions] + CMSDK Clock changes now upstream + When integrating those with the SSE timer model, found what seem like some more clock API changes we could use; patches in progress Some Arm-internal training and similar admin tasks this week. thanks -- PMM

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending 24 Jan 2021

by Richard Henderson

[UM-61 TCG Maint] 3 different attempts at fixing the out-of-temps failure produced by the tcg-constant patch set. The last, longjmp to restart w/ a smaller tb, seems unlikely to have unanticipated side effects. [UM-2 QEMU Maint] Refresh two patches toward cortex-a76. Misc patch review. Partial fix for target/ppc mis-use of tb->flags. r~

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending Jan. 24 2021

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - posted Project Stratos planning priorities for the next development cycle (-> Oct2021) Message-Id: <87im7rtpyq.fsf(a)linaro.org> - baring feedback from members during voting I think this is what we are doing - attended [AGL discussion] on zero-copy for virtio-gpu with Peter Griffin - more meetings on other collaboration opportunities, drew more slide ware - bootstrapped my RB5 rig, just need to figure out how to update the kernel [STR-9] <https://projects.linaro.org/browse/STR-9> [AGL discussion] <https://confluence.automotivelinux.org/display/VE/Meeting+Agenda?src=contex…> QEMU Device and Machine Models ([QEMU-418]) =========================================== - flurry of syncing and card creation, solidified [QEMU-414] [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> [QEMU-414] <https://projects.linaro.org/browse/QEMU-414> QEMU Support for Xen ([STR-20]) =============================== - continued looking at [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> [STR-20] <https://projects.linaro.org/browse/STR-20> QEMU Upstream Work ([UM-2]) =========================== - respun [PULL v2 00/30] testing, gdbstub and semihosting Message-Id: <20210118111745.20104-1-alex.bennee(a)linaro.org> to fix NetBSD issue - posted [PATCH v1 0/6] testing/next (docker binfmt tests) Message-Id: <20210119175208.763-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/8] testing/next (docker, binfmt, gdb version) Message-Id: <20210122181854.23105-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [4/4] ======================= [PATCH] util/log: flush TB cache when log level changes Message-Id: <161130982491.1038646.15688151175539344664.stgit@pasha-ThinkPad-X280> [PATCH v3] hw/core/qdev-properties-system: Rewrite set_pci_host_devaddr using GLib Message-Id: <20201125083300.861206-1-philmd(a)redhat.com> [RFC PATCH] tests/docker: Allow passing --network option when building images Message-Id: <20210119054502.531451-1-f4bug(a)amsat.org> [PATCH] tcg: Increase the static number of temporaries Message-Id: <20210121025439.1120405-1-richard.henderson(a)linaro.org> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v3 00/21] target-arm: Implement ARMv8.5-MemTag, user mode Message-Id: <20210115224645.1196742-1-richard.henderson(a)linaro.org> Added: <2021-01-18 Mon> * [PATCH 0/6] accel: Restrict TCG-specific code Message-Id: <20210117164813.4101761-1-f4bug(a)amsat.org> Added: <2021-01-18 Mon> * [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-13 Wed> * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] 18-22 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - catching up, still ~1 week late due to the numerous commits * GCC - Neon intrinsics: looking at vceqzq improvement (PR98730) - MVE autovectorization: WIP on vorn and vcmp. - helping with cortex-m0 libgcc patch validation. Opened PR98779 about issues in libgcc wrt -mpure-code. * infra: - reviewed patches. - ABE's make-check-gcc is currently broken == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 22 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Code review (including RTH's MTE-for-user-mode-emulation) + Investigating an intermittent failure of a test case involving an s390 guest on aarch64 hosts... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Converted the ARMSSE (IoTKit/SSE-200) code over to use the Clock framework, which was added to QEMU after ARMSSE was first written. (This is a prereq for adding the new-in-SSE-300 timer device, which will use Clocks.) Sent the patches out for review. I'm currently experimenting with a schedule of: Mon: JIRA task work; Tue: code review; Thu: JIRA task work; Fri: misc upstream thanks -- PMM

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending 17 Jan 2021

by Richard Henderson

[UM-61 TCG Maint] Refresh tcg backend constraints. Pull request for tcg constants. -- which caused reported failures. [UM-2 QEMU Maint] Refresh sve pred_desc fixes. Refresh arm alignment fixes. Misc review. [QEMU-344 ARMv8.5-MemTag] Refresh mte user-only patch set. r~

4 years, 5 months

1
0
0 0

Re: Compilation issue with Linaro ARM toolchain

by Mathieu Poirier

Adding the Linaro toolchain group mailing list. On Mon, Jan 18, 2021 at 05:49:39PM +0300, Sergey Suloev wrote: > Hi, guys, > > I am having an issue builduing kernel 5.11 (rc4) with Linaro ARM toolchain. > The issue seems to be related to CC plugins sources. > Here is my build log: https://pastebin.com/DTn7Szax. I have never seen this > before with versions 5.10 and below. > > Thank you, > Sergey > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel(a)lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

4 years, 5 months

3
2
0 0

[ACTIVITY] 11-15 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - catching up, still ~1 week late due to the numerous commits * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: committed - MVE autovectorization: movmisalign, vshl and vshr: committed. WIP on next operators. - opened 2 PRs about missed optims related to these recent patches - helping with cortex-m0 libgcc patch validation * infra: - reviewed ABE patches. - fixed abe-tests == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending Jan. 17 2021

by Alex Bennée

QEMU Device and Machine Models ([QEMU-418]) =========================================== - flurry of syncing and card creation, solidified [QEMU-414] [QEMU-414] <https://projects.linaro.org/browse/QEMU-414> VirtIO Initiative ([STR-9]) =========================== - discussion about next cycle, call on Monday [STR-9] <https://projects.linaro.org/browse/STR-9> QEMU Support for Xen ([STR-20]) =============================== - started looking at [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> [STR-20] <https://projects.linaro.org/browse/STR-20> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/9] testing/next (tags!, more travis/shippable deprecation) Message-Id: <20210113151408.27939-1-alex.bennee(a)linaro.org> - posted [PATCH v2 00/12] testing/next (tags!, shippable/travis deprecation, regression fixes, checkpatch) Message-Id: <20210114165730.31607-1-alex.bennee(a)linaro.org> - posted [PULL 00/30] testing, gdbstub and semihosting Message-Id: <20210115130828.23968-1-alex.bennee(a)linaro.org> - looks like a NetBSD regression needs to be looked at [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [1/1] ======================= Re: [PATCH v6 34/35] Auto-import Docker support files Message-Id: <1610080146-14968-1-git-send-email-tsimpson(a)quicinc.com> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH V4 00/24] IOREQ feature (+ virtio-mmio) on Arm Message-Id: <1610488352-18494-1-git-send-email-olekstysh(a)gmail.com> Added: <2021-01-13 Wed> * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 15 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + code review, pullreq + fixed the "breaks a gitlab CI run" issue with the 'merge docs into a single sphinx manual' patch * QEMU-364 [QEMU support for ARMv8.1-M extensions] + Progress with the SSE-300 model: - finished model of new timer device - updated iotkit-sysctl register block with SSE-300 specific behaviour - implemented simple dummy model of new CPU<N>_PWRCTRL register block - made sse-300 code more data-driven so it can handle sse-300 putting some of the devices at different places thanks -- PMM

4 years, 5 months

1
0
0 0

[ACTIVITY] week ending Jan. 10 2021

by Alex Bennée

QEMU Device and Machine Models ([QEMU-418]) =========================================== - pinged tsc/tle about scheduling a call for next week [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> QEMU Upstream Work ([UM-2]) =========================== - flushed gdbstub and semihosting queues - sent pre-PR series to list [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [2/2] ======================= [PATCH V1] gdbstub: suspended state support Message-Id: <1609963815-417989-1-git-send-email-steven.sistare(a)oracle.com> [PATCH] gdbstub.c uses incorrect check for active gdb in use_gdb_syscalls Message-Id: <20201223212752.1145294-1-keithp(a)keithp.com> Absences ======== - Lockdown 3: Home schooling returns! Current Review Queue ==================== * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v6 0/5] Enable plugin support on msys2/mingw Message-Id: <20201013002806.1447-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> -- Alex Bennée

4 years, 5 months

1
0
0 0

[ACTIVITY] 4-8 January 2021

by Christophe Lyon

== Progress == * GCC upstream validation: - restarted validation after e/o year maintenance - catching up, no regression to report so far * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: movmisalign accepted, waiting for boostrap results vshl and vshr: pinged. - helping with cortex-m0 libgcc patch validation * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - reviewed ABE patches == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 5 months

1
0
0 0

[ACTIVITY] report week ending 8 Jan

by Peter Maydell

Progress (2 day week this week): * UM-2 [QEMU upstream maintainership] + Unsurprisingly, pretty much just catching up with email, pull requests, code review, bug reports, respins of patchsets... * QEMU-364 [QEMU support for ARMv8.1-M extensions] + The final parts of base v8.1M and Cortex-M55 support are now in master. thanks -- PMM

4 years, 5 months

1
0
0 0

[ACTIVITY] 2 weeks ending 27 Dec 2020

by Richard Henderson

(or the 10 days preceding Christmas) [UM-61 TCG Maint] New version of tcg constants patch set. TCG backend constraints cleanup. ARM NEON host patch set. [UM-2 QEMU Maint] Fixed tcg gvec bug vs hosts without vector support. Rebase and re-send pauth impdef algorithm. Patch review: mips, riscv. gdbstub. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending Dec. 20 2020

by Alex Bennée

VirtIO RPMB ([STR-5]) ===================== - Continued working on Rust port of vhost-user-rpmb - Re-based and updated the [QEMU based branch] [QEMU based branch] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-rpmb-v2> QEMU Support for Xen ([STR-20]) =============================== - re-based and continued to work on Xen development environment - with my [current branch] I can now boot domU inside dom0 - also can now run qemu-aarch64 as a Dom0 PV backend [branch to clean-up and add "virt" machine] <https://github.com/stsquad/qemu/tree/xen/add-xen-virt-machine> [current branch] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Device and Machine Models ([QEMU-418]) =========================================== - created new initiative for tracking work both in and outside group - we don't want another watchdog duplication - worked on refining definition for [CPU model for QEMU] - wrote to Linaro open discussion list to canvas members requirements Message-Id: <878saesi0x.fsf(a)linaro.org> [QEMU-418] <https://projects.linaro.org/browse/QEMU-418> [CPU model for QEMU] <https://projects.linaro.org/browse/QEMU-414> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] configure: add --without-default-features Message-Id: <20201202153827.17446-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/8] testing/next (without-features, gitlab, python) Message-Id: <20201210190417.31673-1-alex.bennee(a)linaro.org> - posted [PATCH v1 0/6] gdbstub (auxv, tests, cleanup) Message-Id: <20201214153012.12723-6-alex.bennee(a)linaro.org> - posted [PULL 00/11] testing and configure updates Message-Id: <20201216164827.24457-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/11] testing and configure updates Message-Id: <20201217094330.17400-1-alex.bennee(a)linaro.org> - still stalled due to some stale build issues (unable to repro) - posted [PATCH v2 0/9] gdbstub/next (cleanups, softmmu, SVE) Message-Id: <20201218112707.28348-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Other work ========== - bootstrapped gitdm metadata for GCC project - planning for Stratos/QEMU Next Cycle - declared bankruptcy on my review queue, flushed most of it Completed Reviews [5/5] ======================= [PATCH v4 00/11] hvf: Implement Apple Silicon Support Message-Id: <20201203234857.21051-2-agraf(a)csgraf.de> [RFC v9 00/22] i386 cleanup Message-Id: <20201208194839.31305-1-cfontana(a)suse.de> [PATCH 0/3] hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot Message-Id: <1607937538-69471-1-git-send-email-bmeng.cn(a)gmail.com> [PATCH 0/2] Fix test-char reference counting bug Message-Id: <20201215224133.3545901-1-ehabkost(a)redhat.com> [PATCH 0/8] Add RISC-V semihosting 0.2. Finish ARM semihosting 2.0 Message-Id: <20201125213617.2496935-1-keithp(a)keithp.com> Absences ======== - Back on Jan 5th, Happy Christmas Current Review Queue ==================== * [PATCH v5 00/23] tcg: Better handling of constants Message-Id: <20201217145215.534637-1-richard.henderson(a)linaro.org> Added: <2020-12-17 Thu> * [PATCHv3 00/17] ARMv8.4 Secure EL2 Message-Id: <3333301.iIbC2pHGDl(a)basile.remlab.net> Added: <2020-12-08 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v6 0/5] Enable plugin support on msys2/mingw Message-Id: <20201013002806.1447-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> -- Alex Bennée

4 years, 6 months

1
0
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[ACTIVITY] 14-18 December 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures, trunk build broken several times * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: committed veor, vbic, vmvn and vneg. Sent movmisalign, vshl and vshr patches. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - reviewed ABE patches == Next == Holidays until Jan 4th, 2021 == Future == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 6 months

1
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[ACTIVITY] 7 - 11 Dec 2020

by Prathamesh Kulkarni

== This Week == * PR97872 (missed optimization for comparison on vectors) - Committed fix to trunk * PR97903 (Lower a & b != 0 to vtst) - In progress * PR66791 (Replace builtins by vector extensions in arm_neon.h intrinsics) - Committed patches for vmvn - Patches approved for vcreate, vneg, vclt, vcgt. == Next Week == - PR97903 - PR66791: Commit approved patches and work on new intrinsics

4 years, 6 months

1
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perf issue: etm traces are dumped to the wrong AUX buffer

by Zied Guermazi

hi I am using perf syscall to collect etm traces for btraces implementation in GDB running on Linux kernel 5.9.1 on a cortex A7. in this test case, I am debugging a multi-threaded process (2 pthreads). For each thread, GDB is calling the sys call perf_event_open and gives the corresponding thread ptid.lwp as argument. for each syscall, the AUX buffer is mmap(ped) to a dedicated memory. this is working for almost all test cases I have, except this one, where it has 50% failure rate when executed manually. 90% failure rate when executed from a script. the source code for debugged program is listed below. /* This testcase is part of GDB, the GNU debugger. Copyright 2013-2019 Free Software Foundation, Inc. Contributed by Intel Corp. <markus.t.metzger(a)intel.com> This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <pthread.h> static pthread_barrier_t barrier; static int global; static void * test(void *arg) { pthread_barrier_wait(&barrier); global= 42; /* bp.1 */ pthread_barrier_wait(&barrier); global= 42; /* bp.2 */ return arg; } int main (void) { pthread_t th; pthread_barrier_init(&barrier, NULL, 2); pthread_create(&th, NULL, test, NULL); test(NULL); pthread_join(th, NULL); pthread_barrier_destroy(&barrier); return 0; /* bp.3 */ } in this test case, a breakpoint is set at the line containing the comment /* bp.1 */ , and we start collecting traces. a second breakpoint is set at the line containing the comment /* bp.2 */, and we analyze collected traces. in a successful testcase we get both threads traces in dedicated buffers thread 1 [Switching to thread 1 (Thread 0xb6ff9ca0 (LWP 8813))] #0test (arg=0x0) at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 126 instructions in 15 functions (0 gaps) for thread 1 (Thread 0xb6ff9ca0 (LWP 8813)). (gdb) record function-call-history /ilc 1 test inst 1,9 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 2 pthread_barrier_wait@plt inst 10,12 at 3 pthread_barrier_wait inst 13,32 at 4 __aeabi_uidivmod inst 33,36 at 5 __udivsi3 inst 37,39 at 6 __udivsi3 inst 40,48 at 7 __aeabi_uidivmod inst 49,52 at 8 pthread_barrier_wait inst 53,77 at 9 __libc_do_syscall inst 78,80 at 10 pthread_barrier_wait inst 81,102 at 11 __aeabi_uidivmod inst 103,106 at 12 __udivsi3 inst 107,109 at 13 __udivsi3 inst 110,118 at 14 __aeabi_uidivmod inst 119,122 at 15 pthread_barrier_wait inst 123,126 at here is a log of the collected trace generic elements cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION thread 2 [Switching to thread 2 (Thread 0xb6ea7460 (LWP 8816))] #0test (arg=0x0) at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 150 instructions in 20 functions (0 gaps) for thread 2 (Thread 0xb6ea7460 (LWP 8816)). (gdb) record function-call-history /ilc 1 test inst 1,9 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 2 pthread_barrier_wait@plt inst 10,12 at 3 pthread_barrier_wait inst 13,32 at 4 __aeabi_uidivmod inst 33,36 at 5 __udivsi3 inst 37,39 at 6 __udivsi3 inst 40,48 at 7 __aeabi_uidivmod inst 49,52 at 8 pthread_barrier_wait inst 53,66 at 9 __aeabi_uidivmod inst 67,70 at 10 __udivsi3 inst 71,73 at 11 __udivsi3 inst 74,82 at 12 __aeabi_uidivmod inst 83,86 at 13 pthread_barrier_wait inst 87,103 at 14 __libc_do_syscall inst 104,106 at 15 pthread_barrier_wait inst 107,126 at 16 __aeabi_uidivmod inst 127,130 at 17 __udivsi3 inst 131,133 at 18 __udivsi3 inst 134,142 at 19 __aeabi_uidivmod inst 143,146 at 20 pthread_barrier_wait inst 147,150 at here is a log of the collected trace generic elements cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION in the failing test we got all traces in one buffer, the second one is empty (gdb) thread 1 [Switching to thread 1 (Thread 0xb6ff9ca0 (LWP 8826))] #0 test (arg=0x0) at /home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 276 instructions in 36 functions (0 gaps) for thread 1 (Thread 0xb6ff9ca0 (LWP 8826)). (gdb) record function-call-history /ilc 1 1 test inst 1,9 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 2 pthread_barrier_wait@plt inst 10,12 at 3 pthread_barrier_wait inst 13,32 at 4 __aeabi_uidivmod inst 33,36 at 5 __udivsi3 inst 37,39 at 6 __udivsi3 inst 40,48 at 7 __aeabi_uidivmod inst 49,52 at 8 pthread_barrier_wait inst 53,77 at 9 __libc_do_syscall inst 78,80 at 10 test inst 81,88 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:30,32 11 pthread_barrier_wait@plt inst 89,91 at 12 pthread_barrier_wait inst 92,111 at 13 __aeabi_uidivmod inst 112,115 at 14 __udivsi3 inst 116,118 at 15 __udivsi3 inst 119,127 at 16 __aeabi_uidivmod inst 128,131 at 17 pthread_barrier_wait inst 132,145 at 18 __aeabi_uidivmod inst 146,149 at 19 __udivsi3 inst 150,152 at 20 __udivsi3 inst 153,161 at 21 __aeabi_uidivmod inst 162,165 at 22 pthread_barrier_wait inst 166,182 at 23 __libc_do_syscall inst 183,185 at 24 pthread_barrier_wait inst 186,205 at 25 __aeabi_uidivmod inst 206,209 at 26 __udivsi3 inst 210,212 at 27 __udivsi3 inst 213,221 at 28 __aeabi_uidivmod inst 222,225 at 29 pthread_barrier_wait inst 226,229 at 30 test inst 230,230 at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 31 pthread_barrier_wait inst 231,252 at 32 __aeabi_uidivmod inst 253,256 at 33 __udivsi3 inst 257,259 at 34 __udivsi3 inst 260,268 at 35 __aeabi_uidivmod inst 269,272 at 36 pthread_barrier_wait inst 273,276 at here is a log of the collected trace generic elements cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_NO_SYNC cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE --->cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION (gdb) thread 2 [Switching to thread 2 (Thread 0xb6ea7460 (LWP 8827))] #0test (arg=0x0) at/home/ubuntu/development/gdb/build/gdb/testsuite/../../../binutils-gdb/gdb/testsuite/gdb.btrace/multi-thread-step.c:34 34 global = 42; /* bp.2 */ (gdb) info record Active record target: record-btrace Recording format: arm Processor CoreSight ETM Trace. Buffer size: 8kB. Recorded 0 instructions in 0 functions (0 gaps) for thread 2 (Thread 0xb6ea7460 (LWP 8827)). (gdb) record function-call-history /ilc 1 No trace. (gdb) is there any known issues for calling perf_event_open twice for two different threads? is there any known issues for flushing traces when a switch between two threads takes place? is there any known issue for tracing threads when switching happens due to a pthread_barrier_wait? do you have any other hint to provide here? Kind regards Zied Guermazi

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending 13 Dec 2020

by Richard Henderson

[UM-2] New revision on arm alignment patch set. Patch review: mips and i386 cleanups. [UM-61] New revision on splitwx patch set. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 11 Dec

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + sent out a pullreq for 6.0, and did a bunch more patch review + sent out a respin of the "build one manual, not five" RFC I sent last month; nobody objected to the RFC so this time around it is a proper PATCH + had a brief scan through the GIC architecture specification to look at what extra GICv4 and GICv4.1 add (the big thing is that the ITS is now mandatory; QEMU doesn't emulate that yet) * VIRT-364 [QEMU support for ARMv8.1-M extensions] + SSE-300 timer device model more or less functionally-complete (though untested). I ran into some issues with QEMU's Clock APIs that I needed to fix in the process -- sent a patchseries trying to address those. + Got most of the outstanding v8.1M patches into master; sent a small patch series with respins of the last 4 or so patches that needed more work thanks -- PMM

4 years, 6 months

1
0
0 0

[ACTIVITY] 7-11 December 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: committed vand and vorr patches. Sent updated versions of veor, vbic and vmvn. vshr and vshl need some refactorization with Neon versions, clarified the best way to go with Arm maintainers. - PR97875 (suboptimal vectorization on MVE): investigation shows that movmisalign patterns are missing for MVE. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - debugging issues with our docker containers - looking at ABE patches * misc: - provided feedback to Arm's partner wrt Intrinsics documentation == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE auto-vectorization/intrinsics improvements

4 years, 6 months

1
0
0 0

[ACTIVITY] week ending 6 Dec 2020

by Richard Henderson

[UM-59] More work on softfloat rem; f128 still needs work. [UM-2] Patch review, notably v8.1m, mips cleanups, arc port. Revisions to arm alignment patch set. r~

4 years, 6 months

1
0
0 0

[ACTIVITY] 30 November-4 December 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: handling feedback on(vand, vorr, veor, vshr, vshl). WIP vmvn, vbic. Found further vectorization issues. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers - looking at ABE patches == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 6 months

1
0
0 0

[ACTIVITY] 30 Nov - 4 Dec 2020

by Prathamesh Kulkarni

== This Week == * PR97872 (missed optimization on less-than vector comparison) - Upstream discussion with Richard, patch close to being approved. - Causes a regression for pr78102.c. * PR66791 (replace builtins by vector extensions in arm_neon.h intrinsics) - Submitted patches for vmvn, vcreate, vneg. - Kyrill approved patch for vmvn, and asked to remove corresponding builtins from being created in backend. == Next Week == - Hopefully commit fix for PR97872 - Continue with PR66791 - Start looking at another vectorization PR

4 years, 6 months

1
0
0 0

Timeout tests timing out

by David Blaikie

The clang-cmake-armv8-lld (linaro-toolchain owners) buildbot is timing out trying to run some timeout tests (Dan Liew author): Pass: http://lab.llvm.org:8011/builders/clang-cmake-armv8-lld/builds/5672 Fail: http://lab.llvm.org:8011/builders/clang-cmake-armv8-lld/builds/5673 Is there anything we can do to the buildbot? Or the tests? (bump up the time limits or maybe remove the tests as unreliable?)

4 years, 6 months

5
14
0 0

[ACTIVITY] week ending Dec. 6 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - started reviewing latest EPAM IOREQ/VirtIO patches Message-Id: <1606732298-22107-1-git-send-email-olekstysh(a)gmail.com> VirtIO RPMB ([STR-5]) ===================== - Continued working on Rust port of vhost-user-rpmb VirtIO Portability Demo ([STR-13]) ================================== - done and closed QEMU Support for Xen ([STR-20]) =============================== - re-based and continued to work on Xen development environment - with my [current branch] I can now boot domU inside dom0 - also can now run qemu-aarch64 as a Dom0 PV backend [current branch] <https://github.com/stsquad/qemu/tree/xen/guest-loader-and-arm-build-cleanup…> QEMU Device and Machine Models ([QEMU-418]) =========================================== - created new initiative for tracking work both in and outside group - we don't want another watchdog duplication - worked on refining definition for [CPU model for QEMU] - wrote to Linaro open discussion list to canvas members requirements Message-Id: <878saesi0x.fsf(a)linaro.org> [CPU model for QEMU] <https://projects.linaro.org/browse/QEMU-414> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] configure: add --without-default-features Message-Id: <20201202153827.17446-1-alex.bennee(a)linaro.org> Other work ========== - bootstrapped gitdm metadata for GCC project Completed Reviews [1/1] ======================= [PATCH v4 00/11] hvf: Implement Apple Silicon Support Message-Id: <20201203234857.21051-2-agraf(a)csgraf.de> -- Alex Bennée

4 years, 6 months

1
0
0 0

[ACTIVITY] report week ending 3 Dec

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Cut down the patch review queue a bit ready for 6.0 development cycle * VIRT-364 [QEMU support for ARMv8.1-M extensions] + started working on modelling of the SSE-300. Have done some of the easy "ID registers are different" stuff and started on modelling a new timer device that isn't in the SSE-200. thanks -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] 23 - 27 Nov 2020

by Prathamesh Kulkarni

== This Week == * PR66791 (Replace __builtins_* in arm_neon.h intrinsics by C vector extensions) - Submitted patch for vmvn, waiting for feedback. - Created and tested patches for vcreate and vneg. * PR97849 (segfault in ifcvt with -march=armv8.2-a+sve) - Committed fix to trunk. == Next Week == - PR97872 - Continue with PR66791

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending Nov. 29 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Raised [STR-21] to cover some Zephyr work - Synced with EPAM and ARM to discuss their work and direction [STR-21] <https://projects.linaro.org/browse/STR-21> VirtIO RPMB ([STR-5]) ===================== - Started investigating Rust port of vhost-user-rpmb [STR-5] <https://projects.linaro.org/browse/STR-5> VirtIO Portability Demo ([STR-13]) ================================== - delivered gold copy for talk at [OSS and ALS Japan 2020] - synced with ALS guys on talk [OSS and ALS Japan 2020] <https://sched.co/f2Yk> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 for 5.1 00/10] various fixes (CI, Xen, plugins) Message-Id: <20201110192316.26397-1-alex.bennee(a)linaro.org> - posted [[PULL for 5.2-rc3 0/7] various CI cleanups (scripts, avocado, gitlab)] [UM-2] <https://projects.linaro.org/browse/UM-2> [[PULL for 5.2-rc3 0/7] various CI cleanups (scripts, avocado, gitlab)] <mu4e:i:20201123112518.13425-1-alex.bennee@linaro.org> Completed Reviews [4/4] ======================= [for-5.2 0/9] docs: Move orphan top-level .rst files into manuals Message-Id: <20201112144041.32278-1-peter.maydell(a)linaro.org> [PATCH v3 00/41] Mirror map JIT memory for TCG Message-Id: <20201106032921.600200-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2020-11-14 Sat 11:52] Had a brief look over, waiting for next revision Added: <2020-11-06 Fri> [PATCH v2 00/13] Remove GCC < 4.8 checks Message-Id: <20201126112915.525285-1-marcandre.lureau(a)redhat.com> [PATCH] gdbstub: Correct misparsing of vCont C/S requests Message-Id: <20201121210342.10089-1-peter.maydell(a)linaro.org> Absences ======== - Illness Current Review Queue ==================== * [PATCH v2 0/4] linux/sparc: more get/set_context fixes Message-Id: <20201106152738.26026-1-peter.maydell(a)linaro.org> Added: <2020-11-06 Fri> * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] 23-27 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: sent a few patches (vand, vorr, veor, vshr, vshl). WIP vmvn, vbic * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers - looking at ABE patches == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements Reply Forward

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 27 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Cut rc3; there were a few last-minute bugfixes that came in so we will need an rc4 * VIRT-364 [QEMU support for ARMv8.1-M extensions] + read through the SSE-300 TRM and identified the required work to model it (it's similar to the SSE-200 which we already have but with various minor changes and a couple of new devices) * wisdom tooth extracted \o/ thanks -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending 22 Nov 2020

by Richard Henderson

[UM-59 # FPU Emulation Maintainership ] Lots more work converting to FloatParts. Almost all floatx80 now converted. Still to do are log2 and rem/mod for full conversion. r~

4 years, 7 months

1
0
0 0

[ACTIVITY] 16-20 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: more patterns updates (vshl, vshr). WIP * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 20 Nov

by Peter Maydell

Generally productive week rather derailed at the end by a sudden onset of toothache Thursday night :-/ Progress: * UM-2 [QEMU upstream maintainership] + usual release cycle work * VIRT-364 [QEMU support for ARMv8.1-M extensions] + Worked through the remaining set of identified new features for v8.1M implementing them. + Fixed a handful of pre-existing bugs along the way. + Sent out a patchset with all this plus the "Implement (no-MVE) Cortex-M55 model" patch on top, since we now have all the pieces needed for it. + The next and final piece of work here is to implement a model of a board that uses the Cortex-M55. -- PMM

4 years, 7 months

1
0
0 0

[ACTIVITY] week ending Nov. 15 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO Portability Demo ([STR-13]) ================================== - recorded AGL demo videos (KVM, TCG Xen Dom0 with and without Xen aware kernel) - recorded [preview version of talk] [STR-13] <https://projects.linaro.org/browse/STR-13> [preview version of talk] <https://fileserver.linaro.org/s/wgt2AAj9rxYqJop> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 for 5.1 00/10] various fixes (CI, Xen, plugins) Message-Id: <20201110192316.26397-1-alex.bennee(a)linaro.org> [UM-2] <https://projects.linaro.org/browse/UM-2> Completed Reviews [2/2] ======================= [for-5.2 0/9] docs: Move orphan top-level .rst files into manuals Message-Id: <20201112144041.32278-1-peter.maydell(a)linaro.org> [PATCH v3 00/41] Mirror map JIT memory for TCG Message-Id: <20201106032921.600200-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2020-11-14 Sat 11:52] Had a brief look over, waiting for next revision Added: <2020-11-06 Fri> Current Review Queue ==================== * [PATCH v2 0/4] linux/sparc: more get/set_context fixes Message-Id: <20201106152738.26026-1-peter.maydell(a)linaro.org> Added: <2020-11-06 Fri> * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> -- Alex Bennée

4 years, 7 months

1
0
0 0

[ACTIVITY] 9-13 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback - MVE autovectorization: started patterns updates (vand, vorr, veor) * Misc - investigated LP bug 1747966 (https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966) there is a fix in binutils upstream: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0e6a3f07f50723d18… * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 7 months

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[ACTIVITY] report week ending 13 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + investigated and fixed a bug that had been lurking unfixed in our n800 models for years which prevented guest boot of Maemo images + docs tidyup: moved "orphan" rST documents into the manual structure so they actually get shipped to users + usual release candidate related work * VIRT-364 [QEMU support for ARMv8.1-M extensions] + working on handling for new FP system registers; the FPCXT regs in particular have some tricky corners... thanks -- PMM

4 years, 7 months

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[ACTIVITY] week ending 8 Nov 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] * Fix neon register offsets big-endian hosts. * Fix neon register offsets for VTBL. * Working through a 4th revision of float128_muladd. * Random patch review and bug fixes. [UM-61 # TCG Core Maintainership ] * Two revisions of split w^x patch set. r~

4 years, 7 months

1
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Demo of using etm traces on arm for instructions and functions recording and reverse debugging

by Zied Guermazi

hi all, to demonstrate extending gdb to use etm traces for implementing btrace on arm processors, I have made this video available on youtube https://youtu.be/ptKbJRNUqUI users can then have access to process record and replay, on instructions and functions level (https://sourceware.org/gdb/current/onlinedocs/gdb/Process-Record-and-Replay…) and reverse debugging(https://www.gnu.org/software/gdb/news/reversible.html) we have all functionalities available for intel PT except tracing multi-threaded applications. In this demo I have "reconstructed" the cspr register to enable setting breakpoints in reverse debugging. it is still dirty (adds arm specific register to an architecture agnostic structure) but it shows that it works when implemented properly Kind Regards Zied Guermazi

4 years, 7 months

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[ACTIVITY] 2-6 November 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - PR96767: patch committed - PR96770: patch committed - patch for C++ thunks with -mpure-code and cortex-m0: patches committed - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: handling feedback * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 7 months

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[ACTIVITY] week ending Nov. 8 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Raised two more Xen related cards, [STR-19] and [STR-20] [STR-19] <https://projects.linaro.org/browse/STR-19> [STR-20] <https://projects.linaro.org/browse/STR-20> VirtIO Portability Demo ([STR-13]) ================================== - syned on current status of demo and discussed options - attempted to record the KVM demo, killed my MachiatoBin with load - another go on Monday [STR-13] <https://projects.linaro.org/browse/STR-13> QEMU Support for Xen ([STR-20]) =============================== - posted [RFC PATCH 00/15] Xen guest-loader and arm64 build fixes/enhancements Message-Id: <20201105175153.30489-1-alex.bennee(a)linaro.org> [STR-20] <https://projects.linaro.org/browse/STR-20> Upstream Work ([QEMU-109]) ========================== - finally got round to looking at rth's [128 bit softfloat proposal] - posted [PATCH v2] docs: add some notes on the sbsa-ref machine Message-Id: <20201104165254.24822-1-alex.bennee(a)linaro.org> [128 bit softfloat proposal] <https://github.com/stsquad/qemu/tree/review/rth-sf128> Other ===== - TSC Review prep - Annual Review Completed Reviews [0/0] ======================= Absences ======== - Home schooling Current Review Queue ==================== * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v3 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20201014052140.1146924-1-crosa(a)redhat.com> Added: <2020-10-14 Wed> -- Alex Bennée

4 years, 7 months

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[ACTIVITY] report week ending 6 Nov

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + usual release cycle work + Our Coverity-Scan issues had been left untended a bit too long: went through them doing triage, reporting them back to patch submitters, and writing a few fixes for some of the easy ones + That took me down a rabbit-hole of fixing some issues with our sparc64 usermode emulation so I could demonstrate that the coverity fixes hadn't broken anything... thanks -- PMM

4 years, 7 months

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GDB: status of branch tracing on arm processors using coresight etm traces

by Zied Guermazi

hi all I am announcing updates in the implementation of branch tracing using coresight etm in GDB. in this update, functions and instruction history are running successfully on single threaded applications. reverse debugging is basically working with the limitation that sometimes cspr register (register 25) is required but current implementation does not provide it. the feature requires linux kernel v 4.19 or higher with manual etm sink setup. 5.9.1 or higher for automatic sink selection. GDB gdb.btrace test suite was adapted to run on arm processors. here is the summary of the gdb.btrace test results executed on an STM32MP157 (ARM cortex A7) with Linux kernel 5.9.1 === gdb Summary === # of expected passes 390 # of unexpected failures 119 # of unsupported tests 4 following tests are 100% successful: - buffer-size - enable - instruction_history - function_call_history - data - delta - cpu - gcore - record_goto-step - dlopen - vdso - segv GDB source code is available on https://github.com/gzied/binutils-gdb/tree/gdb_arm_coresight many thanks to GDB and linaro communities for their support Kind Regards Zied Guermazi

4 years, 7 months

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Re: GDB: etm traces decoding and breakpoints for arm targets

by Zied Guermazi

hi Thanks Mike for your support, it was very helpful. to put everything together, on arm, gdb inserts a sw breakpoint by patching the code with an undefined instruction ( see comments in arm-tdep.c line7687) when a breakpoint is hit, an exception number 9 "Undefined Instruction exception" is raised and a branch packet with this info is generated in etm traces, the trap is get handled by the kernel and it sends the appropriate signal to gdb process. when the user continues the execution, gdb patches back the code and executes the instruction. this leads to the instruction traced twice with an exception in between, the same happens for next executed instruction here is the log of decoded packets [btrace] [ftrace] update insn: fun = main, file = ./function_call_history.c, level = 0, insn = [1; 2) cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE */<= first execution attempt that raises an undefined instruction exception/* trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400534 end addr = 0x400536 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 [btrace] [ftrace] update insn: fun = main, file = ./function_call_history.c, level = 0, insn = [1; 3) cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_EXCEPTION */<= the exception is traced/* trace_chan_id: 18 exception number: 9 */<= undefined instruction exception/* cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_TRACE_ON cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_PE_CONTEXT cs_etm_decoder_trace_element_callback: elem->elem_type OCSD_GEN_TRC_ELEM_INSTR_RANGE */<= execution of the original instruction/* trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400534 end addr = 0x400536 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 as the code was changed during execution, it can not be reconstructed during traces decoding. in addition, and for tracing applications running on Linux, we are not interested in capturing raised exceptions, we can consider rolling back last instruction in ftraces. As this is not obvious, we can consider ignoring the repeated instruction as a workaround. for tracing bare metal software, we need to keep tracing exception, so we can have a flag for ignoring exceptions, and activate or dis-activate it according to the context. what do you think about it, shall I go for implementing it as described above? Kind Regards Zied Guermazi On 02.11.20 12:59, Mike Leach wrote: > Hi Zeid, > > On Sat, 31 Oct 2020 at 23:11, Zied Guermazi <zied.guermazi(a)trande.de> wrote: >> hi, >> >> while testing the implementation in gdb of branch tracing on arm >> processors using etm, I faced the the situation where a breakpoint was >> set, was hit and then the execution of the program was continued. While >> decoding generated traces, I got the address of the breakpoint >> (0x400552) executed twice, and then the following address (0x400554) >> also executed twice. the instruction at (0x400554) is a BL ( a function >> call) and the second execution corrupts the function history. >> >> here is a dump of generated trace elements >> >> >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400552 >> end addr = 0x400554 >> instructions count = 1 >> last_i_type: OCSD_INSTR_OTHER >> last_i_subtype: OCSD_S_INSTR_NONE >> last instruction was executed >> last instruction size: 2 >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400552 >> end addr = 0x400554 >> instructions count = 1 >> last_i_type: OCSD_INSTR_OTHER >> last_i_subtype: OCSD_S_INSTR_NONE >> last instruction was executed >> last instruction size: 2 >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400554 >> end addr = 0x400558 >> instructions count = 1 >> last_i_type: OCSD_INSTR_BR >> last_i_subtype: OCSD_S_INSTR_BR_LINK >> last instruction was executed >> last instruction size: 4 >> --------------------------------- >> trace_chan_id: 18 >> isa: CS_ETM_ISA_T32 >> start addr = 0x400554 >> end addr = 0x400558 >> instructions count = 1 >> last_i_type: OCSD_INSTR_BR >> last_i_subtype: OCSD_S_INSTR_BR_LINK >> last instruction was executed >> last instruction size: 4 >> >> the explanation I have for this behavior is that : >> >> -when setting the software breakpoint, the memory content of the >> instruction (at 0x400552) was altered to the instruction BKPT, >> >> -when the breakpoint was hit, the original opcode was set at (0x400552) >> and a BKPT was set to the next instruction address (0x400554), then the >> execution was continued >> >> -when the second breakpoint (0x400554) was hit, the a BKPT opcode was >> set at (0x400552) and the original opcode was set at (0x400554) then the >> execution was continued >> >> I am using the function "int target_read_code (CORE_ADDR memaddr, >> gdb_byte *myaddr, ssize_t len)" to give program memory content to the >> decoder. so the collected etm traces are correct, but, as memory was >> altered in between, the decoder is "cheated". >> >> I need to identify the re-execution of code due to breakpoint handling, >> and roll back its impact on etm decoding. >> >> is there a mean to get the actual content of program memory including >> patched addresses? >> >> is there a means of getting the history of patched addresses during the >> debugging of a program? >> >> what is the type and subtype of a BKPT instruction in a decoded trace >> elements? >> > I can only really comment on this question. The type / subtype > information in the output from the decoder is generated from the > decoder walking the memory image of the executed trace - not from the > trace packets themselves. > The decoder classifies instructions according to how they will affect > trace flow with the "other" category being set for the majority of > instructions. The categories are: other, branch, indirect branch, ISB > / DSB / DMB / WFI / WFE. > These are important in program flow trace (PTM 1.x, ETM 4.x) as these > determine which instruction we attach the E/N atoms to. BKPT will be > classified as "other", if it is seen, as it has no effect on normal > program flow. It will cause an exception which has a specific trace > packet format. > > Regards > > Mike > > >> do you have any other idea for handling this situation? >> >> >> I am attaching the source code of the program as well as the >> disassembled binary. the code was compiled as an application running on >> linux on an ARMv7 A (STM32MP157 SoC). the breakpoint was set at line 43 >> in the source code (line 238 in the disassembled code) >> >> >> Kind Regards >> >> Zied Guermazi >> >> _______________________________________________ >> CoreSight mailing list >> CoreSight(a)lists.linaro.org >> https://lists.linaro.org/mailman/listinfo/coresight > >

4 years, 8 months

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GDB: etm traces decoding and breakpoints for arm targets

by Zied Guermazi

hi, while testing the implementation in gdb of branch tracing on arm processors using etm, I faced the the situation where a breakpoint was set, was hit and then the execution of the program was continued. While decoding generated traces, I got the address of the breakpoint (0x400552) executed twice, and then the following address (0x400554) also executed twice. the instruction at (0x400554) is a BL ( a function call) and the second execution corrupts the function history. here is a dump of generated trace elements --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400552 end addr = 0x400554 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400552 end addr = 0x400554 instructions count = 1 last_i_type: OCSD_INSTR_OTHER last_i_subtype: OCSD_S_INSTR_NONE last instruction was executed last instruction size: 2 --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400554 end addr = 0x400558 instructions count = 1 last_i_type: OCSD_INSTR_BR last_i_subtype: OCSD_S_INSTR_BR_LINK last instruction was executed last instruction size: 4 --------------------------------- trace_chan_id: 18 isa: CS_ETM_ISA_T32 start addr = 0x400554 end addr = 0x400558 instructions count = 1 last_i_type: OCSD_INSTR_BR last_i_subtype: OCSD_S_INSTR_BR_LINK last instruction was executed last instruction size: 4 the explanation I have for this behavior is that : -when setting the software breakpoint, the memory content of the instruction (at 0x400552) was altered to the instruction BKPT, -when the breakpoint was hit, the original opcode was set at (0x400552) and a BKPT was set to the next instruction address (0x400554), then the execution was continued -when the second breakpoint (0x400554) was hit, the a BKPT opcode was set at (0x400552) and the original opcode was set at (0x400554) then the execution was continued I am using the function "int target_read_code (CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)" to give program memory content to the decoder. so the collected etm traces are correct, but, as memory was altered in between, the decoder is "cheated". I need to identify the re-execution of code due to breakpoint handling, and roll back its impact on etm decoding. is there a mean to get the actual content of program memory including patched addresses? is there a means of getting the history of patched addresses during the debugging of a program? what is the type and subtype of a BKPT instruction in a decoded trace elements? do you have any other idea for handling this situation? I am attaching the source code of the program as well as the disassembled binary. the code was compiled as an application running on linux on an ARMv7 A (STM32MP157 SoC). the breakpoint was set at line 43 in the source code (line 238 in the disassembled code) Kind Regards Zied Guermazi

4 years, 8 months

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[ACTIVITY] report week ending 30 Oct

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + more code review and assembly of the last pull request for softfreeze for QEMU 5.2 + noticed that our AArch32 Neon emulation doesn't work on big-endian hosts. RTH fixed most of this and I wrote a couple of patches to fix bugs in some insns that were only noticeable once we got out of the "anything working on vectors is broken" state :-) + looked at trying to get our documentation to build with Sphinx 3, which has made some annoying incompatible changes to the markup it accepts * VIRT-364 [QEMU support for ARMv8.1-M extensions] + started implementation of new insns VSCCLRM, CLRM, and the new FP sysregs accessed via VLDR/VSTR KVM Forum (virtual conference) was this week. Some interesting talks: * Will Deacon on what Google is doing to introduce KVM into Android * Marc Zyngier/Christoffer Dall on a virtual-only interrupt controller that's less of a big lump of code to put on a security boundary than a full-on GIC * Salil Mehta on the current problems with doing Arm vCPU hotplug in KVM thanks -- PMM

4 years, 8 months

1
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[ACTIVITY] week ending Nov. 1 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - Stratos sync call, discussion on AGL demo - Google sync call - Created a first cut of additional Xen work cards under [STR-16] [STR-16] <https://projects.linaro.org/browse/STR-16> VirtIO Portability Demo ([STR-13]) ================================== - Created a [branch with the experimental ioreq (virtio-mmio) support] - developing understanding of the ioreq piece - posted [PATCH] meson.build: fix building of Xen support for aarch64 Message-Id: <20201028174406.23424-1-alex.bennee(a)linaro.org> - continued work and expanded into [branch to clean-up and add "virt" machine] [STR-13] <https://projects.linaro.org/browse/STR-13> [branch with the experimental ioreq (virtio-mmio) support] <http://git.linaro.org/people/alex.bennee/linux.git/shortlog/refs/heads/expe…> [branch to clean-up and add "virt" machine] <https://github.com/stsquad/qemu/tree/xen/add-xen-virt-machine> Upstream Work ([QEMU-109]) ========================== - posted [PULL 0/8] testing and misc (gitdm, gitlab, docker, make) Message-Id: <20201027095938.28673-1-alex.bennee(a)linaro.org> [QEMU-109] <https://projects.linaro.org/browse/QEMU-109> Other ===== - KVM Forum 2020 Completed Reviews [2/2] ======================= [PATCH 0/2] tcg: optimize across branches Message-Id: <20201013222330.173525-1-richard.henderson(a)linaro.org> [PATCH 00/15] remove bios_name variable Message-Id: <20201026143028.3034018-8-pbonzini(a)redhat.com> Absences ======== - Welsh lockdown next week - Children at home Current Review Queue ==================== * [PATCH 0/8] arm/virt: add usb support Message-Id: <20201023071022.24916-1-kraxel(a)redhat.com> Added: <2020-10-27 Tue> * [PATCH 0/4] riscv: Add semihosting support [v10] Message-Id: <20201026212853.92880-1-keithp(a)keithp.com> Added: <2020-10-27 Tue> * [PATCH v2 0/7] xen/arm: Unbreak ACPI Message-Id: <20201023154156.6593-1-julien(a)xen.org> Added: <2020-10-24 Sat> * [PATCH v3 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20201014052140.1146924-1-crosa(a)redhat.com> Added: <2020-10-14 Wed> -- Alex Bennée

4 years, 8 months

1
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Please make clang-cmake-armv7-selfhost-neon and clang-cmake-thumbv7-full-sh green

by Galina Kistanova

4 years, 8 months

2
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[ACTIVITY] 26-30 October 2020

by Christophe Lyon

* 2 days off == Progress == * GCC upstream validation: - reported several regressions/new failures * GCC - PR96767: patch accepted - PR96770: patch accepted - patch for C++ thunks with -mpure-code and cortex-m0: iterating, almost OK - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. * infra: - debugging issues with our docker containers - added monitoring for disk space on dev machines == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 8 months

1
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[ACTIVITY] week ending 25 Oct 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] More time than I expected on float128_muladd, adjusting the codebase to share code with float64_muladd. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Posted v12, adjusting one of the smoke tests vs a distro linker bug (fixed in mainline). r~

4 years, 8 months

1
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[ACTIVITY] week ending Oct. 25 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO RPMB ([STR-5]) ===================== - Synced with with Ulf/Illias on enhancements for eMMC stacks - need to support 512 frames somehow for the CSD, everything else should be fine [STR-5] <https://projects.linaro.org/browse/STR-5> VirtIO Portability Demo ([STR-13]) ================================== - More work on trying to get Xen working on MB - more failures, this time GIC related. Might just stick to KVM - Created a [branch with the experimental ioreq (virtio-mmio) support] - Got Virgl based acceleration working on both TCG and KVM - so now fast graphics! - posted [PATCH v1 0/4] add guest-loader (for direct Xen boot) Message-Id: <20201021170842.25762-1-alex.bennee(a)linaro.org> [STR-13] <https://projects.linaro.org/browse/STR-13> [branch with the experimental ioreq (virtio-mmio) support] <http://git.linaro.org/people/alex.bennee/linux.git/shortlog/refs/heads/expe…> Upstream Work ([QEMU-109]) ========================== - Some discussion on converting the final bits of 96/128 bit softfloat - posted [RFC PATCH 0/8] fpu: experimental conversion of float128_addsub Message-Id: <20201020163738.27700-1-alex.bennee(a)linaro.org> - partial reviewed [RFC PATCH 00/15] softfloat: alternate conversion of float128_addsub Message-Id: <20201021045149.1582203-1-richard.henderson(a)linaro.org> - posted [PATCH v1 0/6] testing/next (gitdm, acceptance, docker, gitlab) Message-Id: <20201021163136.27324-5-alex.bennee(a)linaro.org> Other ===== - reclaiming space for my gmail (98.5% used!) Completed Reviews [1/1] ======================= [PATCH 0/2] tcg: optimize across branches Message-Id: <20201013222330.173525-1-richard.henderson(a)linaro.org> Absences ======== - Welsh lockdown next week - Children at home Current Review Queue ==================== * [PATCH v3 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI) Message-Id: <20201014052140.1146924-1-crosa(a)redhat.com> Added: <2020-10-14 Wed> * [PATCH v6 0/5] Enable plugin support on msys2/mingw Message-Id: <20201013002806.1447-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> * [PATCH v7 0/4] Improve cirrus msys2 Message-Id: <20201012233740.190-1-luoyonggang(a)gmail.com> Added: <2020-10-13 Tue> * [PATCH RFC 00/22] Support of Virtual CPU Hotplug for ARMv8 Arch Message-Id: <20200613213629.21984-1-salil.mehta(a)huawei.com> Added: <2020-09-23 Wed> -- Alex Bennée

4 years, 8 months

1
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[ACTIVITY] 19-23 October 2020

by Christophe Lyon

* 2 days off == Progress == * GCC upstream validation: - identified several regressions, but they had already been reported * GCC - PR96767: no feedback - PR96770: no feedback - patch for C++ thunks with -mpure-code and cortex-m0: handling further feedback - Neon intrinsics: vceqq, vceqz and vceqzq for p64 patch: no feedback * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 8 months

1
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Toolchain for cross compiling

by Suresh Nulu

Hi, I am new to toolchains. I would like to know information on building toolchains for different architectures. My objective is to build a cross compiling toolchain for AARCH64 BE target on the RHEL7.6 build system. It would be great if you can give me pointers on how to compile toolchains. Do we have any Wiki pages on building linaro toolchains for different architectures? Appreciate your help. Regards Suresh

4 years, 8 months

2
1
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[ACTIVITY] 12-16 October 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions - committed minor cleanup fixes - fixed broken trunk build with gcc-4.8 * GCC - PR96767: no feedback - PR96770: no feedback - patch for C++ thunks with -mpure-code and cortex-m0: sent updated patch - Neon intrinsics: sent patch to implement vceqq, vceqz and vceqzq for p64. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. * infra: - debugging issues with our docker containers == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 8 months

1
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[ACTIVITY] week ending 11 Oct 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] Completed capstone update. Flushed tcg patch queue. Fixed a decodetree issue for pmm. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Refreshed BTI linux-user patch set. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Fixed a couple of MTE bugs reported by Arm. r~

4 years, 8 months

1
0
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[ACTIVITY] week ending Oct. 11 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO Portability Demo ([STR-13]) ================================== - sync up discussion - posted [RFC PATCH 0/4] generic loader FDT support (for direct Xen boot) Message-Id: <20201009170742.23695-1-alex.bennee(a)linaro.org> - now GICv3 and GICv2 boot fine under TCG, pointing finger at EFI/Grub [STR-13] <https://projects.linaro.org/browse/STR-13> Upstream Work ([QEMU-109]) ========================== - posted [PATCH v1 00/22] testing and plugin fixes with gitdm updates (pre PR) Message-Id: <20201007160038.26953-1-alex.bennee(a)linaro.org> - posted [PULL 00/22] acceptance regressions, testing, gitdm, plugins Message-Id: <20201009163147.28512-1-alex.bennee(a)linaro.org> Other ===== - spent some time on JIRA cleanup for PoR - preparation for TSC health check call Completed Reviews [3/3] ======================= [PATCH v3 0/6] Enable plugin support on msys2/mingw Message-Id: <20201001163429.1348-1-luoyonggang(a)gmail.com> - CLOSING NOTE [2020-10-06 Tue 12:37] A few rough edges but seems to be on track, merged first few patches. Added: <2020-10-01 Thu> [PATCH 00/12] contrib/gitdm: First round of updates Message-Id: <20201006160653.2391972-1-f4bug(a)amsat.org> - CLOSING NOTE [2020-10-10 Sat 17:00] Merged Added: <2020-10-06 Tue> [PATCH 0/2] .mailmap: Fixes since v5.1 Message-Id: <20201004172644.2027440-1-f4bug(a)amsat.org> - CLOSING NOTE [2020-10-10 Sat 17:00] Merged Added: <2020-10-04 Sun> Absences ======== Current Review Queue ==================== * [PATCH RFC 00/22] Support of Virtual CPU Hotplug for ARMv8 Arch Message-Id: <20200613213629.21984-1-salil.mehta(a)huawei.com> Added: <2020-09-23 Wed> * [RFC PATCH 0/3] Automatically convert configure options to meson build options Message-Id: <20200913100534.22084-1-pbonzini(a)redhat.com> Added: <2020-09-13 Sun> * [PATCH 0/6] misc: Some inclusive terminology changes Message-Id: <20200910070131.435543-1-philmd(a)redhat.com> Added: <2020-09-10 Thu> * [PATCH 00/43] tcg patch queue Message-Id: <20200909001647.532249-1-richard.henderson(a)linaro.org> Added: <2020-09-09 Wed> -- Alex Bennée

4 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 9 Oct

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + another round of code review and target-arm queue wrangling + found and fixed an edge-case bug in setting Q flag in SMLAD insn + fixed a GICv3 emulation bug where we didn't ever raise maintenance interrupts * VIRT-364 [QEMU support for ARMv8.1-M extensions] + went through Arm ARM and identified exactly what the "v8.1M changes which aren't part of a named architectural feature" are (for QEMU-409 subtask) + implemented some parts of NOCP handling that were left as TODO comments for being v8.1M-specific + implemented conditional-select insns (CSEL, CSINC, CSINV, CSNEG) + implemented low-overhead-loops and branch-future (in the 'trivial' don't-cache-anything way the architecture permits) thanks -- PMM

4 years, 8 months

1
0
0 0

[ACTIVITY] 5-9 October 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions - committed minor cleanup fixes - reduced the number of gcc-testresults emails to avoid too much traffic * GCC - PR96767: no feedback - PR96770: no feedback - patch for C++ thunks with -mpure-code and cortex-m0: received comments, handling - PR96914 MVE intrinsics: committed patches to remove a few illegal ones and add the missing ones. * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues. No progress this week. == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 8 months

1
0
0 0

[ACTIVITY] 21 September - 2 October 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions - committed minor cleanup fixes - improved gcc-testresults email titles after discussion with other contributors * GCC - PR96767: patch sent - PR96770: patch sent - sent another patch to fix C++ thunks with -mpure-code and cortex-m0 - PR94595: patch committed - looking at some problems with validating with PCH disabled * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking * MVE intrinsics improvements

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Oct. 4 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO RPMB ([STR-5]) ===================== - some discussion about eMMC pass-through [STR-5] <https://projects.linaro.org/browse/STR-5> VirtIO Portability Demo ([STR-13]) ================================== - more debugging and tweaking for Xen - rooting out ACPI and DT issues - got working on QEMU TCG (with GICv2) - testing Grub patches for MachiatoBin - see state on MB Message-Id: <01000174ea0b72ae-028e8625-0ead-4cb8-a429-49bd11b5bf30-000000(a)email.amazonses.com> and state on TCG Message-Id: <87tuvcn067.fsf(a)linaro.org> - verified sound and KVM working on MachatioBin [STR-13] <https://projects.linaro.org/browse/STR-13> Upstream Work ([QEMU-109]) ========================== - posted [PULL 00/14] testing updates (python, plugins) Message-Id: <20201002113645.17693-1-alex.bennee(a)linaro.org> [QEMU-109] <https://projects.linaro.org/browse/QEMU-109> [various fixes] <https://github.com/stsquad/qemu/tree/testing/next> Completed Reviews [1/1] ======================= [PATCH v6 00/14] Reverse debugging Message-Id: <160137726426.31007.12061315974029139983.stgit@pasha-ThinkPad-X280> Current Review Queue ==================== * [PATCH v3 0/6] Enable plugin support on msys2/mingw Message-Id: <20201001163429.1348-1-luoyonggang(a)gmail.com> Added: <2020-10-01 Thu> * [PATCH RFC 00/22] Support of Virtual CPU Hotplug for ARMv8 Arch Message-Id: <20200613213629.21984-1-salil.mehta(a)huawei.com> Added: <2020-09-23 Wed> -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending 28 Sep 2020

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] Capstone patch set v4. Implement float128_muladd. Some patch review. Note, on holiday next week. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Sep. 27 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== VirtIO RPMB ([STR-5]) ===================== - posted [RFC PATCH 00/19] vhost-user-rpmb (Replay Protected Memory Block) Message-Id: <20200925125147.26943-1-alex.bennee(a)linaro.org> Upstream Work ([QEMU-109]) ========================== - posted [PATCH v1 00/15] testing/next pre-PR (python3.6, check-tcg) Message-Id: <20200925154027.12672-1-alex.bennee(a)linaro.org> - posted [PATCH] configure: make building deprecated targets easier Message-Id: <20200925161408.4016-1-alex.bennee(a)linaro.org> [QEMU-109] <https://projects.linaro.org/browse/QEMU-109> [various fixes] <https://github.com/stsquad/qemu/tree/testing/next> Completed Reviews [1/1] ======================= [PATCH v4 00/11] capstone + disassembler patches Message-Id: <20200921174118.39352-1-richard.henderson(a)linaro.org> Absences ======== - Connect (virtual) Current Review Queue ==================== * [PATCH RFC 00/22] Support of Virtual CPU Hotplug for ARMv8 Arch Message-Id: <20200613213629.21984-1-salil.mehta(a)huawei.com> Added: <2020-09-23 Wed> * [PATCH v4 00/15] Reverse debugging Message-Id: <160006358590.31457.16757371597343007847.stgit@pasha-ThinkPad-X280> Added: <2020-09-18 Fri> * [RFC PATCH 0/3] Automatically convert configure options to meson build options Message-Id: <20200913100534.22084-1-pbonzini(a)redhat.com> Added: <2020-09-13 Sun> * [PATCH 0/6] misc: Some inclusive terminology changes Message-Id: <20200910070131.435543-1-philmd(a)redhat.com> Added: <2020-09-10 Thu> -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 25 Sep

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + Got a v6 series sent to the list of the conversion of QAPI doc-comments into rST/Sphinx. This took most of the week, following Markus' detailed review on the v5 (and involved some wrestling with Meson). Optimistic that this can get into master now... thanks -- PMM

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending 20 Sep 2020

by Richard Henderson

[VIRT-349 # QEMU SVE2 Support ] Posted v3, now tested vs armie. [VIRT-327 # Richard's upstream QEMU work ] Another round of capstone patches, still needs review. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending Sep. 20 2020

by Alex Bennée

VirtIO Initiative ([STR-9]) =========================== - started reviewing [PATCH 00/11] Additional virtio device resources Message-Id: <20200824143708.5664-6-ndragazis(a)arrikto.com> - synced with Arnd and JPB on VirtIO work for [minimal memory profile stuff] [STR-9] <https://projects.linaro.org/browse/STR-9> [minimal memory profile stuff] <https://projects.linaro.org/browse/STR-8> VirtIO RPMB ([STR-5]) ===================== - worked with Illias to get him up and running with uboot virtio-rpmb driver - debugging differences in HMAC implementations :-/ [STR-5] <https://projects.linaro.org/browse/STR-5> VirtIO Portability Demo ([STR-13]) ================================== - continue to debug nouvaue issues on latest kernel - need to ESC/reset to EFI until framebuffer comes on - seems ok with Debian 5.6.14-2~bpo10+1 - but not vanilla 5.6.14 or above - need to track down kernel differences - did some poking into getting Xen up on Debian - seems multiboot not the way, got a bit further but need a debug build [STR-13] <https://projects.linaro.org/browse/STR-13> Upstream Work ([QEMU-109]) ========================== - posted [PATCH v1 0/6] deprecation and linux-user tweaks (+test fix) Message-Id: <20200914150716.10501-5-alex.bennee(a)linaro.org> - posted [PATCH v2 0/8] configure deprecation, linux-user and iotest fixes Message-Id: <20200915134317.11110-1-alex.bennee(a)linaro.org> - posted [PULL 0/8] configure deprecation, linux-user and test fix Message-Id: <20200916122648.17468-1-alex.bennee(a)linaro.org> [QEMU-109] <https://projects.linaro.org/browse/QEMU-109> Completed Reviews [2/2] ======================= [RISU PATCH 0/2] arm.risu: two minor fixes Message-Id: <20200901162046.32670-1-peter.maydell(a)linaro.org> [PATCH V3 00/10] fix some comment spelling errors Message-Id: <20200917075029.313-1-zhaolichang(a)huawei.com> Absences ======== - Family self-isolated for first half of week Current Review Queue ==================== * [PATCH v4 00/15] Reverse debugging Message-Id: <160006358590.31457.16757371597343007847.stgit@pasha-ThinkPad-X280> Added: <2020-09-18 Fri> * [RFC PATCH 0/3] Automatically convert configure options to meson build options Message-Id: <20200913100534.22084-1-pbonzini(a)redhat.com> Added: <2020-09-13 Sun> * [PATCH 0/6] misc: Some inclusive terminology changes Message-Id: <20200910070131.435543-1-philmd(a)redhat.com> Added: <2020-09-10 Thu> * [PATCH 00/43] tcg patch queue Message-Id: <20200909001647.532249-1-richard.henderson(a)linaro.org> Added: <2020-09-09 Wed> -- Alex Bennée

4 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 18 Sep

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + usual maintainer stuff + started a rebase/respin of the convert-QAPI-docs-to-Sphinx series * VIRT-364 [QEMU support for ARMv8.1-M extensions] + sent patchset to make QEMU handle the way M-profile and A-profile report presence of fp16 differently in their ID registers thanks -- PMM

4 years, 9 months

1
0
0 0

[ACTIVITY] 14-18 September 2020

by Christophe Lyon

== Progress == * GCC upstream validation: - reported several regressions - committed minor cleanup fixes * GCC - PR96767: patch almost ready - PR71233: missing ACLE intrinsics, updated the list. Created PR96914 with the missing MVE intrinsics * benchmarking: - Scripts to run coremark on stm32 now merged, debugging issues == Next == * GCC/cortex-M testing improvements & fixes * cortex-m benchmarking

4 years, 9 months

1
0
0 0

[ACTIVITY] week ending 14 Sep 2020

by Richard Henderson

[ Sorry it's a bit late. ] [VIRT-327 # Richard's upstream QEMU work ] Send out tcg patch queue. Prototype a disassembler using llvm. Not ideal. If we proceed with this further, we should probably schedule time for it, because the job is not small. Updating the capstone submodule; a couple of rounds converting that to meson. r~

4 years, 9 months

1
0
0 0

[ACTIVITY] 7 - 11 September 2020

by Prathamesh Kulkarni

== This Week == * GNU-659 (calculix) - Comparing code-gen of hoisting region doesn't show many more extra stores - Came up with two heuristics, which "fix" the issue, but aren't very general. * LLVM-611 - D79785: Created fix for expensive checks issue, and posted on llvm-dev - D87430: Posted patch for adding heuristic to LowerCall. == Next Week == - Continue ongoing tasks

4 years, 9 months

1
0
0 0

libcxx-libcxxabi-libunwind-armv7-linux-noexceptions broken

by Louis Dionne

Hi, Something appears to be wrong with your builder libcxx-libcxxabi-libunwind-armv7-linux-noexceptions: http://lab.llvm.org:8011/builders/libcxx-libcxxabi-libunwind-armv7-linux-no… It's been failing that way for over 2 weeks now. Is anyone monitoring those builders? Louis

4 years, 9 months

1
0
0 0

linaro-tk1-03

by Galina Kistanova

Hello Linaro Toolchain Working Group, Do you plan to bring linaro-tk1-03 back online soon? If not, I'll remove it from the LLVM buildbot this Friday. Thanks Galina

4 years, 9 months

2
1
0 0

[ACTIVITY] week ending 6 Sep 2020

by Richard Henderson

[VIRT-349 # QEMU SVE2 Support ] Continuing the testing vs armie. [VIRT-327 # Richard's upstream QEMU work ] * More microblaze cleanup, including a check-acceptance regression fix from the first pull. Ho hum. * Patch review, queue is empty again. * Old patch queue cleanup, Fixed some gvec bugs affecting 32-bit x86; testing vs aa32 risu. r~

4 years, 9 months

1
0
0 0

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