- linaro-toolchain - lists.linaro.org

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Code review. In particular: reviewed RTH's FEAT_RME series - Wrote and sent an RFC patchset proposing renaming of the badly misnamed '-singlestep' command line option (it actually does "put only one guest instruction in each JIT basic block") -- PMM

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending Feb. 12 2023

by Alex Bennée

Project Stratos =============== - more prep work for Project Orko FEAT_RME, CCA Realms ([QEMU-466]) ================================= - sync up meeting with Huawei - see QEMU, FEAT_RME/CCA and next steps Message-Id: <87mt5ln2t6.fsf(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py Message-Id: <20230203181632.2919715-1-alex.bennee(a)linaro.org> - continued working on [testing/next] with tuxrun tests - hacked up [PoC to use local QEMU in TuxRun] [UM-2] <https://linaro.atlassian.net/browse/UM-2> [testing/next] <https://github.com/stsquad/qemu/tree/testing/next> [PoC to use local QEMU in TuxRun] <https://gitlab.com/stsquad/tuxrun/-/commit/0f9711c18b7e723e1c50c8a8fd116b93…> Completed Reviews [3/3] ======================= [PATCH v3 0/9] virtio-gpu: Support Venus Vulkan driver Message-Id: <20220926142422.22325-1-antonio.caggiano(a)collabora.com> [PATCH] gdbstub: move update guest debug to accel ops Message-Id: <20221123121712.72817-1-mads(a)ynddal.dk> [PATCH v2 0/3] Add gdbstub support to HVF Message-Id: <20221116174749.65175-1-fcagnin(a)quarkslab.com> Current Review Queue ==================== TODO [PATCH 00/22] target/arm: Implement FEAT_RME Message-Id: <20230124000027.3565716-1-richard.henderson(a)linaro.org> ==================================================================================================================== TODO [RFC PATCH 00/16] Add stage-2 translation for SMMUv3 Message-Id: <20230205094411.793816-1-smostafa(a)google.com> ================================================================================================================== TODO [PATCH v2 0/2] fix for #285 Message-Id: <20230205163758.416992-1-cota(a)braap.org> ==================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 7 months

1
0
0 0

Re: Seeking toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi

by Maxim Kuvyrkov

[CC: linaro-toolchain@] Hi Bryan, I don't think that Linaro has ever released a toolchain with uClibc, but I may be wrong. Could you provide additional information about the target, rootfs and your setup? -- Maxim Kuvyrkov https://www.linaro.org > On Feb 7, 2023, at 10:31 AM, Bryan Phillippe <bp(a)darkforest.org> wrote: > > > Hello! I know this is a long shot, but I have a few devices with code that was built using this toolchain: toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi > > I'm trying to find a copy of that so I can rebuild 1 binary/package on the system without blowing everything up. Do you have any idea where I can find this toolchain? Thank you so much in advance! > > -- > -bp >

2 years, 7 months

1
0
0 0

[ACTIVITY] Report for week #5

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - The patches were already reviewed by 3 maintainers, so started addressing their review comments and answering questions. - Committed first two patches in the series, which were self-contained code improvements. -- Thiago

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending Feb. 5 2023

by Alex Bennée

Project Stratos =============== - posted [PATCH v2] backends/vhost-user: remove the ioeventfd check Message-Id: <20230130124728.175610-1-alex.bennee(a)linaro.org> - bunch of sync and planning for Project Orko - see Project Orko requirements from TRS Message-Id: <87sffmke2i.fsf(a)linaro.org> - also debugging some TRS <-> QEMU interactions - posted [RFC PATCH] target/arm: disable FEAT_SME if we turn off SVE Message-Id: <20230203100551.2445547-1-alex.bennee(a)linaro.org> [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL v2 00/36] Testing, docs, semihosting and plugin updates Message-Id: <20230202160109.2061994-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py Message-Id: <20230203181632.2919715-1-alex.bennee(a)linaro.org> Other ===== - Did some investigation into LKFT regressions - posted Initial investigation of slowness kselftest job Message-Id: <1ba91912e18492c7dafedc5fbd5aef817f109d53fdc95554870edf077a6e21dc(a)mu.id> - posted Candidate patches for Debian's 7.2 release (and backports) Message-Id: <87edr8kqqq.fsf(a)linaro.org> Completed Reviews [4/4] ======================= [PATCH v6 00/36] tcg: Support for Int128 with helpers Message-Id: <20230130214844.1158612-1-richard.henderson(a)linaro.org> [PATCH] vhost-user-gpio: Configure vhost_dev when connecting Message-Id: <20230130140320.77999-1-akihiko.odaki(a)daynix.com> [PATCH] configure: Bump minimum Clang version to 10.0 Message-Id: <20230131180239.1582302-1-thuth(a)redhat.com> [PATCH v3 0/9] virtio-gpu: Support Venus Vulkan driver Message-Id: <20220926142422.22325-1-antonio.caggiano(a)collabora.com> Current Review Queue ==================== TODO [PATCH 0/4] Fix deadlock when dying because of a signal Message-Id: <20230201004609.3005029-1-iii(a)linux.ibm.com> ==================================================================================================================== TODO [RFC PATCH v1 0/8] Look Ma! We made a XenStore Message-Id: <20230201144358.1744876-1-dwmw2(a)infradead.org> ============================================================================================================= TODO [QEMU][PATCH v5 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230131225149.14764-1-vikram.garhwal(a)amd.com> ==================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 3 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual upstream maintenance tasks - the CI/tests have got rather flaky of late: trying to find out why... * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - FEAT_FGT: is now upstream -- PMM

2 years, 7 months

1
0
0 0

[ACTIVITY] Report for week #4

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued preparing patches for upstream submission. Did some final code and testcase cleanups, updated/rewrote patch descriptions, wrote the cover letter and the list of changes from v2. - Posted the patches upstream¹. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20230130044518.3322695-1-thiago.ba…

2 years, 7 months

1
0
0 0

[ACTIVITY] week ending Jan. 29 2023

by Alex Bennée

Project Stratos =============== - reading up on the linux-mm subsystem - learning about struct vma_area [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> FEAT_RME, CCA Realms ([QEMU-466]) ================================= - more review of [PATCH v5 00/36] tcg: Support for Int128 with helpers Message-Id: <20230126043824.54819-1-richard.henderson(a)linaro.org> [QEMU-466] <https://linaro.atlassian.net/browse/QEMU-466> QEMU Upstream Work ([UM-2]) =========================== - updated maintainer trees, running [CI over weekend] - posted [PULL 00/35] Testing, docs, semihosting and plugin updates Message-Id: <20230126112250.2584701-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> [CI over weekend] <https://gitlab.com/stsquad/qemu/-/pipelines/753447926> Current Review Queue ==================== TODO [RFC PATCH 00/16] arm: Run Arm CCA VMs with KVM Message-Id: <20230127150727.612594-1-jean-philippe(a)linaro.org> ================================================================================================================== TODO [QEMU][PATCH v4 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230125085407.7144-1-vikram.garhwal(a)amd.com> =================================================================================================================================== TODO [PATCH v3 0/3] tcg: add perfmap and jitdump Message-Id: <20230111014705.2275040-1-iii(a)linux.ibm.com> ======================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 27 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual upstream maintenance tasks * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - FEAT_FGT: finished coding, did some testing, sent patches for review -- PMM

2 years, 7 months

1
0
0 0

[TCWG CI] [TCWG CI] 465.tonto failed to build after gdb-13-branchpoint-527-g46758593515: Rename to allow_ifunc_tests

by ci_notify＠linaro.org

After gdb-13-branchpoint-527-g46758593515 commit 4675859351582f017b495ff13fb2ea72a99834af Author: Tom Tromey <tom(a)tromey.com> Rename to allow_ifunc_tests the following benchmarks slowed down by more than 3%: - 465.tonto failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of gdb-13-branchpoint-527-g46758593515 commit for tcwg_bmk-code_speed-spec2k6: commit 4675859351582f017b495ff13fb2ea72a99834af Author: Tom Tromey <tom(a)tromey.com> Date: Sun Jan 8 11:41:19 2023 -0700 Rename to allow_ifunc_tests This changes skip_ifunc_tests to invert the sense, and renames it to allow_ifunc_tests. * gnu-aarch64-master-O3 ** After gdb-13-branchpoint-527-g46758593515 commit 4675859351582f017b495ff13fb2ea72a99834af ** Author: Tom Tromey <tom(a)tromey.com> ** ** Rename to allow_ifunc_tests ** ** the following benchmarks slowed down by more than 3%: ** - 465.tonto failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Reproduce current build: <cut> mkdir -p investigate-binutils-4675859351582f017b495ff13fb2ea72a99834af cd investigate-binutils-4675859351582f017b495ff13fb2ea72a99834af # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 4675859351582f017b495ff13fb2ea72a99834af Author: Tom Tromey <tom(a)tromey.com> Date: Sun Jan 8 11:41:19 2023 -0700 Rename to allow_ifunc_tests This changes skip_ifunc_tests to invert the sense, and renames it to allow_ifunc_tests. --- gdb/testsuite/gdb.base/gnu-ifunc.exp | 2 +- gdb/testsuite/gdb.compile/compile-ifunc.exp | 2 +- gdb/testsuite/lib/gdb.exp | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/gdb/testsuite/gdb.base/gnu-ifunc.exp b/gdb/testsuite/gdb.base/gnu-ifunc.exp index 967d1e053e7..81119f764b8 100644 --- a/gdb/testsuite/gdb.base/gnu-ifunc.exp +++ b/gdb/testsuite/gdb.base/gnu-ifunc.exp @@ -13,7 +13,7 @@ # You should have received a copy of the GNU General Public License # along with this program. If not, see <http://www.gnu.org/licenses/>. -require !skip_shlib_tests !skip_ifunc_tests +require !skip_shlib_tests allow_ifunc_tests standard_testfile .c set staticexecutable ${testfile}-static diff --git a/gdb/testsuite/gdb.compile/compile-ifunc.exp b/gdb/testsuite/gdb.compile/compile-ifunc.exp index bfbe65a503b..990d35a53f6 100644 --- a/gdb/testsuite/gdb.compile/compile-ifunc.exp +++ b/gdb/testsuite/gdb.compile/compile-ifunc.exp @@ -15,7 +15,7 @@ load_lib compile-support.exp -require !skip_ifunc_tests +require allow_ifunc_tests standard_testfile diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp index 7143908bbc2..3a1936ffc82 100644 --- a/gdb/testsuite/lib/gdb.exp +++ b/gdb/testsuite/lib/gdb.exp @@ -3972,17 +3972,17 @@ gdb_caching_proc has_int128_cxx { return [gdb_int128_helper c++] } -# Return true if the IFUNC feature is unsupported. -gdb_caching_proc skip_ifunc_tests { +# Return true if the IFUNC feature is supported. +gdb_caching_proc allow_ifunc_tests { if [gdb_can_simple_compile ifunc { extern void f_ (); typedef void F (void); F* g (void) { return &f_; } void f () __attribute__ ((ifunc ("g"))); } object] { - return 0 - } else { return 1 + } else { + return 0 } } </cut>

2 years, 7 months

3
3
0 0

[ACTIVITY] Report for week #3

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued preparing patches for upstream submission. Realised I had to document my changes to the remote protocol in the GDB manual, so did that. Also making small code cleanups and updating/rewriting patch descriptions. - Noticed I could to a small optimisation in one patch, but it would involve a lot of refactoring to move GDB-specific code so that it could also be used by gdbserver, so saved the WIP branch for later. # TCWG CI - Investigated failure report from yesterday's email. Reproduced on tcwg-jade-03 with a slightly different build failure, but wasn't able to make much progress¹. -- Thiago ¹ https://lists.linaro.org/archives/list/linaro-toolchain@lists.linaro.org/th…

2 years, 7 months

1
0
0 0

[ACTIVITY] report week ending 20 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual upstream maintenance tasks * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - FEAT_FGT getting closer towards being done: I just have to mark up the ARMCPRegInfo structs for HDFGRTR traps, and write the code to handle traps on ERET and SVC -- PMM

2 years, 8 months

1
0
0 0

[ACTIVITY] week ending Jan. 22 2023

by Alex Bennée

Project Stratos =============== - finished draft of [proposal for Unprivilaged VirtIO API] - sent out for comment [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> vhost-device maintainer effort ([UM-196]) - a few version bump reviews [UM-196] <https://linaro.atlassian.net/browse/UM-196> Plugin register access ([QEMU-495]) =================================== - posted [PATCH v2 00/21] gdbstub: re-organise to for better compilation behaviour Message-Id: <20230105164320.2164095-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] docs: add some details about compilation units to coding style Message-Id: <20230103104758.767266-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: fix handling of HLT semihosting in system mode Message-Id: <20230105114304.2017493-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] testing: probe gdb for supported architectures ahead of time Message-Id: <20230105181533.2235792-1-alex.bennee(a)linaro.org> - posted [PATCH v2] scripts/ci: update gitlab-runner playbook to use latest runner Message-Id: <20230106152338.2599827-1-alex.bennee(a)linaro.org> - posted [PATCH 00/18] testing/next updates (gitlab, docker, check-tcg) Message-Id: <20230119180419.30304-1-alex.bennee(a)linaro.org> - updated maintainer trees, running [CI over weekend] [UM-2] <https://linaro.atlassian.net/browse/UM-2> [CI over weekend] <https://gitlab.com/stsquad/qemu/-/pipelines/753447926> Completed Reviews [7/7] ======================= [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH v2] semihosting: add O_BINARY flag in host_open for NT compatibility Message-Id: <20230106102018.20520-1-eiakovlev(a)linux.microsoft.com> [PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64 Message-Id: <75da8346.1fd34.1856e0d08ef.Coremail.fanwj(a)mail.ustc.edu.cn> [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> [PATCH v2 00/22] tcg: exit_tb tidy, goto_tb reorg Message-Id: <20230109014248.2894281-1-richard.henderson(a)linaro.org> [PATCH v3 0/8] Fix win32/msys2 shader compilation & update lcitool deps Message-Id: <20230110080246.536056-1-marcandre.lureau(a)redhat.com> Other ===== - bit of travel forecasting Current Review Queue ==================== TODO [PATCH 0/3] various aarch64 fixes for running Hyper-V on TCG Message-Id: <20230105221251.17896-1-eiakovlev(a)linux.microsoft.com> =================================================================================================================================== TODO [PATCH 0/4] tsan fixes Message-Id: <20230108163905.59601-1-cota(a)braap.org> ============================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 8 months

1
0
0 0

[TCWG CI] [TCWG CI] 481.wrf failed to build after gdb-13-branchpoint-388-g71fa8692930: sim: cris: move arch-specific file compilation to top-level

by ci_notify＠linaro.org

After gdb-13-branchpoint-388-g71fa8692930 commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> sim: cris: move arch-specific file compilation to top-level the following benchmarks slowed down by more than 3%: - 481.wrf failed to build - 416.gamess failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: arm-linux-gnueabihf - Compiler flags: -O3 -flto -marm - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of gdb-13-branchpoint-388-g71fa8692930 commit for tcwg_bmk-code_speed-spec2k6: commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> Date: Sun Jan 1 13:40:11 2023 -0500 sim: cris: move arch-specific file compilation to top-level * gnu-arm-master-O3_LTO ** After gdb-13-branchpoint-388-g71fa8692930 commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 ** Author: Mike Frysinger <vapier(a)gentoo.org> ** ** sim: cris: move arch-specific file compilation to top-level ** ** the following benchmarks slowed down by more than 3%: ** - 481.wrf failed to build ** - 416.gamess failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… Reproduce current build: <cut> mkdir -p investigate-binutils-71fa8692930cd5fc3f332415cf642d3aa5f55fc6 cd investigate-binutils-71fa8692930cd5fc3f332415cf642d3aa5f55fc6 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-arm-master-O3_LTO… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 71fa8692930cd5fc3f332415cf642d3aa5f55fc6 Author: Mike Frysinger <vapier(a)gentoo.org> Date: Sun Jan 1 13:40:11 2023 -0500 sim: cris: move arch-specific file compilation to top-level --- sim/Makefile.in | 3 --- sim/cris/local.mk | 3 --- 2 files changed, 6 deletions(-) diff --git a/sim/Makefile.in b/sim/Makefile.in index 435c36b2b83..0ad692126e7 100644 --- a/sim/Makefile.in +++ b/sim/Makefile.in @@ -4801,9 +4801,6 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo @SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< >$@ @SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD): cris/hw-config.h -@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: cris/%.c -@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) - @SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c @SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) @SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS) diff --git a/sim/cris/local.mk b/sim/cris/local.mk index 912ca12a32f..3950baed7a1 100644 --- a/sim/cris/local.mk +++ b/sim/cris/local.mk @@ -47,9 +47,6 @@ $(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h noinst_LIBRARIES += %D%/libsim.a -%D%/%.o: %D%/%.c - $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) - %D%/%.o: common/%.c $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F) </cut>

2 years, 8 months

1
0
0 0

[TCWG CI] [TCWG CI] 459.GemsFDTD failed to build after glibc-2.36.9000-435-g569cfcc6bf: hurd: Fix _NOFLSH value

by ci_notify＠linaro.org

After glibc-2.36.9000-435-g569cfcc6bf commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> hurd: Fix _NOFLSH value the following benchmarks slowed down by more than 3%: - 459.GemsFDTD failed to build - 436.cactusADM failed to build Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. For your convenience, we have uploaded tarballs with pre-processed source and assembly files at: - First_bad save-temps: $FIRST_BAD_ARTIFACTS/save-temps/ - Last_good save-temps: $LAST_GOOD_ARTIFACTS/save-temps/ - Baseline save-temps: $BASELINE_ARTIFACTS/save-temps/ Configuration: - Benchmark: SPEC CPU2006 - Toolchain: GCC + Glibc + GNU Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 -flto - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of glibc-2.36.9000-435-g569cfcc6bf commit for tcwg_bmk-code_speed-spec2k6: commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> Date: Sun Jan 15 20:54:42 2023 +0100 hurd: Fix _NOFLSH value shifting 1 (thus an integer) left 31 bit is undefined behavior. We have to make it an unsigned integer to properly get 0x80000000 (like done in other places). * gnu-aarch64-master-O3_LTO ** After glibc-2.36.9000-435-g569cfcc6bf commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 ** Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> ** ** hurd: Fix _NOFLSH value ** ** the following benchmarks slowed down by more than 3%: ** - 459.GemsFDTD failed to build ** - 436.cactusADM failed to build ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… Reproduce current build: <cut> mkdir -p investigate-glibc-569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 cd investigate-glibc-569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-gnu-aarch64-master-O3… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 569cfcc6bf35c28112ca8d7112e9eb4a22bed5b8 Author: Samuel Thibault <samuel.thibault(a)ens-lyon.org> Date: Sun Jan 15 20:54:42 2023 +0100 hurd: Fix _NOFLSH value shifting 1 (thus an integer) left 31 bit is undefined behavior. We have to make it an unsigned integer to properly get 0x80000000 (like done in other places). --- bits/termios.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bits/termios.h b/bits/termios.h index ae62d00853..4439c2f14e 100644 --- a/bits/termios.h +++ b/bits/termios.h @@ -246,7 +246,7 @@ struct termios # define NOKERNINFO (1 << 25) /* Disable VSTATUS. */ # define PENDIN (1 << 29) /* Retype pending input (state). */ #endif -#define _NOFLSH (1 << 31) /* Disable flush after interrupt. */ +#define _NOFLSH (1U << 31) /* Disable flush after interrupt. */ #define NOFLSH _NOFLSH /* Control characters. */ </cut>

2 years, 8 months

1
0
0 0

[TCWG CI] [TCWG CI] 521.wrf_r slowed down by 5% after basepoints/gcc-13-5062-gcb93c5f8008: Subject: [committed, pushed, Modula2] Added missing dependency.

by ci_notify＠linaro.org

[Error replacing 'FILE' - Error processing tokens]

2 years, 8 months

1
0
0 0

[TCWG CI] [TCWG CI] 445.gobmk slowed down by 6% after llvmorg-16-init-16383-g9b5f62685ab4: [SLP]Fix cost of the broadcast buildvector/gather.

by ci_notify＠linaro.org

After llvmorg-16-init-16383-g9b5f62685ab4 commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> [SLP]Fix cost of the broadcast buildvector/gather. the following benchmarks slowed down by more than 3%: - 445.gobmk slowed down by 6% from 10321 to 10904 perf samples Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don\'t have access to Linaro TCWG CI. Configuration: - Benchmark: SPEC CPU2006 - Toolchain: Clang + Glibc + LLVM Linker - Version: all components were built from their tip of trunk - Target: arm-linux-gnueabihf - Compiler flags: -O3 -flto -marm - Hardware: This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-16-init-16383-g9b5f62685ab4 commit for tcwg_bmk-code_speed-spec2k6: commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> Date: Wed Dec 21 13:38:38 2022 -0800 [SLP]Fix cost of the broadcast buildvector/gather. Need to include the cost of the initial insertelement to the cost of the broadcasts. Also, need to adjust the cost of the gather/buildvector if the element is inserted into poison/undef vector. Differential Revision: https://reviews.llvm.org/D140498 * llvm-arm-master-O3_LTO ** After llvmorg-16-init-16383-g9b5f62685ab4 commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b ** Author: Alexey Bataev <a.bataev(a)outlook.com> ** ** [SLP]Fix cost of the broadcast buildvector/gather. ** ** the following benchmarks slowed down by more than 3%: ** - 445.gobmk slowed down by 6% from 10321 to 10904 perf samples ** https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Bad build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Good build: https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… Reproduce current build: <cut> mkdir -p investigate-llvm-9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b cd investigate-llvm-9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_bmk-code_speed-spec2k6-llvm-arm-master-O3_LT… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_bmk-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 9b5f62685ab447ba9d3ea8ac2616e0c76a44d21b Author: Alexey Bataev <a.bataev(a)outlook.com> Date: Wed Dec 21 13:38:38 2022 -0800 [SLP]Fix cost of the broadcast buildvector/gather. Need to include the cost of the initial insertelement to the cost of the broadcasts. Also, need to adjust the cost of the gather/buildvector if the element is inserted into poison/undef vector. Differential Revision: https://reviews.llvm.org/D140498 --- llvm/include/llvm/Analysis/TargetTransformInfo.h | 12 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 4 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 54 +-- llvm/lib/Analysis/TargetTransformInfo.cpp | 8 +- .../Target/AArch64/AArch64TargetTransformInfo.cpp | 7 +- .../Target/AArch64/AArch64TargetTransformInfo.h | 4 +- .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h | 2 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 7 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 4 +- .../Target/Hexagon/HexagonTargetTransformInfo.cpp | 6 +- .../Target/Hexagon/HexagonTargetTransformInfo.h | 4 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 9 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 4 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 7 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 +- .../Target/SystemZ/SystemZTargetTransformInfo.cpp | 5 +- .../Target/SystemZ/SystemZTargetTransformInfo.h | 4 +- .../WebAssembly/WebAssemblyTargetTransformInfo.cpp | 5 +- .../WebAssembly/WebAssemblyTargetTransformInfo.h | 4 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 42 ++- llvm/lib/Target/X86/X86TargetTransformInfo.h | 4 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 21 +- .../Analysis/CostModel/X86/loop_v2-inseltpoison.ll | 2 +- llvm/test/Analysis/CostModel/X86/loop_v2.ll | 2 +- .../X86/masked-intrinsic-cost-inseltpoison.ll | 4 +- .../CostModel/X86/masked-intrinsic-cost.ll | 4 +- .../CostModel/X86/vector-insert-inseltpoison.ll | 120 +++---- llvm/test/Analysis/CostModel/X86/vector-insert.ll | 120 +++---- .../Analysis/CostModel/X86/vshift-ashr-codesize.ll | 50 +-- .../CostModel/X86/vshift-ashr-cost-inseltpoison.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-ashr-cost.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-ashr-latency.ll | 18 +- .../CostModel/X86/vshift-ashr-sizelatency.ll | 50 +-- .../Analysis/CostModel/X86/vshift-lshr-codesize.ll | 82 +---- .../CostModel/X86/vshift-lshr-cost-inseltpoison.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-lshr-cost.ll | 102 ++---- .../Analysis/CostModel/X86/vshift-lshr-latency.ll | 102 ++---- .../CostModel/X86/vshift-lshr-sizelatency.ll | 82 +---- .../Analysis/CostModel/X86/vshift-shl-codesize.ll | 82 +---- .../CostModel/X86/vshift-shl-cost-inseltpoison.ll | 138 ++----- .../test/Analysis/CostModel/X86/vshift-shl-cost.ll | 138 ++----- .../Analysis/CostModel/X86/vshift-shl-latency.ll | 102 ++---- .../CostModel/X86/vshift-shl-sizelatency.ll | 174 ++------- llvm/test/Transforms/SLPVectorizer/X86/cse.ll | 7 +- .../Transforms/SLPVectorizer/X86/malformed_phis.ll | 140 ++++---- .../X86/remark_gather-load-redux-cost.ll | 2 +- .../SLPVectorizer/X86/used-reduced-op.ll | 399 +++++++++++---------- 50 files changed, 941 insertions(+), 1522 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 6200af73842c..a9cb8717ffa8 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1193,7 +1193,8 @@ public: /// case is to provision the cost of vectorization/scalarization in /// vectorizer passes. InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index = -1) const; + unsigned Index = -1, Value *Op0 = nullptr, + Value *Op1 = nullptr) const; /// \return The expected cost of vector Insert and Extract. /// This is used when instruction is available, and implementation @@ -1786,7 +1787,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I) = 0; virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) = 0; + unsigned Index, Value *Op0, + Value *Op1) = 0; virtual InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) = 0; @@ -2358,9 +2360,9 @@ public: const Instruction *I) override { return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) override { - return Impl.getVectorInstrCost(Opcode, Val, Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) override { + return Impl.getVectorInstrCost(Opcode, Val, Index, Op0, Op1); } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) override { diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index e81e430f6624..262b42a05d99 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -585,8 +585,8 @@ public: return 1; } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) const { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) const { return 1; } diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index aabb94d82c4b..f27c6899d757 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -90,10 +90,12 @@ private: InstructionCost Cost = 0; // Broadcast cost is equal to the cost of extracting the zero'th element // plus the cost of inserting it into every element of the result vector. - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, 0); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, 0, + nullptr, nullptr); for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i, + nullptr, nullptr); } return Cost; } @@ -110,8 +112,10 @@ private: // vector and finally index 3 of second vector and insert them at index // <0,1,2,3> of result vector. for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i); - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, i, + nullptr, nullptr); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, i, + nullptr, nullptr); } return Cost; } @@ -134,9 +138,9 @@ private: // type. for (int i = 0; i != NumSubElts; ++i) { Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, - i + Index); - Cost += - thisT()->getVectorInstrCost(Instruction::InsertElement, SubVTy, i); + i + Index, nullptr, nullptr); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, SubVTy, i, + nullptr, nullptr); } return Cost; } @@ -158,10 +162,10 @@ private: // the source type plus the cost of inserting them into the result vector // type. for (int i = 0; i != NumSubElts; ++i) { - Cost += - thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVTy, i); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, SubVTy, + i, nullptr, nullptr); Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, - i + Index); + i + Index, nullptr, nullptr); } return Cost; } @@ -212,7 +216,7 @@ private: FixedVectorType::get( PointerType::get(VT->getElementType(), 0), VT->getNumElements()), - -1) + -1, nullptr, nullptr) : 0; InstructionCost LoadCost = VT->getNumElements() * @@ -237,7 +241,7 @@ private: Instruction::ExtractElement, FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()), VT->getNumElements()), - -1) + + -1, nullptr, nullptr) + getCFInstrCost(Instruction::Br, CostKind) + getCFInstrCost(Instruction::PHI, CostKind)); } @@ -722,9 +726,11 @@ public: if (!DemandedElts[i]) continue; if (Insert) - Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, Ty, i); + Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, Ty, i, + nullptr, nullptr); if (Extract) - Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, i); + Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, i, + nullptr, nullptr); } return Cost; @@ -1123,7 +1129,7 @@ public: InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) { return thisT()->getVectorInstrCost(Instruction::ExtractElement, VecTy, - Index) + + Index, nullptr, nullptr) + thisT()->getCastInstrCost(Opcode, Dst, VecTy->getElementType(), TTI::CastContextHint::None, TTI::TCK_RecipThroughput); @@ -1184,14 +1190,20 @@ public: return 1; } - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1) { return getRegUsageForType(Val->getScalarType()); } InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index) { - return thisT()->getVectorInstrCost(I.getOpcode(), Val, Index); + Value *Op0 = nullptr; + Value *Op1 = nullptr; + if (auto *IE = dyn_cast<InsertElementInst>(&I)) { + Op0 = IE->getOperand(0); + Op1 = IE->getOperand(1); + } + return thisT()->getVectorInstrCost(I.getOpcode(), Val, Index, Op0, Op1); } InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, @@ -2246,7 +2258,8 @@ public: ArithCost += NumReduxLevels * thisT()->getArithmeticInstrCost(Opcode, Ty, CostKind); return ShuffleCost + ArithCost + - thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } /// Try to calculate the cost of performing strict (in-order) reductions, @@ -2353,7 +2366,8 @@ public: // The last min/max should be in vector registers and we counted it above. // So just need a single extractelement. return ShuffleCost + MinMaxCost + - thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + thisT()->getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 7459ce18c3cf..d03a8cf14172 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -897,13 +897,13 @@ InstructionCost TargetTransformInfo::getCmpSelInstrCost( return Cost; } -InstructionCost TargetTransformInfo::getVectorInstrCost(unsigned Opcode, - Type *Val, - unsigned Index) const { +InstructionCost TargetTransformInfo::getVectorInstrCost( + unsigned Opcode, Type *Val, unsigned Index, Value *Op0, Value *Op1) const { // FIXME: Assert that Opcode is either InsertElement or ExtractElement. // This is mentioned in the interface description and respected by all // callers, but never asserted upon. - InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index); + InstructionCost Cost = + TTIImpl->getVectorInstrCost(Opcode, Val, Index, Op0, Op1); assert(Cost >= 0 && "TTI should not produce negative costs!"); return Cost; } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index ae12ae951d75..f5f6c07f766a 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -2034,8 +2034,8 @@ InstructionCost AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, // Get the cost for the extract. We compute the cost (if any) for the extend // below. - InstructionCost Cost = - getVectorInstrCost(Instruction::ExtractElement, VecTy, Index); + InstructionCost Cost = getVectorInstrCost(Instruction::ExtractElement, VecTy, + Index, nullptr, nullptr); // Legalize the types. auto VecLT = getTypeLegalizationCost(VecTy); @@ -2128,7 +2128,8 @@ InstructionCost AArch64TTIImpl::getVectorInstrCostHelper(Type *Val, } InstructionCost AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { return getVectorInstrCostHelper(Val, Index, false /* HasRealUse */); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index e309117a885b..6eaff9566b8c 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -169,8 +169,8 @@ public: InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I = nullptr); - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, unsigned Index); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index af72ba2daa2d..00e6970291bf 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -790,7 +790,8 @@ GCNTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, } InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { switch (Opcode) { case Instruction::ExtractElement: case Instruction::InsertElement: { @@ -799,7 +800,7 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, if (EltSize < 32) { if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) return 0; - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } // Extracts are just reads of a subregister, so are free. Inserts are @@ -810,7 +811,7 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return Index == ~0u ? 2 : 0; } default: - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h index 347ce87acd26..4a1137dcf2e2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -162,7 +162,7 @@ public: using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index); + unsigned Index, Value *Op0, Value *Op1); bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const; bool isSourceOfDivergence(const Value *V) const; diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp index 365c005b2503..c3dd321a7b9c 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp @@ -108,14 +108,15 @@ InstructionCost R600TTIImpl::getCFInstrCost(unsigned Opcode, } InstructionCost R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { switch (Opcode) { case Instruction::ExtractElement: case Instruction::InsertElement: { unsigned EltSize = DL.getTypeSizeInBits(cast<VectorType>(ValTy)->getElementType()); if (EltSize < 32) { - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } // Extracts are just reads of a subregister, so are free. Inserts are @@ -126,7 +127,7 @@ InstructionCost R600TTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return Index == ~0u ? 2 : 0; } default: - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } } diff --git a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h index f1a198fd14e4..9045cc773189 100644 --- a/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h @@ -62,7 +62,7 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index); + unsigned Index, Value *Op0, Value *Op1); }; } // end namespace llvm diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 8eec432a4a66..07786ea82738 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -874,7 +874,8 @@ InstructionCost ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, } InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { // Penalize inserting into an D-subregister. We end up with a three times // lower estimated throughput on swift. if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement && @@ -893,7 +894,7 @@ InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, if (ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32) return std::max<InstructionCost>( - BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U); + BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1), 2U); } if (ST->hasMVEIntegerOps() && (Opcode == Instruction::InsertElement || @@ -906,7 +907,7 @@ InstructionCost ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, return LT.first * (ValTy->getScalarType()->isIntegerTy() ? 4 : 1); } - return BaseT::getVectorInstrCost(Opcode, ValTy, Index); + return BaseT::getVectorInstrCost(Opcode, ValTy, Index, Op0, Op1); } InstructionCost ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index db96c3da54cf..6b1e6444c516 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -240,8 +240,8 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index 779577816fb9..6089c865cedf 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -329,7 +329,8 @@ InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, } InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType() : Val; if (Opcode == Instruction::InsertElement) { @@ -338,7 +339,8 @@ InstructionCost HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (ElemTy->isIntegerTy(32)) return Cost; // If it's not a 32-bit value, there will need to be an extract. - return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index); + return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index, + Op0, Op1); } if (Opcode == Instruction::ExtractElement) diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 49d9520b8323..d41299ff6413 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -154,8 +154,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I = nullptr) { diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 3b952f11be34..328a70ec43f6 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -675,7 +675,8 @@ InstructionCost PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { assert(Val->isVectorTy() && "This must be a vector type"); int ISD = TLI->InstructionOpcodeToISD(Opcode); @@ -685,7 +686,8 @@ InstructionCost PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (!CostFactor.isValid()) return InstructionCost::getMax(); - InstructionCost Cost = BaseT::getVectorInstrCost(Opcode, Val, Index); + InstructionCost Cost = + BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); Cost *= CostFactor; if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { @@ -827,7 +829,8 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, if (Src->isVectorTy() && Opcode == Instruction::Store) for (int i = 0, e = cast<FixedVectorType>(Src)->getNumElements(); i < e; ++i) - Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i); + Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i, nullptr, + nullptr); return Cost; } diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h index 9db903baf407..810a7d0d62ef 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -126,8 +126,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 02ce1b135f7f..ed8af25998b0 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1216,12 +1216,13 @@ InstructionCost RISCVTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { assert(Val->isVectorTy() && "This must be a vector type"); if (Opcode != Instruction::ExtractElement && Opcode != Instruction::InsertElement) - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // Legalize the type. std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Val); @@ -1235,7 +1236,7 @@ InstructionCost RISCVTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return LT.first; if (!isTypeLegal(Val)) - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // In RVV, we could use vslidedown + vmv.x.s to extract element from vector // and vslideup + vmv.s.x to insert element to vector. diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 80c7ca3564d7..5df266ba35b5 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -157,8 +157,8 @@ public: const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp index 5d00e56ae347..d6736319a404 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -996,7 +996,8 @@ InstructionCost SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, } InstructionCost SystemZTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { // vlvgp will insert two grs into a vector register, so only count half the // number of instructions. if (Opcode == Instruction::InsertElement && Val->isIntOrIntVectorTy(64)) @@ -1012,7 +1013,7 @@ InstructionCost SystemZTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, return Cost; } - return BaseT::getVectorInstrCost(Opcode, Val, Index); + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); } // Check if a load may be folded as a memory operand in its user. diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h index 5ac3d8149a1d..33c3778d572c 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -107,8 +107,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); bool isFoldableLoad(const LoadInst *Ld, const Instruction *&FoldedValue); InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp index 38464627e742..b94dcd63ad8b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp @@ -82,9 +82,10 @@ InstructionCost WebAssemblyTTIImpl::getArithmeticInstrCost( InstructionCost WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, + Value *Op0, Value *Op1) { InstructionCost Cost = - BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); + BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index, Op0, Op1); // SIMD128's insert/extract currently only take constant indices. if (Index == -1u) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h index 7eed7ef44af7..4f54a762042f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -66,8 +66,8 @@ public: ArrayRef<const Value *> Args = ArrayRef<const Value *>(), const Instruction *CxtI = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); /// @} diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 7d08a1654be7..5b6c7d86cebe 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -4257,7 +4257,8 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index) { + unsigned Index, Value *Op0, + Value *Op1) { static const CostTblEntry SLMCostTbl[] = { { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, @@ -4330,6 +4331,14 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, } } + MVT MScalarTy = LT.second.getScalarType(); + auto IsCheapPInsrPExtrInsertPS = [&]() { + return (MScalarTy == MVT::i16 && ST->hasSSE2()) || + (MScalarTy.isInteger() && ST->hasSSE41()) || + (MScalarTy == MVT::f32 && ST->hasSSE41() && + Opcode == Instruction::InsertElement); + }; + if (Index == 0) { // Floating point scalars are already located in index #0. // Many insertions to #0 can fold away for scalar fp-ops, so let's assume @@ -4337,6 +4346,20 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (ScalarType->isFloatingPointTy()) return RegisterFileMoveCost; + if (Opcode == Instruction::InsertElement && + isa_and_nonnull<UndefValue>(Op0)) { + // Consider the gather cost to be cheap. + if (isa_and_nonnull<LoadInst>(Op1)) + return RegisterFileMoveCost; + if (!IsCheapPInsrPExtrInsertPS()) { + // mov constant-to-GPR + movd/movq GPR -> XMM. + if (isa_and_nonnull<Constant>(Op1) && Op1->getType()->isIntegerTy()) + return 2 + RegisterFileMoveCost; + // Assume movd/movq GPR -> XMM is relatively cheap on all targets. + return 1 + RegisterFileMoveCost; + } + } + // Assume movd/movq XMM -> GPR is relatively cheap on all targets. if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) return 1 + RegisterFileMoveCost; @@ -4344,19 +4367,13 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, int ISD = TLI->InstructionOpcodeToISD(Opcode); assert(ISD && "Unexpected vector opcode"); - MVT MScalarTy = LT.second.getScalarType(); if (ST->useSLMArithCosts()) if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) return Entry->Cost + RegisterFileMoveCost; // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. - if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || - (MScalarTy.isInteger() && ST->hasSSE41())) - return 1 + RegisterFileMoveCost; - // Assume insertps is relatively cheap on all targets. - if (MScalarTy == MVT::f32 && ST->hasSSE41() && - Opcode == Instruction::InsertElement) + if (IsCheapPInsrPExtrInsertPS()) return 1 + RegisterFileMoveCost; // For extractions we just need to shuffle the element to index 0, which @@ -4383,7 +4400,8 @@ InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) RegisterFileMoveCost += 1; - return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; + return BaseT::getVectorInstrCost(Opcode, Val, Index, Op0, Op1) + + RegisterFileMoveCost; } InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, @@ -5155,7 +5173,8 @@ X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, } // Add the final extract element to the cost. - return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, @@ -5455,7 +5474,8 @@ X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, } // Add the final extract element to the cost. - return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); + return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0, + nullptr, nullptr); } /// Calculate the cost of materializing a 64-bit value. This helper diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 666789e160dc..c189e503f4e8 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -147,8 +147,8 @@ public: TTI::TargetCostKind CostKind, const Instruction *I = nullptr); using BaseT::getVectorInstrCost; - InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, - unsigned Index); + InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index, + Value *Op0, Value *Op1); InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract); diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index e1b52aa2f80e..8ca422cfab9f 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -6745,9 +6745,24 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, // broadcast. assert(VecTy == FinalVecTy && "No reused scalars expected for broadcast."); - return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy, - /*Mask=*/std::nullopt, CostKind, /*Index=*/0, - /*SubTp=*/nullptr, /*Args=*/VL[0]); + const auto *It = + find_if(VL, [](Value *V) { return !isa<UndefValue>(V); }); + // If all values are undefs - consider cost free. + if (It == VL.end()) + return TTI::TCC_Free; + // Add broadcast for non-identity shuffle only. + bool NeedShuffle = + VL.front() != *It || !all_of(VL.drop_front(), UndefValue::classof); + InstructionCost InsertCost = + TTI->getVectorInstrCost(Instruction::InsertElement, VecTy, + /*Index=*/0, PoisonValue::get(VecTy), *It); + return InsertCost + (NeedShuffle + ? TTI->getShuffleCost( + TargetTransformInfo::SK_Broadcast, VecTy, + /*Mask=*/std::nullopt, CostKind, + /*Index=*/0, + /*SubTp=*/nullptr, /*Args=*/VL[0]) + : TTI::TCC_Free); } InstructionCost ReuseShuffleCost = 0; if (NeedToShuffleReuses) diff --git a/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll index 3e0f4c11aadf..1e96f97f16e9 100644 --- a/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll @@ -20,7 +20,7 @@ vector.body: ; preds = %vector.body, %vecto %5 = extractelement <2 x i64> %2, i32 1 %6 = getelementptr inbounds i32, ptr %A, i64 %5 %7 = load i32, ptr %4, align 4 - ;CHECK: cost of 1 {{.*}} insert + ;CHECK: cost of 0 {{.*}} insert %8 = insertelement <2 x i32> poison, i32 %7, i32 0 %9 = load i32, ptr %6, align 4 ;CHECK: cost of 1 {{.*}} insert diff --git a/llvm/test/Analysis/CostModel/X86/loop_v2.ll b/llvm/test/Analysis/CostModel/X86/loop_v2.ll index a9cbaaf2fd63..8f67b365ca9b 100644 --- a/llvm/test/Analysis/CostModel/X86/loop_v2.ll +++ b/llvm/test/Analysis/CostModel/X86/loop_v2.ll @@ -20,7 +20,7 @@ vector.body: ; preds = %vector.body, %vecto %5 = extractelement <2 x i64> %2, i32 1 %6 = getelementptr inbounds i32, ptr %A, i64 %5 %7 = load i32, ptr %4, align 4 - ;CHECK: cost of 1 {{.*}} insert + ;CHECK: cost of 0 {{.*}} insert %8 = insertelement <2 x i32> undef, i32 %7, i32 0 %9 = load i32, ptr %6, align 4 ;CHECK: cost of 1 {{.*}} insert diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll index 381e5b630812..897344d622d0 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll @@ -1907,7 +1907,7 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask2' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> poison, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind @@ -1966,7 +1966,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) { ; SSE2-LABEL: 'test_scatter_16i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> poison, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> poison, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll index 2fa41968e807..5f22b2e39f94 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll @@ -1907,7 +1907,7 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask2' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind @@ -1966,7 +1966,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) { ; SSE2-LABEL: 'test_scatter_16i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x ptr> undef, ptr %base, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> diff --git a/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll index 2296b3d5b0c4..e6a4de688186 100644 --- a/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll +++ b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll @@ -382,58 +382,58 @@ define i32 @insert_i64(i32 %arg) { define i32 @insert_i32(i32 %arg) { ; SSE2-LABEL: 'insert_i32' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SSE3-LABEL: 'insert_i32' ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; SSSE3-LABEL: 'insert_i32' ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3 -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3 -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; @@ -664,100 +664,100 @@ define i32 @insert_i16(i32 %arg) { define i32 @insert_i8(i32 %arg) { ; SSE2-LABEL: 'insert_i8' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31 ; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31 -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32 -; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32 +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48 ; SSE2-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63 </cut>

2 years, 8 months

1
0
0 0

[ACTIVITY] Report for week #2

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Fixed a regression found when preparing the new patches. Rebased on the current mainline branch and continued preparing patches for upstream submission. # Misc - Found a minor problem with a script in upstream GDB. Submitted and committed a quick patch¹ to fix it. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20230111174501.3699871-1-thiago.ba…

2 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 13 Jan

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - another round of patch review and a pull request * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - Made some useful progress with the FEAT_FGT implementation -- PMM

2 years, 8 months

1
0
0 0

[ACTIVITY] week ending 8 Jan 2023

by Richard Henderson

* A couple of attempts at minimizing arm per-cpu init work. I've posted a short/medium-term solution for the lookup issue, so that we can re-apply Alex's CPUState unrealize patch. * TCG patch queue flushed, including call abi reorg. - Rebase TCGv_i128 patch set - Rebase goto_tb race condition patch set r~

2 years, 8 months

1
0
0 0

[ACTIVITY] week ending Jan. 8 2023

by Alex Bennée

Project Stratos =============== vhost-device maintainer effort ([UM-196]) - a few version bump reviews Plugin register access ([QEMU-495]) =================================== - posted [PATCH v2 00/21] gdbstub: re-organise to for better compilation behaviour Message-Id: <20230105164320.2164095-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] docs: add some details about compilation units to coding style Message-Id: <20230103104758.767266-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: fix handling of HLT semihosting in system mode Message-Id: <20230105114304.2017493-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] testing: probe gdb for supported architectures ahead of time Message-Id: <20230105181533.2235792-1-alex.bennee(a)linaro.org> - posted [PATCH v2] scripts/ci: update gitlab-runner playbook to use latest runner Message-Id: <20230106152338.2599827-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [5/5] ======================= [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH] semihosting: Write back semihosting data before completion callback Message-Id: <20221012014822.1242170-1-keithp(a)keithp.com> [PATCH v2] semihosting: add O_BINARY flag in host_open for NT compatibility Message-Id: <20230106102018.20520-1-eiakovlev(a)linux.microsoft.com> [PATCH] linux-user: fix bug about incorrect base addresss of idt and gdt on i386 and x86_64 Message-Id: <75da8346.1fd34.1856e0d08ef.Coremail.fanwj(a)mail.ustc.edu.cn> [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> Other ===== - bit of travel forecasting Current Review Queue ==================== TODO [RFC PATCH 00/40] Toward class init of cpu features Message-Id: <20230103181646.55711-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [RFC PATCH v6] virtio-video: Add virtio video device specification Message-Id: <20221208072325.2259940-1-acourbot(a)chromium.org> =================================================================================================================================== TODO [RFC PATCH kvmtool v1 00/32] Add support for restricted guest memory in kvmtool Message-Id: <20221202174417.1310826-1-tabba(a)google.com> =========================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 6 Jan

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] - Pretty much entirely trying to catch up with the code review backlog that had built up over the holidays. Got it down from 35 items to 7... Absences: * NB: I work a 4 day week, excluding Wednesdays * Apr 26 -- 28 : Linaro Connect (London) In office (provisional; let me know if you have preferences!): * week of the 9 Jan -- PMM

2 years, 8 months

1
0
0 0

[ACTIVITY] Report for week #52

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Identified a regression on systems that do not support SVE. Debugged it and now working on a fix. -- Thiago

2 years, 8 months

1
0
0 0

[ACTIVITY] Report for week #51

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished implementing the new approach of sending new XML target descriptions through the wire. - Fixed a couple of minor regressions I introduced and rebased the code on the current main branch. - Now preparing the patches for submitting upstream. # Community participation - Reviewed mailing list patch “[PATCH] [AArch64] Enable pointer authentication support for aarch64 bare metal/kernel mode addresses”. -- Thiago

2 years, 8 months

1
0
0 0

[ACTIVITY] week ending Dec. 25 2022

by Alex Bennée

Project Stratos =============== - started reviewing [PATCH v9 0/8] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221025151344.3784230-1-chao.p.peng(a)linux.intel.com> - trying to assess if user-space facing solution for memory sharing - writing up a [proposal for an API] [proposal for an API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> vhost-device maintainer effort ([UM-196]) - debugged regression in virtio-vsock and QEMU - should have some error message patches to post - QEMU 7.2 shipped with stubs for virtio-gpio and virtio-i2c [UM-196] <https://linaro.atlassian.net/browse/UM-196> Single Binary ([QEMU-487]) ========================== - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> Plugin register access ([QEMU-495]) =================================== - While experimenting with [the register API] ran into issues integrating to gdbstub - started a [re-factor] to make the process less painful - posted [PATCH v1 00/10] split user and system code in gdbstub Message-Id: <20221216112206.3171578-1-alex.bennee(a)linaro.org> [QEMU-495] <https://linaro.atlassian.net/browse/QEMU-495> [the register API] <https://github.com/stsquad/qemu/tree/introspection/registers> [re-factor] <https://github.com/stsquad/qemu/tree/gdbstub/next> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 0/6] testing updates Message-Id: <20221221144019.2149905-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] gitdm metadata updates Message-Id: <20221219121914.851488-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [5/5] ======================= [QEMU][PATCH v2 00/11] Introduce xenpv machine for arm architecture Message-Id: <20221202030003.11441-1-vikram.garhwal(a)amd.com> [PATCH] configure: Fix check-tcg not executing any tests Message-Id: <20221207082309.9966-1-quic_mthiyaga(a)quicinc.com> [PATCH v4 00/27] tcg misc patches Message-Id: <20221213212541.1820840-1-richard.henderson(a)linaro.org> [PATCH v3 0/8] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221209051914.398215-1-richard.henderson(a)linaro.org> [PATCH-for-8.0 0/5] accel/tcg: Restrict page_collection structure to system TB maintainance Message-Id: <20221209093649.43738-1-philmd(a)linaro.org> Absences ======== Christmas holidays - merry Christmas! Current Review Queue ==================== TODO [RFC PATCH v6] virtio-video: Add virtio video device specification Message-Id: <20221208072325.2259940-1-acourbot(a)chromium.org> =================================================================================================================================== TODO [RFC PATCH kvmtool v1 00/32] Add support for restricted guest memory in kvmtool Message-Id: <20221202174417.1310826-1-tabba(a)google.com> =========================================================================================================================================== TODO [PATCH v10 0/9] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221202061347.1070246-1-chao.p.peng(a)linux.intel.com> ==================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 8 months

1
0
0 0

[ACTIVITY] report week ending 20 Dec

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - I'm now back on merging duty for the 8.0 release cycle, so some time spent on pull request processing - Sent pull requests with accumulated arm and reset-refactoring patches from the freeze period - Trying to cut down my code review backlog before the holidays -- PMM

2 years, 9 months

1
0
0 0

[ACTIVITY] Report for week #50

by Thiago Jung Bauermann

# [GNU-767] Support changing SVE vector length in remote debugging - Patches to gdbserver to support changing the SVE vector length: About halfway through implementing the new approach of sending new XML target descriptions through the wire. # Misc - Experimented with using a GDB wrapper to run the testsuite. Came up with a small patch that fixes the tests that fail when using the wrapper. -- Thiago

2 years, 9 months

1
0
0 0

[TCWG CI] Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.

by ci_notify＠linaro.org

Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 7572 # First few build errors in logs: # 00:10:43 drivers/gpu/drm/v3d/v3d_perfmon.c:57:1: internal compiler error: in decompose, at rtl.h:2288 # 00:10:44 make[5]: *** [scripts/Makefile.build:250: drivers/gpu/drm/v3d/v3d_perfmon.o] Error 1 # 00:10:53 make[4]: *** [scripts/Makefile.build:502: drivers/gpu/drm/v3d] Error 2 # 00:13:52 drivers/media/mc/mc-device.c:198:1: internal compiler error: in decompose, at rtl.h:2288 # 00:13:53 make[4]: *** [scripts/Makefile.build:250: drivers/media/mc/mc-device.o] Error 1 # 00:13:57 make[3]: *** [scripts/Makefile.build:502: drivers/media/mc] Error 2 # 00:15:27 make[2]: *** [scripts/Makefile.build:502: drivers/media] Error 2 # 00:17:50 make[3]: *** [scripts/Makefile.build:502: drivers/gpu/drm] Error 2 # 00:17:50 make[2]: *** [scripts/Makefile.build:502: drivers/gpu] Error 2 # 00:17:50 make[1]: *** [scripts/Makefile.build:502: drivers] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 8625 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-4618-g17ae956c0fa commit for tcwg_kernel: commit 17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 Author: Tamar Christina <tamar.christina(a)arm.com> Date: Mon Dec 12 15:18:56 2022 +0000 AArch64: Support new tbranch optab. This implements the new tbranch optab for AArch64. we cannot emit one big RTL for the final instruction immediately. The reason that all comparisons in the AArch64 backend expand to separate CC compares, and separate testing of the operands is for ifcvt. The separate CC compare is needed so ifcvt can produce csel, cset etc from the compares. Unlike say combine, ifcvt can not do recog on a parallel with a clobber. Should we emit the instruction directly then ifcvt will not be able to say, make a csel, because we have no patterns which handle zero_extract and compare. (unlike combine ifcvt cannot transform the extract into an AND). While you could provide various patterns for this (and I did try) you end up with broken patterns because you can't add the clobber to the CC register. If you do, ifcvt recog fails. i.e. int f1 (int x) { if (x & 1) return 1; return x; } We lose csel here. Secondly the reason the compare with an explicit CC mode is needed is so that ifcvt can transform the operation into a version that doesn't require the flags to be set. But it only does so if it know the explicit usage of the CC reg. For instance int foo (int a, int b) { return ((a & (1 << 25)) ? 5 : 4); } Doesn't require a comparison, the optimal form is: foo(int, int): ubfx x0, x0, 25, 1 add w0, w0, 4 ret and no compare is actually needed. If you represent the instruction using an ANDS instead of a zero_extract then you get close, but you end up with an ands followed by an add, which is a slower operation. gcc/ChangeLog: * config/aarch64/aarch64.md (*tb<optab><mode>1): Rename to... (*tb<optab><ALLI:mode><GPI:mode>1): ... this. (tbranch_<code><mode>4): New. * config/aarch64/iterators.md(ZEROM, zerom): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/tbz_1.c: New test. * gnu-master-aarch64-mainline-defconfig ** Failure after basepoints/gcc-13-4618-g17ae956c0fa: AArch64: Support new tbranch optab.: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… Reproduce current build: <cut> mkdir -p investigate-gcc-17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 cd investigate-gcc-17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-mainline… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 17ae956c0fa6baac3d22764019d5dd5ebf5c2b11 Author: Tamar Christina <tamar.christina(a)arm.com> Date: Mon Dec 12 15:18:56 2022 +0000 AArch64: Support new tbranch optab. This implements the new tbranch optab for AArch64. we cannot emit one big RTL for the final instruction immediately. The reason that all comparisons in the AArch64 backend expand to separate CC compares, and separate testing of the operands is for ifcvt. The separate CC compare is needed so ifcvt can produce csel, cset etc from the compares. Unlike say combine, ifcvt can not do recog on a parallel with a clobber. Should we emit the instruction directly then ifcvt will not be able to say, make a csel, because we have no patterns which handle zero_extract and compare. (unlike combine ifcvt cannot transform the extract into an AND). While you could provide various patterns for this (and I did try) you end up with broken patterns because you can't add the clobber to the CC register. If you do, ifcvt recog fails. i.e. int f1 (int x) { if (x & 1) return 1; return x; } We lose csel here. Secondly the reason the compare with an explicit CC mode is needed is so that ifcvt can transform the operation into a version that doesn't require the flags to be set. But it only does so if it know the explicit usage of the CC reg. For instance int foo (int a, int b) { return ((a & (1 << 25)) ? 5 : 4); } Doesn't require a comparison, the optimal form is: foo(int, int): ubfx x0, x0, 25, 1 add w0, w0, 4 ret and no compare is actually needed. If you represent the instruction using an ANDS instead of a zero_extract then you get close, but you end up with an ands followed by an add, which is a slower operation. gcc/ChangeLog: * config/aarch64/aarch64.md (*tb<optab><mode>1): Rename to... (*tb<optab><ALLI:mode><GPI:mode>1): ... this. (tbranch_<code><mode>4): New. * config/aarch64/iterators.md(ZEROM, zerom): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/tbz_1.c: New test. --- gcc/config/aarch64/aarch64.md | 33 ++++++++--- gcc/config/aarch64/iterators.md | 2 + gcc/testsuite/gcc.target/aarch64/tbz_1.c | 95 ++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 8 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 896b6a8ac79..d749c98eef6 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -947,12 +947,29 @@ (const_int 1)))] ) -(define_insn "*tb<optab><mode>1" +(define_expand "tbranch_<code><mode>3" [(set (pc) (if_then_else - (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r") - (const_int 1) - (match_operand 1 - "aarch64_simd_shift_imm_<mode>" "n")) + (EQL (match_operand:ALLI 0 "register_operand") + (match_operand 1 "aarch64_simd_shift_imm_<mode>")) + (label_ref (match_operand 2 "")) + (pc)))] + "" +{ + rtx bitvalue = gen_reg_rtx (<ZEROM>mode); + rtx reg = gen_lowpart (<ZEROM>mode, operands[0]); + rtx val = GEN_INT (1UL << UINTVAL (operands[1])); + emit_insn (gen_and<zerom>3 (bitvalue, reg, val)); + operands[1] = const0_rtx; + operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue, + operands[1]); +}) + +(define_insn "*tb<optab><ALLI:mode><GPI:mode>1" + [(set (pc) (if_then_else + (EQL (zero_extract:GPI (match_operand:ALLI 0 "register_operand" "r") + (const_int 1) + (match_operand 1 + "aarch64_simd_shift_imm_<ALLI:mode>" "n")) (const_int 0)) (label_ref (match_operand 2 "" "")) (pc))) @@ -963,15 +980,15 @@ { if (get_attr_far_branch (insn) == 1) return aarch64_gen_far_branch (operands, 2, "Ltb", - "<inv_tb>\\t%<w>0, %1, "); + "<inv_tb>\\t%<ALLI:w>0, %1, "); else { operands[1] = GEN_INT (HOST_WIDE_INT_1U << UINTVAL (operands[1])); - return "tst\t%<w>0, %1\;<bcond>\t%l2"; + return "tst\t%<ALLI:w>0, %1\;<bcond>\t%l2"; } } else - return "<tbz>\t%<w>0, %1, %l2"; + return "<tbz>\t%<ALLI:w>0, %1, %l2"; } [(set_attr "type" "branch") (set (attr "length") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d10cf93572e..a521dbde1ec 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1107,6 +1107,8 @@ ;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) +(define_mode_attr ZEROM [(QI "SI") (HI "SI") (SI "SI") (DI "DI")]) +(define_mode_attr zerom [(QI "si") (HI "si") (SI "si") (DI "di")]) ;; Give the ordinal of the MSB in the mode (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") diff --git a/gcc/testsuite/gcc.target/aarch64/tbz_1.c b/gcc/testsuite/gcc.target/aarch64/tbz_1.c new file mode 100644 index 00000000000..39deb58e278 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tbz_1.c @@ -0,0 +1,95 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -std=c99 -fno-unwind-tables -fno-asynchronous-unwind-tables" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#include <stdbool.h> + +void h(void); + +/* +** g1: +** tbnz w[0-9]+, #?0, .L([0-9]+) +** ret +** ... +*/ +void g1(bool x) +{ + if (__builtin_expect (x, 0)) + h (); +} + +/* +** g2: +** tbz w[0-9]+, #?0, .L([0-9]+) +** b h +** ... +*/ +void g2(bool x) +{ + if (__builtin_expect (x, 1)) + h (); +} + +/* +** g3_ge: +** tbnz w[0-9]+, #?31, .L[0-9]+ +** b h +** ... +*/ +void g3_ge(int x) +{ + if (__builtin_expect (x >= 0, 1)) + h (); +} + +/* +** g3_gt: +** cmp w[0-9]+, 0 +** ble .L[0-9]+ +** b h +** ... +*/ +void g3_gt(int x) +{ + if (__builtin_expect (x > 0, 1)) + h (); +} + +/* +** g3_lt: +** tbz w[0-9]+, #?31, .L[0-9]+ +** b h +** ... +*/ +void g3_lt(int x) +{ + if (__builtin_expect (x < 0, 1)) + h (); +} + +/* +** g3_le: +** cmp w[0-9]+, 0 +** bgt .L[0-9]+ +** b h +** ... +*/ +void g3_le(int x) +{ + if (__builtin_expect (x <= 0, 1)) + h (); +} + +/* +** g5: +** mov w[0-9]+, 65279 +** tst w[0-9]+, w[0-9]+ +** beq .L[0-9]+ +** b h +** ... +*/ +void g5(int x) +{ + if (__builtin_expect (x & 0xfeff, 1)) + h (); +} </cut>

2 years, 9 months

1
0
0 0

[ACTIVITY] Report for week #49

by Thiago Jung Bauermann

# [GNU-767] Support changing SVE vector length in remote debugging - Patches to gdbserver to support changing the SVE vector length: There was an upstream discussion about whether changing the implementation from relying on expedited registers to relying on sending target descriptions over the wire was a better approach. Simon Marchi detailed his idea on how to do that and it does seem better. - Started implementing Simon's approach of sending target descriptions over the wire for each thread. # Misc - Sent and later committed a couple of patches¹ fixing whitespace issues in a Python script that generates a GDB source file. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221202192200.405379-1-thiago.bau…

2 years, 9 months

1
0
0 0

[ACTIVITY] Report for week #48

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - v2 of the gdbserver patches to support changing the SVE vector length was quickly reviewed by both Luis and Simon Marchi. I applied their review suggestions and I'm now working on fixing a bug with multi-threaded programs that they spotted. - Submitted a couple of small patches¹ fixing tab vs spaces issues in the gdbarch.py script that generates some source code in GDB. # Misc - Fixed problem in the tcwg-dev/start.sh script where asking docker to expose /dev/kvm to a dev container on a host which doesn't have KVM support causes docker to error out (reported by David Spickett). Sent Gerrit change request “42669: tcwg-dev: Add heuristic to check for KVM support on the host” to fix it. David reviewed and merged it. Thanks! -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221202192200.405379-1-thiago.bau…

2 years, 9 months

1
0
0 0

[ACTIVITY] Report for week #47

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Worked on v2 of the gdbserver patches improving SVE support. Found a couple of simplifications that could be made to the code. Rebased on current master branch and finished regression testing and patch preparation. Wrote the cover letter. - Finally posted the patch series upstream¹. -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/20221126020452.1686509-1-thiago.ba…

2 years, 9 months

1
0
0 0

[ACTIVITY] report week ending 25 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - More conversions of devices to 3-phase reset in pursuit of the interim goal of getting rid of device_class_set_parent_reset() - Investigated a regression in a TF-A workload: this was due to recent pagetable walk refactoring breaking debug accesses. - code review, etc; mostly this has been of for-8.0 material, as (other than the above mentioned ptw regression) there haven't been many release-worthy issues this freeze cycle. -- PMM

2 years, 9 months

1
0
0 0

[TCWG CI] 403.gcc failed to run after working-3971-g5f7f484ee54e: [AArch64] Add GPR rr instructions to isAssociativeAndCommutative

by Maxim Kuvyrkov

Hi David, Our CI flagged your commit; it seems it miscompiles 403.gcc from SPEC CPU2006 at -O3 -flto for aarch64-linux-gnu. Would you please investigate? Let me know if you need any assistance in reproducing this. Thanks! === After working-3971-g5f7f484ee54e commit 5f7f484ee54ebbf702ee4c5fe9852502dc237121 Author: David Green <david.green(a)arm.com> [AArch64] Add GPR rr instructions to isAssociativeAndCommutative the following benchmarks slowed down by more than 3%: - 403.gcc failed to run Configuration: - Benchmark: SPEC CPU2006 - Toolchain: Clang + Glibc + LLVM Linker - Version: all components were built from their tip of trunk - Target: aarch64-linux-gnu - Compiler flags: -O3 -flto - Hardware: NVidia TX1 4x Cortex-A57 -- Maxim Kuvyrkov https://www.linaro.org

2 years, 9 months

2
2
0 0

[ACTIVITY] Report for week #46

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Working on v2 of the gdbserver patches improving SVE support. Found and fixed a memory leak in my code while preparing patches for upstream submission. Continuing preparing the patches. # [GNU-796] Stabilise GDB testsuite results in the CI - Analysed failures of “fast_check_gdb” CI jobs over the weekend. They were caused by unrelated build issues in GCC and libstdc++. -- Thiago

2 years, 10 months

1
0
0 0

[ACTIVITY] week ending Nov. 20 2022

by Alex Bennée

Project Stratos =============== - finished [blog post for virtio-camera] - now live [on web site] - did a review of [virtio-loopback] - started reviewing [PATCH v9 0/8] KVM: mm: fd-based approach for supporting KVM Message-Id: <20221025151344.3784230-1-chao.p.peng(a)linux.intel.com> - trying to assess if user-space facing solution for memory sharing [blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> [on web site] <https://www.linaro.org/blog/the-challenges-of-abstracting-virtio/> [virtio-loopback] <https://git.virtualopensystems.com/virtio-loopback> vhost-device maintainer effort ([UM-196]) - debugged regression in virtio-vsock and QEMU - should have some error message patches to post [UM-196] <https://linaro.atlassian.net/browse/UM-196> Single Binary ([QEMU-487]) ========================== - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> - posted [PULL for 7.2 00/10] testing and doc updates Message-Id: <20221115133439.2348929-1-alex.bennee(a)linaro.org> - did a bunch of follow-up testing to shake out other console bugs - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> - posted [PATCH for 7.2? v1 0/2] Arm GICv2 patches Message-Id: <20221115134048.2352715-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - hackbox2 upgrade follow-up - health check content Completed Reviews [1/1] ======================= [PATCH] ci: replace x86_64 macos-11 with aarch64 macos-12 Message-Id: <20221116175023.80627-1-berrange(a)redhat.com> Absences ======== Current Review Queue ==================== TODO [PATCH v6 00/21] Drivers for gunyah hypervisor Message-Id: <20221026185846.3983888-1-quic_eberman(a)quicinc.com> ================================================================================================================== TODO [PATCH v2 0/1] tcg: add perfmap and jitdump Message-Id: <20221114161321.3364875-1-iii(a)linux.ibm.com> ======================================================================================================== TODO [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Message-Id: <20221111074101.2069454-1-richard.henderson(a)linaro.org> ===================================================================================================================================== -- Alex Bennée

2 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 18 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- the usual release cycle work. Looks relatively quiet this time around. -- taking the opportunity to try to catch up on some of the for-8.0 code review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] -- started thinking about how to implement FEAT_FGT. Looking at the code where this ought to go, I found a minor bug with how we implement the existing HSTR_EL2 traps, and a case where we trap AArch32 ATS12NSO* with the wrong syndrome. -- PMM

2 years, 10 months

1
0
0 0

[ACTIVITY] Report for week #45

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Working on v2 of the gdbserver patches improving SVE support. Tested new code for regressions in different systems and configurations and found none. Preparing new version of the patches for upstream submission. Will likely post them early next week. -- Thiago

2 years, 10 months

1
0
0 0

[ACTIVITY] week ending Nov. 13 2022

by Alex Bennée

Project Stratos =============== - finished [blog post for virtio-camera] - did a review of [virtio-loopback] [blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> [virtio-loopback] <https://git.virtualopensystems.com/virtio-loopback> vhost-device maintainer effort ([UM-196]) - review work Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing - posted [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Message-Id: <20221111182535.64844-1-alex.bennee(a)linaro.org> [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.2-rc1 v2 00/12] testing, docs, plugins, arm pre-PR Message-Id: <20221111145529.4020801-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - hackbox2 upgrade follow-up - health check content Completed Reviews [7/7] ======================= [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-1-richard.henderson(a)linaro.org> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH] Run docker probe only if docker or podman are available Message-Id: <20221030083510.310584-1-sw(a)weilnetz.de> [PULL 3/3] linux-test (tests/tcg/multiarch/linux-test.c) add check Message-Id: <1626902375-7002-4-git-send-email-tsimpson(a)quicinc.com> [PATCH v5 00/18] tests/qtest: Enable running qtest on Windows Message-Id: <20221006151927.2079583-3-bmeng.cn(a)gmail.com> [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> [PATCH RFC 0/1] tcg: add perfmap and jitdump Message-Id: <20221012051846.1432050-1-iii(a)linux.ibm.com> Absences ======== Current Review Queue ==================== TODO [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Message-Id: <20221111074101.2069454-1-richard.henderson(a)linaro.org> ===================================================================================================================================== TODO [PATCH v3 0/7] memory: prevent dma-reentracy issues Message-Id: <20221028191648.964076-1-alxndr(a)bu.edu> =========================================================================================================== TODO [QEMU][PATCH v2 0/5] Introduce Xilinx Versal CANFD Message-Id: <20221022054746.28217-1-vikram.garhwal(a)amd.com> ================================================================================================================== -- Alex Bennée

2 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 10 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- identified another piece of the reset mechanics that can be tractably cleaned up: I think we should be able to get everything (effectively) moved over to the 3-phase reset system -- sent out various for-8.0 patchsets that convert devices that were using device_class_set_parent_reset(), since getting rid of that function is step 1 of that cleanup -- code review etc -- PMM

2 years, 10 months

1
0
0 0

[ACTIVITY] Report for week #44

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Confirmed that gdbserver doesn't send a new XML target description over the wire when the vector length changes, so there's no impact of these patches on the amount of remote protocol traffic, which was a concern for GDB maintainers. - Started doing some up code cleanup and regression tests to prepare for submitting v2 of the patches. # [GNU-796] Stabilise GDB testsuite results in the CI - Committed Gerrit change request adding the new CI job¹ to run fast subset of GDB tests, which also has stable results. The list of tests comes from Sourceware's builder project. -- Thiago ¹ https://ci.linaro.org/view/tcwg_gnu_native/job/tcwg_gnu_native_fast_check_g…

2 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 4 Nov

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] -- investigated and thought a bit more about a race condition involving display devices. I know think I understand the problem but the best idea I could come up with for a solution is pretty painful... (Still hoping for feedback on whether I've missed something.) -- collated and sent out a pull request with various bug fixes for rc0 -- sent some more reset-cleanup patches (these will be for 8.0) -- PMM

2 years, 10 months

1
0
0 0

Virt meeting 2022-11-01

by Richard Henderson

Hi guys, I will attempt to join today, but we've been finding that connectivity is dependent on the number of rain drops and/or hail in between here and the mast. So I'm not overly hopeful for later this evening. Status report: - Fixed a failure in my x86 TARGET_TB_PCREL patches, which caused non-booting of some images (in today's tcg PR). - Revised the TCGv_i128 patch set (not yet posted). - Lots of work on accel/tcg/{cputlb,user-exec}.c, to honor atomicity requirements of FEAT_LSE2. Next up: Adding qemu_ld/st helpers and patterns for i128. r~

2 years, 10 months

1
0
0 0

[ACTIVITY] Report for week #43

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. Started checking changes for regressions. -- Thiago

2 years, 10 months

1
0
0 0

[ACTIVITY] report week ending 28 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Cross-checked our boot.c code against the kernel's booting.rst, and sent patch fixing a few EL3 config bits we weren't setting - Sent out the minutes from QEMU Summit * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - Wrote and sent out patches to implement the extra traps required for FEAT_EVT -- PMM

2 years, 10 months

1
0
0 0

[ACTIVITY] Report for week #42

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilise GDB testsuite results in the CI - Reworked and committed Gerrit change request for jenkins-scripts adding a new CI job definition in tcwg_gnu-build.sh. - Also reworked and committed another one to the same script adding a default manifest file if one isn't specified on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Implemented Luis' suggestion of assuming that if ptrace can't read the SVE state, then SVE is disabled (which is what gdbserver does before my patches). It turns out that the only situation where this happens, gdbserver doesn't actually care about the target description. - Started exploring/implementing Luis' idea of having a process-wide target description in addition to the thread-specific one. As Luis suggests, it may simplify the code. -- Thiago

2 years, 11 months

1
0
0 0

[ACTIVITY] week ending Oct. 23 2022

by Alex Bennée

Project Stratos =============== - wrote a [draft blog post for virtio-camera] [draft blog post for virtio-camera] <https://linaro.atlassian.net/jira/core/projects/LBO/board?selectedIssue=LBO…> vhost-device maintainer effort ([UM-196]) - review work [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> Single Binary ([QEMU-487]) ========================== - cleaning up current_cpu in [with mxtxattrs] - stumbled into regressions in the way of testing [QEMU-487] <https://linaro.atlassian.net/browse/QEMU-487> [with mxtxattrs] <https://github.com/stsquad/qemu/tree/memtxattrs/cpuid-v5> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/arm: don't process FCSE translations on physical TLBs Message-Id: <20221021172338.2782240-1-alex.bennee(a)linaro.org> - posted [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: protect execlog's last_exec expansion Message-Id: <20221021164028.2757262-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] contrib/plugins: enable debug on CONFIG_DEBUG_TCG Message-Id: <20221021155146.2729598-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [4/4] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> [PATCH v3 00/26] testing/next (docker, avocado, s390x, MAINTAINERS) Message-Id: <20221020115209.1761864-1-alex.bennee(a)linaro.org> [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits Message-Id: <20221020123506.26363-1-ani(a)anisinha.ca> Other ===== - reviews and appraisals - members operational meeting - QEMU plans Absences ======== Current Review Queue ==================== TODO [PATCH 00/31] tcg: Support for Int128 with helpers Message-Id: <20221020115242.2301066-1-richard.henderson(a)linaro.org> ========================================================================================================================== TODO [PATCH v8 0/9] target/arm: pc-relative translation blocks Message-Id: <20221020030641.2066807-1-richard.henderson(a)linaro.org> ================================================================================================================================= TODO [PATCH v1 00/12] Introduce xenpv machine for arm architecture Message-Id: <20221015050750.4185-1-vikram.garhwal(a)amd.com> ============================================================================================================================ -- Alex Bennée

2 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 21 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Usual code review and patch handling work - Spent a couple of days investigating a long-standing intermittent test case failure booting a kernel on the raspberry pi. This turned out to be caused by two linked bugs: - the test framework unhelpfully disconnects immediately from the guest serial console when the test ends, rather than staying connected until the QEMU process exits to capture all the output - QEMU's socket chardev loses data when the remote end closes the connection if the guest UART hasn't read all of it So the test was failing because the guest sometimes only saw the 'h' of the final 'halt' command the test sent... - Investigated and fixed a regression caused by some of last week's reset patches. (Turns out the patch to fix it had been sent back in 2021 but we accidentally dropped it on the floor. Oops.) thanks -- PMM

2 years, 11 months

1
0
0 0

[ACTIVITY] Report for week #41

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued incorporating suggestions from Luis' review of the patches. Working on a few regressions I introduced in the process. # [GNU-796] Stabilise GDB testsuite results in the CI - Started addressing Maxim's comments to my change requests for jenkins-scripts. -- Thiago

2 years, 11 months

1
0
0 0

[ACTIVITY] week ending Oct. 16 2022

by Alex Bennée

Project Stratos =============== - virtio-camera discussion and prep vhost-device maintainer effort ([UM-196]) - more review, vsock merged \o/ [UM-196] <https://linaro.atlassian.net/browse/UM-196> [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - more leadership committee work - more member engagement on CCA/RME - posted [PATCH v1 0/4] testing/next hotfix (revert bios build, mingw) Message-Id: <20221011113417.794841-1-alex.bennee(a)linaro.org> - posted [PULL 0/1] testing: revert pc-bios build patch Message-Id: <20221011192858.956078-1-alex.bennee(a)linaro.org> - posted [PATCH v2 0/7] testing/next (configure, RUNC, win32|64) Message-Id: <20221013154705.1846261-1-alex.bennee(a)linaro.org> - posted [RFC PATCH 0/4] docs/devel suggestions for discussion Message-Id: <20221012121152.1179051-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [2/2] ======================= [libvirt PATCH] conf: skip resource cache init if sysfs files are missing Message-Id: <20221010164753.1701971-1-berrange(a)redhat.com> [libvirt PATCH v2 0/2] conf: fix handling of missing CPU cache info in sysfs Message-Id: <20221011090621.1712993-1-berrange(a)redhat.com> Other ===== - reviews and appraisals - other admin Absences ======== - day off ill Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== -- Alex Bennée

2 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 14 Oct

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Started looking again at QEMU's rather messy set of reset related APIs. Dug out the half-a-plan I wrote up a long time back and refreshed my memory of what I was hoping we might be able to do. - As an initial step, wrote some patches to get rid of uses of several deprecated reset-related functions so that I only have to think about one set of functions and not two... -- PMM

2 years, 11 months

1
0
0 0

[TCWG CI] Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses

by ci_notify＠linaro.org

Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 624 # First few build errors in logs: # 00:01:42 mm/slub.c:4428:5: error: virtual use of statement not up to date # 00:01:42 mm/slub.c:4428:5: internal compiler error: verify_ssa failed # 00:01:43 make[2]: *** [scripts/Makefile.build:250: mm/slub.o] Error 1 # 00:01:44 make[1]: *** [scripts/Makefile.build:500: mm] Error 2 # 00:01:56 make: *** [Makefile:1990: .] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 629 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-3219-g25413fdb2ac commit for tcwg_kernel: commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. * gnu-master-aarch64-next-allnoconfig ** Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Reproduce current build: <cut> mkdir -p investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 cd investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. --- gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c | 40 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c | 44 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c | 45 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c | 39 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c | 42 +++ gcc/tree-if-conv.cc | 313 ++++++++++++++++++-- gcc/tree-vect-data-refs.cc | 3 +- gcc/tree-vect-patterns.cc | 330 +++++++++++++++++++++- 14 files changed, 1079 insertions(+), 31 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c new file mode 100644 index 00000000000..01cf34fb444 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c @@ -0,0 +1,40 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define ELT0 {0} +#define ELT1 {1} +#define ELT2 {2} +#define ELT3 {3} +#define N 32 +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].i; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c new file mode 100644 index 00000000000..1a4a1579c14 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 0} +#define ELT1 {0x7FFFFFFFUL, 1} +#define ELT2 {0x7FFFFFFFUL, 2} +#define ELT3 {0x7FFFFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c new file mode 100644 index 00000000000..849f4a017e1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c @@ -0,0 +1,44 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" +#include <stdbool.h> + +extern void abort(void); + +typedef struct { + int c; + int b; + bool a : 1; + int d : 31; +} struct_t; + +#define N 16 +#define ELT_F { 0xFFFFFFFF, 0xFFFFFFFF, 0, 0x7FFFFFFF } +#define ELT_T { 0xFFFFFFFF, 0xFFFFFFFF, 1, 0x7FFFFFFF } + +struct_t vect_false[N] = { ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +struct_t vect_true[N] = { ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +int main (void) +{ + unsigned ret = 0; + for (unsigned i = 0; i < N; i++) + { + ret |= vect_false[i].a; + } + if (ret) + abort (); + + for (unsigned i = 0; i < N; i++) + { + ret |= vect_true[i].a; + } + if (!ret) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c new file mode 100644 index 00000000000..5bc9c412e96 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c @@ -0,0 +1,45 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 3, 0} +#define ELT1 {0x7FFFFFFFUL, 3, 1} +#define ELT2 {0x7FFFFFFFUL, 3, 2} +#define ELT3 {0x7FFFFFFFUL, 3, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c new file mode 100644 index 00000000000..1dc24d3eded --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 9; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c new file mode 100644 index 00000000000..7d24c299758 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 8; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c new file mode 100644 index 00000000000..19683d277b1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c @@ -0,0 +1,39 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].i = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].i != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c new file mode 100644 index 00000000000..d550dd35ab7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c new file mode 100644 index 00000000000..3303d2610ff --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c new file mode 100644 index 00000000000..fae6ea3557d --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 9; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c new file mode 100644 index 00000000000..99360c2967b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 8; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc index bac29fb5574..e468a4659fa 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -91,6 +91,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-pass.h" #include "ssa.h" #include "expmed.h" +#include "expr.h" #include "optabs-query.h" #include "gimple-pretty-print.h" #include "alias.h" @@ -123,6 +124,9 @@ along with GCC; see the file COPYING3. If not see #include "tree-vectorizer.h" #include "tree-eh.h" +/* For lang_hooks.types.type_for_mode. */ +#include "langhooks.h" + /* Only handle PHIs with no more arguments unless we are asked to by simd pragma. */ #define MAX_PHI_ARG_NUM \ @@ -145,6 +149,12 @@ static bool need_to_rewrite_undefined; before phi_convertible_by_degenerating_args. */ static bool any_complicated_phi; +/* True if we have bitfield accesses we can lower. */ +static bool need_to_lower_bitfields; + +/* True if there is any ifcvting to be done. */ +static bool need_to_ifcvt; + /* Hash for struct innermost_loop_behavior. It depends on the user to free the memory. */ @@ -1411,15 +1421,6 @@ if_convertible_loop_p_1 (class loop *loop, vec<data_reference_p> *refs) calculate_dominance_info (CDI_DOMINATORS); - /* Allow statements that can be handled during if-conversion. */ - ifc_bbs = get_loop_body_in_if_conv_order (loop); - if (!ifc_bbs) - { - if (dump_file && (dump_flags & TDF_DETAILS)) - fprintf (dump_file, "Irreducible loop\n"); - return false; - } - for (i = 0; i < loop->num_nodes; i++) { basic_block bb = ifc_bbs[i]; @@ -2899,18 +2900,22 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) class loop *new_loop; gimple *g; gimple_stmt_iterator gsi; - unsigned int save_length; + unsigned int save_length = 0; g = gimple_build_call_internal (IFN_LOOP_VECTORIZED, 2, build_int_cst (integer_type_node, loop->num), integer_zero_node); gimple_call_set_lhs (g, cond); - /* Save BB->aux around loop_version as that uses the same field. */ - save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; - void **saved_preds = XALLOCAVEC (void *, save_length); - for (unsigned i = 0; i < save_length; i++) - saved_preds[i] = ifc_bbs[i]->aux; + void **saved_preds = NULL; + if (any_complicated_phi || need_to_predicate) + { + /* Save BB->aux around loop_version as that uses the same field. */ + save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; + saved_preds = XALLOCAVEC (void *, save_length); + for (unsigned i = 0; i < save_length; i++) + saved_preds[i] = ifc_bbs[i]->aux; + } initialize_original_copy_tables (); /* At this point we invalidate porfile confistency until IFN_LOOP_VECTORIZED @@ -2922,8 +2927,9 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) profile_probability::always (), true); free_original_copy_tables (); - for (unsigned i = 0; i < save_length; i++) - ifc_bbs[i]->aux = saved_preds[i]; + if (any_complicated_phi || need_to_predicate) + for (unsigned i = 0; i < save_length; i++) + ifc_bbs[i]->aux = saved_preds[i]; if (new_loop == NULL) return NULL; @@ -2999,7 +3005,7 @@ ifcvt_split_critical_edges (class loop *loop, bool aggressive_if_conv) auto_vec<edge> critical_edges; /* Loop is not well formed. */ - if (num <= 2 || loop->inner || !single_exit (loop)) + if (loop->inner) return false; body = get_loop_body (loop); @@ -3260,6 +3266,201 @@ ifcvt_hoist_invariants (class loop *loop, edge pe) free (body); } +/* Returns the DECL_FIELD_BIT_OFFSET of the bitfield accesse in stmt iff its + type mode is not BLKmode. If BITPOS is not NULL it will hold the poly_int64 + value of the DECL_FIELD_BIT_OFFSET of the bitfield access and STRUCT_EXPR, + if not NULL, will hold the tree representing the base struct of this + bitfield. */ + +static tree +get_bitfield_rep (gassign *stmt, bool write, tree *bitpos, + tree *struct_expr) +{ + tree comp_ref = write ? gimple_assign_lhs (stmt) + : gimple_assign_rhs1 (stmt); + + tree field_decl = TREE_OPERAND (comp_ref, 1); + tree rep_decl = DECL_BIT_FIELD_REPRESENTATIVE (field_decl); + + /* Bail out if the representative is BLKmode as we will not be able to + vectorize this. */ + if (TYPE_MODE (TREE_TYPE (rep_decl)) == E_BLKmode) + return NULL_TREE; + + /* Bail out if the DECL_SIZE of the field_decl isn't the same as the BF's + precision. */ + unsigned HOST_WIDE_INT bf_prec + = TYPE_PRECISION (TREE_TYPE (gimple_assign_lhs (stmt))); + if (compare_tree_int (DECL_SIZE (field_decl), bf_prec) != 0) + return NULL_TREE; + + if (struct_expr) + *struct_expr = TREE_OPERAND (comp_ref, 0); + + if (bitpos) + *bitpos + = fold_build2 (MINUS_EXPR, bitsizetype, + DECL_FIELD_BIT_OFFSET (field_decl), + DECL_FIELD_BIT_OFFSET (rep_decl)); + + return rep_decl; + +} + +/* Lowers the bitfield described by DATA. + For a write like: + + struct.bf = _1; + + lower to: + + __ifc_1 = struct.<representative>; + __ifc_2 = BIT_INSERT_EXPR (__ifc_1, _1, bitpos); + struct.<representative> = __ifc_2; + + For a read: + + _1 = struct.bf; + + lower to: + + __ifc_1 = struct.<representative>; + _1 = BIT_FIELD_REF (__ifc_1, bitsize, bitpos); + + where representative is a legal load that contains the bitfield value, + bitsize is the size of the bitfield and bitpos the offset to the start of + the bitfield within the representative. */ + +static void +lower_bitfield (gassign *stmt, bool write) +{ + tree struct_expr; + tree bitpos; + tree rep_decl = get_bitfield_rep (stmt, write, &bitpos, &struct_expr); + tree rep_type = TREE_TYPE (rep_decl); + tree bf_type = TREE_TYPE (gimple_assign_lhs (stmt)); + + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Lowering:\n"); + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + fprintf (dump_file, "to:\n"); + } + + /* REP_COMP_REF is a COMPONENT_REF for the representative. NEW_VAL is it's + defining SSA_NAME. */ + tree rep_comp_ref = build3 (COMPONENT_REF, rep_type, struct_expr, rep_decl, + NULL_TREE); + tree new_val = ifc_temp_var (rep_type, rep_comp_ref, &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + if (write) + { + new_val = ifc_temp_var (rep_type, + build3 (BIT_INSERT_EXPR, rep_type, new_val, + unshare_expr (gimple_assign_rhs1 (stmt)), + bitpos), &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + gimple *new_stmt = gimple_build_assign (unshare_expr (rep_comp_ref), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + else + { + tree bfr = build3 (BIT_FIELD_REF, bf_type, new_val, + build_int_cst (bitsizetype, TYPE_PRECISION (bf_type)), + bitpos); + new_val = ifc_temp_var (bf_type, bfr, &gsi); + + gimple *new_stmt = gimple_build_assign (gimple_assign_lhs (stmt), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + + gsi_remove (&gsi, true); +} + +/* Return TRUE if there are bitfields to lower in this LOOP. Fill TO_LOWER + with data structures representing these bitfields. */ + +static bool +bitfields_to_lower_p (class loop *loop, + vec <gassign *> &reads_to_lower, + vec <gassign *> &writes_to_lower) +{ + gimple_stmt_iterator gsi; + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Analyzing loop %d for bitfields:\n", loop->num); + } + + for (unsigned i = 0; i < loop->num_nodes; ++i) + { + basic_block bb = ifc_bbs[i]; + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) + { + gassign *stmt = dyn_cast<gassign*> (gsi_stmt (gsi)); + if (!stmt) + continue; + + tree op = gimple_assign_lhs (stmt); + bool write = TREE_CODE (op) == COMPONENT_REF; + + if (!write) + op = gimple_assign_rhs1 (stmt); + + if (TREE_CODE (op) != COMPONENT_REF) + continue; + + if (DECL_BIT_FIELD_TYPE (TREE_OPERAND (op, 1))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + + if (!INTEGRAL_TYPE_P (TREE_TYPE (op))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NO OK to lower," + " field type is not Integral.\n"); + return false; + } + + if (!get_bitfield_rep (stmt, write, NULL, NULL)) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NOT OK to lower," + " representative is BLKmode.\n"); + return false; + } + + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\tBitfield OK to lower.\n"); + if (write) + writes_to_lower.safe_push (stmt); + else + reads_to_lower.safe_push (stmt); + } + } + } + return !reads_to_lower.is_empty () || !writes_to_lower.is_empty (); +} + + /* If-convert LOOP when it is legal. For the moment this pass has no profitability analysis. Returns non-zero todo flags when something changed. */ @@ -3270,12 +3471,16 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) unsigned int todo = 0; bool aggressive_if_conv; class loop *rloop; + auto_vec <gassign *, 4> reads_to_lower; + auto_vec <gassign *, 4> writes_to_lower; bitmap exit_bbs; edge pe; again: rloop = NULL; ifc_bbs = NULL; + need_to_lower_bitfields = false; + need_to_ifcvt = false; need_to_predicate = false; need_to_rewrite_undefined = false; any_complicated_phi = false; @@ -3291,16 +3496,42 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) aggressive_if_conv = true; } - if (!ifcvt_split_critical_edges (loop, aggressive_if_conv)) + if (!single_exit (loop)) goto cleanup; - if (!if_convertible_loop_p (loop) - || !dbg_cnt (if_conversion_tree)) + /* If there are more than two BBs in the loop then there is at least one if + to convert. */ + if (loop->num_nodes > 2 + && !ifcvt_split_critical_edges (loop, aggressive_if_conv)) goto cleanup; - if ((need_to_predicate || any_complicated_phi) - && ((!flag_tree_loop_vectorize && !loop->force_vectorize) - || loop->dont_vectorize)) + ifc_bbs = get_loop_body_in_if_conv_order (loop); + if (!ifc_bbs) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "Irreducible loop\n"); + goto cleanup; + } + + if (loop->num_nodes > 2) + { + need_to_ifcvt = true; + + if (!if_convertible_loop_p (loop) || !dbg_cnt (if_conversion_tree)) + goto cleanup; + + if ((need_to_predicate || any_complicated_phi) + && ((!flag_tree_loop_vectorize && !loop->force_vectorize) + || loop->dont_vectorize)) + goto cleanup; + } + + if ((flag_tree_loop_vectorize || loop->force_vectorize) + && !loop->dont_vectorize) + need_to_lower_bitfields = bitfields_to_lower_p (loop, reads_to_lower, + writes_to_lower); + + if (!need_to_ifcvt && !need_to_lower_bitfields) goto cleanup; /* The edge to insert invariant stmts on. */ @@ -3311,7 +3542,8 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) Either version this loop, or if the pattern is right for outer-loop vectorization, version the outer loop. In the latter case we will still if-convert the original inner loop. */ - if (need_to_predicate + if (need_to_lower_bitfields + || need_to_predicate || any_complicated_phi || flag_tree_loop_if_convert != 1) { @@ -3351,10 +3583,31 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) pe = single_pred_edge (gimple_bb (preds->last ())); } - /* Now all statements are if-convertible. Combine all the basic - blocks into one huge basic block doing the if-conversion - on-the-fly. */ - combine_blocks (loop); + if (need_to_lower_bitfields) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "-------------------------\n"); + fprintf (dump_file, "Start lowering bitfields\n"); + } + while (!reads_to_lower.is_empty ()) + lower_bitfield (reads_to_lower.pop (), false); + while (!writes_to_lower.is_empty ()) + lower_bitfield (writes_to_lower.pop (), true); + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Done lowering bitfields\n"); + fprintf (dump_file, "-------------------------\n"); + } + } + if (need_to_ifcvt) + { + /* Now all statements are if-convertible. Combine all the basic + blocks into one huge basic block doing the if-conversion + on-the-fly. */ + combine_blocks (loop); + } </cut>

2 years, 11 months

1
0
0 0

[ACTIVITY] Report for weeks #37, #39 and #40

by Thiago Jung Bauermann

Hello, I haven't sent a report since week #36. For that reason, this report covers three weeks. # [GNU-796] Stabilise GDB testsuite results in the CI - Implemented CI job to run fast GDB tests based on the list from Sourceware's builder. Submitted Gerrit change requests for jenkins-scripts and ci/job/configs. - Posted Gerrit change request for jenkins-scripts with an improvement to tcwg_gnu-build.sh to use a default path for the artifacts file if one isn't given on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Started incorporating suggestions from Luis' review of the patches. # Community participation - Reviewed mailing list patch “[PATCH v3] gdb/arm: Handle lazy FPU register stacking” - Attended GNU Tools Cauldron 2022. -- Thiago

2 years, 11 months

1
0
0 0

[ACTIVITY] week ending Oct. 9 2022

by Alex Bennée

Project Stratos =============== [UM-196] <https://linaro.atlassian.net/browse/UM-196> vhost-device maintainer effort ([UM-196]) - [review of vhost-sock for vhost-device] [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/54] testing, gdbstub, plugin and gitdm updates Message-Id: <20221004130138.2299307-1-alex.bennee(a)linaro.org> - took 3 attempts [PULL v3 00/52] testing, gdbstub, plugin and gitdm updates Message-Id: <20221006105556.3319342-1-alex.bennee(a)linaro.org> - leadership committee work - member engagement on CCA/RME [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH 00/20] Cross compilation changes for 7.2 Message-Id: <20220825222745.38779-13-pbonzini(a)redhat.com> [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Message-Id: <20221004141051.110653-4-richard.henderson(a)linaro.org> [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> Other ===== - reviews and appraisals Absences ======== Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org> =========================================================================================================================================================================== -- Alex Bennée

2 years, 11 months

1
0
0 0

[ACTIVITY] report week ending Oct 7

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - miscellaneous upstream patch review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - sent out patchset implementing FEAT_GTG - sent out patch implementing FEAT_E0PD - code review of RTH's FEAT_HAFDBS patchset -- PMM

2 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 30 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out patch which adds a retry-on-EINTR loop to KVM_CREATE_VM ioctls - wrote up the draft of the minutes for the QEMU Summit for review - more code review and pullrequest collation (notably the Arm v8R support patchset) * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - read up on the remaining unimplemented features under this epic; closed out one we'd already implemented, and wrote up enough detail on the others to be happy with putting them all into the current sprint (they're all small features) - started looking at FEAT_GTG thanks -- PMM

2 years, 11 months

1
0
0 0

[ACTIVITY] week ending Sep. 25 2022

by Alex Bennée

Project Stratos =============== - held poll for next meeting - started planning for virtio-camera/sensor QEMU Upstream Work ([UM-2]) =========================== - posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id: <CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com> - sadly one patch had to be reverted as it exposed another race - posted [PATCH v1 00/10] plugins/next (disas, monitor, docs, execlog) Message-Id: <20220921160801.1490125-6-alex.bennee(a)linaro.org> - posted [PULL 00/30] testing updates (docker, avocado, deprecate 32bit BE MIPS) Message-Id: <20220920171533.1098094-4-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Update docs - mention -d plugin - document features of tests/plugin plugins - clean up command lines to drop builddir KVM Forum ========= - Attended KVM forum, gave a talk, helper with another Completed Reviews [3/3] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> [RFC PATCH v2] gdbstub: only send stop-reply packets when allowed to Message-Id: <ba99db564c3aeb1812bdfbc9116849092334482f.1661362557.git.quic_mathbern(a)quicinc.com> [RFC 0/4] Support interactions between TCG plugins Message-Id: <20220901182734.2987337-1-fasano(a)mit.edu> Absences ======== Current Review Queue ==================== TODO [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [PATCH 00/51] tests/qtest: Enable running qtest on Windows Message-Id: <20220824094029.1634519-1-bmeng.cn(a)gmail.com> ======================================================================================================================== TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org> ======================================================================================================================================= -- Alex Bennée

2 years, 11 months

1
0
0 0

[ACTIVITY] report week ending 23 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - attended KVM Forum - catching up with code review, email, etc... - sent out an Arm pullreq now 7.2 has opened up for development * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - diagnosed a regression caused by the recent FEAT_PMUv3p5 changes and sent out a fix KVM Forum trip highlights: * it was good to be able to meet people face-to-face again after several years * Cloud use of Arm hardware has now got to the point where big cloud companies are working through performance issues and then coming to present about it; e.g. Google did a talk about perf issues during migration on an Ampere Altra setup. The solutions seem to be a mix of "apply the lessons and fixes we already went through with x86" and "architecture fixes coming down the pipe" (in this case FEAT_TLBIRANGE and FEAT_BBM). * lots of Google talks about pKVM (using hypervisor hardware on Android to improve security). In fact lots of Google all over -- apparently they've made a big push to do more upstream kernel work and as a result a large chunk of the kernel KVM commits come from them... * talk from Xilinx (now with AMD) about doing co-simulation of QEMU and RTL -- basically (with the aid of a lot of non-upstream stuff) having QEMU talk to a SystemC environment so you can have eg an emulated ethernet card in FPGA that plugs into a QEMU VM. This kind of thing is a use-case which historically upstream have not really been interested in addressing. * Which brings me to the BoF session on emulation, perhaps the most interesting bit of the conference for me. There was a lot of discussion about whether QEMU might move closer to what I call the "bag of lego bricks" paradigm, where it provides device models and users might be able to configure it at runtime to stitch them together, perhaps adding out-of-tree devices of their own. There is clearly interest in this (eg from attendees from Xilinx and Qualcomm); the sticking point is that from upstream's perspective this seems like "you should do this thing that will benefit us and not you". My take is that whether this goes anywhere will depend on whether those who would like this are prepared to coordinate together to present themselves as a group who are willing to dig in to the necessary upstream refactoring and cleanup that would be a precondition for having something like this be anywhere near supportable, i.e. that they're a group who will come and help rather than merely consume... * There was also a shorter discussion in the BoF about the idea of "heterogenous CPU emulation", eg one QEMU model with both Arm and Microblaze CPUs. This is not conceptually controversial, it's just a lot of work. It seemed like maybe a few folk now care enough to have a go at it. -- PMM

2 years, 11 months

1
0
0 0

[ACTIVITY] Report for week #36

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Made a few last-minute adjustments to the code and fixed a couple of regressions on x86_64-linux. Re-ran regression tests on x86_64-linux and aarch64-linux. Wrote cover letter and descriptions for all the patches. - Finally posted the patch series upstream¹. # [GNU-796] Stabilize GDB testsuite results in the Linaro CI - Started working on this issue. Currently adding a new CI job to run the same small subset of GDB testcases that Sourceware's buildbot runs. This subset runs quickly and has stable results so the job will be a good canary to check that the CI infrastructure is working correctly. -- Thiago ¹https://inbox.sourceware.org/gdb-patches/20220908064151.3959930-1-thiago.b…

3 years

1
0
0 0

[ACTIVITY] Report for week #35

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Cleaned up code for upstream submission, and divided it into patches. A couple of the patches affect other architectures and OSes, so made sure the code builds on as many combinations I can test, and now doing final regression testing on some of them. I'm hoping to finally send the patches upstream early next week. -- Thiago

3 years

1
0
0 0

[ACTIVITY] Report for week #34

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished fixing regressions in my changes to gdbserver for debugging an inferior which changes the SVE length. - Started cleaning up code for upstream submission and dividing it into patches. # Community participation - Reviewed mailing list patches: - [PATCH,v3] [aarch64] Fix removal of non-address bits for PAuth - [PATCH 1/2] gdb: Fix deleted thread when issuing next command - [PATCH 2/2] gdb: Improve the resuming of the stepped thread -- Thiago

3 years

1
0
0 0

[ACTIVITY] report week ending 25 Aug

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] - pretty much just tying up loose ends and doing other miscellaneous bits and pieces * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - respin, resend of PMUv3p5 series -- PMM

3 years

1
0
0 0

[ACTIVITY] Report for week #33

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - v2 of the patches fixing a small SVE bug when debugging in native mode an inferior which changes the SVE length was committed upstream. - Continued working on fixing regressions in my changes to gdbserver for debugging an inferior which changes the SVE length. -- Thiago

3 years

1
0
0 0

[ACTIVITY] week ending Aug. 21 2022

by Alex Bennée

Project Stratos =============== - continued working on [adding vhost-user-rng to crosvm] - this is to demo Stratos on Gunyah - re-built guest kernel with known working backend - it works :-) - initial review of Viresh's slides for KVM Forum talk [adding vhost-user-rng to crosvm] <https://github.com/stsquad/crosvm/tree/add-vhost-user-rng> vhost-device maintainer effort ([UM-196]) - prepared a clean-up [branch for new queue interface] - spent time testing and realised it had broken things [branch for new queue interface] <https://github.com/stsquad/vhost-device/tree/update-queue-interface> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id: <CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com> - sadly one patch had to be reverted as it exposed another race [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [1/1] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> Absences ======== - will take a long w/e for August BH Current Review Queue ==================== TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org> ======================================================================================================================================= TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org> =========================================================================================================================================================================== -- Alex Bennée

3 years

1
0
0 0

[ACTIVITY] report week ending 19 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - respin and resend for a few patchsets after code review * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - identified what the old ARMv8.5-CMODX feature is now ("prefetch speculation protection") and confirmed that QEMU is already compliant with the instruction fetch ordering requirements so there's no coding work required here - Checked that we implement FEAT_ETS already and sent patches to advertise it in the ID registers - Checked that we already conform to the ordering rules required by "prefetch speculation protection" - Discovered that we accidentally fail to RAZ for a big chunk of the reserved-for-new-AArch32-ID-registers space for v8 CPUs; sent patches fixing that thanks -- PMM

3 years

1
0
0 0

clang-arm64-windows-msvc is red for 12 days

by Galina Kistanova

Hello Linaro Toolchain Working Group, clang-arm64-windows-msvc is red for 12 days. The host is missing a correct version of msvc. Is somebody looking at this? Thanks Galina

3 years, 1 month

2
1
0 0

[ACTIVITY] report week ending 12 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual release cycle work: rounded up a couple of last-minute fixes for "whoops, this crashes" bugs and some safe changes like docs typo fixes. * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - Finished implementing the FEAT_PMUv3p5 work. In the process of testing it I found a handful of bugs in our existing PMU emulation code. Sent out the patchset which fixes those bugs and adds FEAT_PMUv3p5. - Cleaned up the epic to remove subtasks we aren't going to implement (FEAT_SPE, FEAT_TRF), and added one for "actually define the new CPU model" - FEAT_LSE2 is the only remaining real work here, and it is probably going to be seriously tricky...(i.e. I hope to leave it to RTH ;-)) -- PMM

3 years, 1 month

1
0
0 0

[ACTIVITY] week ending Aug. 14 2022

by Alex Bennée

Project Stratos =============== - continued working on [adding vhost-user-rng to crosvm] - this is to demo Stratos on Gunyah - backend comes up and device is detected but queues are not consumed - had some initial discussions with Viresh about talk structure for KVM Forum [adding vhost-user-rng to crosvm] <https://github.com/stsquad/crosvm/tree/add-vhost-user-rng> vhost-device maintainer effort ([UM-196]) - prepared a clean-up [branch for new queue interface] [UM-196] <https://linaro.atlassian.net/browse/UM-196> [branch for new queue interface] <https://github.com/stsquad/vhost-device/tree/update-queue-interface> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.1 v1 0/8] memory leaks and speed tweaks Message-Id: <20220811151413.3350684-8-alex.bennee(a)linaro.org> - will drop most of the speed tweaks until 7.2 opens [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [1/1] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> Absences ======== - 2 day week next week - will take a long w/e for August BH -- Alex Bennée

3 years, 1 month

1
0
0 0

[ACTIVITY] week ending Aug. 7 2022

by Alex Bennée

Project Stratos =============== - worked on [adding vhost-user-rng to crosvm] - this is to demo Stratos on Gunyah [adding vhost-user-rng to crosvm] <https://github.com/stsquad/crosvm/tree/add-vhost-user-rng> vhost-device maintainer effort ([UM-196]) - posted [error message cleanup series] [UM-196] <https://linaro.atlassian.net/browse/UM-196> [error message cleanup series] <https://github.com/rust-vmm/vhost/pull/113> Linux RPMB Sub-system and virtio-driver ([STR-40]) - posted [PATCH v4 for 7.2 00/22] virtio-gpio and various virtio cleanups Message-Id: <20220802095010.3330793-1-alex.bennee(a)linaro.org> [STR-40] <https://linaro.atlassian.net/browse/STR-40> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] util: add a qemu_backtrace utility function Message-Id: <20220801141209.2184305-1-alex.bennee(a)linaro.org> - posted [PATCH v2] linux-user: un-parent OBJECT(cpu) when closing thread Message-Id: <20220803130537.763666-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] cputlb and ssi: cache class to avoid expensive object_dynamic_cast_assert (HACK!!!) Message-Id: <20220804092044.2101093-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [4/4] ======================= [PATCH] tests/tcg/i386: Use explicit suffix on fist insns Message-Id: <20220527171143.168276-1-richard.henderson(a)linaro.org> [PATCH 00/43] semihosting cleanup Message-Id: <20220430132932.324018-1-richard.henderson(a)linaro.org> [PATCH 0/2] gdbstub: don't crash if no gdb attached and gdb syscall attempted Message-Id: <20220526190053.521505-1-peter.maydell(a)linaro.org> [PATCH 0/2] Floating-point OE/UE exception bug Message-Id: <87pmhemzh9.fsf(a)linaro.org> Absences ======== Current Review Queue ==================== TODO [PATCH RFC v2 0/2] arm: enable MTE for QEMU + kvm Message-Id: <20220707161656.41664-1-cohuck(a)redhat.com> ============================================================================================================ TODO [PATCH v4 0/9] Record/replay refactoring and stuff Message-Id: <165364836050.688121.11980415709895333098.stgit@pasha-ThinkPad-X280> ======================================================================================================================================= TODO [PATCH v11 0/2] hw/arm/virt: CXL 2.0 emulation support Message-Id: <20220520163732.27545-3-Jonathan.Cameron(a)huawei.com> =========================================================================================================================== -- Alex Bennée

3 years, 1 month

1
0
0 0

[ACTIVITY] Report for weeks #30 and #31

by Thiago Jung Bauermann

Hello, I noticed that I didn't send a report for week #30. Sorry about that. For that reason, this report covers two weeks. # [GNU-767] Support changing SVE vector length in remote debugging - Prepared and submitted upstream a fix and a testcase for a small SVE bug when debugging in native mode an inferior which changes the SVE length. Luis reviewed it and I submitted v2 addressing his comments. # Misc - Was out for 2 days. -- Thiago

3 years, 1 month

1
0
0 0

[ACTIVITY] report week ending 5 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - more investigation, triage and fixing of minor bugs in run-up to release * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - starting working on the PMUv8p5 enhancements. These consist of a couple of new cycle-counter-disable bits (easy) and extension of the event counters to 64 bits (more tricky). So far I have code for the easy part and have made a start on the hard part... -- PMM

3 years, 1 month

1
0
0 0

[ACTIVITY] report week ending 29 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - debugged and sent patch to fix a bug in timer_create syscall support in linux-user on certain host libcs - tried and failed to repro a bug where semihosting SYS_HEAPINFO was returning addresses in the flash rom - more Coverity issue triage -- now have finished triage of everything that isn't either in the test suite or an "insecure data handling" issue. Sent patches for a few issues, prodded other people about some more... -- PMM

3 years, 1 month

1
0
0 0

[ACTIVITY] Report for week #29

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Fixed last bug which prevented the sve-ioctls QEMU testcase to be correctly stepped through in gdbserver. The next step is checking whether any regression was introduced by my changes, and clean up the code. * In the process, spotted small bug in GDB when stepping through the sve-ioctls QEMU testcase using the existing native support. Started preparing a patch to submit upstream. # [LLVM-769] Linaro CI * Increased tcwg-fx-02 ccache max size to 40 GB. * Learned a bit about Zorg and started adding “depends_on_projects” field to builders running on Linaro workers. -- Thiago

3 years, 1 month

1
0
0 0

Enabling CCache on LLVM bots

by Mehdi AMINI

Hi, I noticed that bots like flang-aarch64-latest-gcc are quite slow and could benefit from enabling ccache. Could you make it available on the system so it could be turned on for all these builds? Thanks, -- Mehdi

3 years, 1 month

4
14
0 0

[ACTIVITY] report week ending 21 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - softfreeze this week; lots of pullrequest merging - spent some time going through our backlog of Coverity Scan issues, triaging them and sending patches for some of them - sent a patchset fixing portability issues in our configure script which had crept in recently and were causing problems on OpenBSD and NetBSD - sent out the invite emails for QEMU Summit -- PMM

3 years, 1 month

1
0
0 0

[ACTIVITY] Report for week #28

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Rebased the actual SVE vector length changes on top of the stabilised per-thread target descriptions changes. Now stabilising the result. Fixed a couple of problems found when remote-debugging QEMU's sve-ioctls test binary, currently looking into a third one. # Linaro CI's GDB testsuite results * Updated and expanded the LLVM Docker Buildbot Maintenance wiki page with the information about ccache setup I gathered in the past few days. Also added a link to it to the Buildkite Bot Maintenance wiki page since libstdc++ buildkites uses the same configuration. * Increased ccache max size in GNU build jobs on tcwg-jade-02. * Updated ABE repo's tested branch with my commits from last week to improve the GDB testsuite results. Confirmed that the GDB testsuite went from 538 unexpected failures to 307. There's still room for improvement though. -- Thiago

3 years, 2 months

1
0
0 0

[ACTIVITY] report week ending 15 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - took over pullreq handling from RTH for the next couple of weeks - wrote and sent patches that fix a mishandling of Secure stage 2 translation caused by QEMU not noticing that some config bits are in VTCR_EL2 and some in VSTCR_EL2. Removed an ancient microoptimization that was getting in the way of fixing that. - sent patch fixing incorrect syndrome value for data abort on some post-indexed load/store insns - RTH's SME patchset is now upstream, so now would be a good time to test it if anybody has compiler test cases or similar they were thinking of running under QEMU - softfreeze next Tuesday: started reviewing and collecting up minor patches for a pre-freeze pullreq -- PMM

3 years, 2 months

1
0
0 0

Status of ccache setup on LLVM build bots

by Thiago Jung Bauermann

Hello, I went through the LLVM build bots (and also the libc++ buildkites) and increased their ccache max size. There was a big impact on the flang builds on tcwg-jade-01 (which went from 1h–2h to 10min–30min), but not on other builds. One reason is probably that since I made this change earlier today, there wasn't time yet to finish enough several-hours-long builds to warm up the caches. Since different machines have different disk sizes and free space I chose different ccache max sizes for them, as follows: * tcwg-fx-02 hosts the following build bots: - clang-aarch64-sve-vls-2stage - clang-aarch64-sve-vls - clang-aarch64-sve-vla-2stage - clang-aarch64-sve-vla All share the same ccache. I changed its max size to 20 GB. It's not a lot, but this machine is also used as a dev box so I though it would be good to preserve a fair amount of space. * tcwg-jade-01 hosts the following build bots: - clang-armv8-lld-2stage - clang-armv7-vfpv3-2stage - clang-armv7-global-isel - clang-armv7-quick - clang-armv7-2stage - clang-armv7-lnt - flang-aarch64-latest-gcc - flang-aarch64-rel-assert - flang-aarch64-release - flang-aarch64-latest-clang - flang-aarch64-debug - flang-aarch64-out-of-tree - flang-aarch64-sharedlibs - flang-aarch64-dylib - clang-aarch64-full-2stage - clang-aarch64-global-isel - clang-aarch64-lld-2stage - clang-aarch64-quick All armv7 and armv8 bots share one ccache, and all aarch64 bots share another. I changed the max size of each one to 100 GB. * tcwg-jade-04 hosts the following build bots: - lldb-aarch64-ubuntu - lldb-arm-ubuntu - buildkite-linaro-armv8-libcxx-01 - buildkite-linaro-armv8-libcxx-02 - buildkite-linaro-armv8-libcxx-03 - buildkite-linaro-armv8-libcxx-04 The buildkite bots share a 50 GB ccache, while lldb-arm-ubuntu uses another 50 GB ccache due to being based on a different distro version. And lldb-aarch64-ubuntu also uses its own 50 GB ccache. * tcwg-llvmbot_tk1-01.tcwglab hosts the following build bot: - silent-linaro-tk1-01 I changed the max cache size to 10 GB. There's not a lot of free space on the machine. * tcwg-llvmbot_tk1-03.tcwglab hosts the following build bot: - normal-linaro-tk1-02 I changed the max cache size to 20 GB. * tcwg-llvmbot_tk1-05.tcwglab hosts the following build bot: - silent-linaro-tk1-08 I changed the max cache size to 10 GB. * The following tcwg-llvmbot_tk1-* machines are currently unreachable so I couldn't examine them: - tcwg-llvmbot_tk1-02.tcwglab - tcwg-llvmbot_tk1-04.tcwglab * The following tcwg-llvmbot_tk1-* machines are running an llvmbot container but no builder container, so I didn't change their ccache configuration: - tcwg-llvmbot_tk1-06.tcwglab - tcwg-llvmbot_tk1-07.tcwglab - tcwg-llvmbot_tk1-08.tcwglab - tcwg-llvmbot_tk1-09.tcwglab * tcwg-jade-02 is a GNU builder, and from peeking into a few containers running build jobs I have the impression that it doesn't use ccache. Should I look into it? * Going through our ssh config file I didn't find these build bots that are listed at http://llvm.validation.linaro.org/ so I didn't check their ccache usage: - clang-arm64-windows-msvc-2stage - clang-arm64-windows-msvc - clang-arm64-windows-msvc-2stage - clang-arm64-windows-msvc - clang-native-arm-lnt-perf - clang-armv7-vfpv3-full-2stage - clang-thumbv7-full-2stage - libcxx aarch64 - libcxx aarch64 -fno-exceptions -- Thiago

3 years, 2 months

2
2
0 0

[ACTIVITY] Report for week #27

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Analysed and fixed a couple more regressions in my branch. The change to per-thread target descriptions in gdbserver (which was the more challenging part) is now free of regressions. Now cleaning up the part that actually deals with the SVE vector length change. # Linaro CI's GDB testsuite results * Increased ccache's max size on most build bots. Sent email to the linaro-toolchain list summarising the current status of their ccache setup. * Started looking more closely into how ccache configuration is put together in our container scripts to document it on the wiki (together with the steps I took to change the ccache max size). -- Thiago

3 years, 2 months

1
0
0 0

linaro-clang-armv8-lld-2stage has been red for a month

by Galina Kistanova

Hello Linaro Toolchain Working Group, linaro-clang-armv8-lld-2stage <https://lab.llvm.org/buildbot/#/workers/140> has been red since June 7th. Is anybody looking at the issue? Thanks Galina

3 years, 2 months

2
1
0 0

[weekly][linaro] report week ending 7 Jul

by Peter Maydell

Progress: (short week, 3 days) * UM-2 [QEMU upstream maintainership] - More code review, as softfreeze is now quite close. I think we've finally got there with the SME patchset (the remaining problems with v5 were very minor) * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - QEMU-315 OS Lock/DoubleLock work now upstream -- PMM

3 years, 2 months

1
0
0 0

clang-armv7-vfpv3-full-2stage has been failing for more than 7 days and sends emails for each failed build

by Florian Hahn

Hi, It looks like https://lab.llvm.org/buildbot/#/builders/190 has been failing for the last week. It also sends out emails for each failed build, instead of for new failures only. The failure is below. It would be great if you could take a look and possibly adjust the configuration of the bot: [10/2380] Linking CXX shared library lib/clang/15.0.0/lib/linux/libclang_rt.scudo_standalone-armhf.so FAILED: lib/clang/15.0.0/lib/linux/libclang_rt.scudo_standalone-armhf.so : && /usr/local/bin/c++ -fPIC -fPIC -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -Wall -std=c++14 -Wno-unused-parameter -O3 -DNDEBUG -Wl,-z,defs -Wl,-z,nodelete -Wl,-rpath-link,/home/tcwg-buildbot/worker/clang-armv7-vfpv3-full-2stage/stage1/./lib -march=armv7-a -mfloat-abi=hard -Wl,-z,defs,-z,now,-z,relro -ffunction-sections -fdata-sections -Wl,--gc-sections -nostdlib++ --unwindlib=none -pthread -shared -Wl,-soname,libclang_rt.scudo_standalone-armhf.so -o lib/clang/15.0.0/lib/linux/libclang_rt.scudo_standalone-armhf.so projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/common_posix.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/mutex_posix.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/utilities_posix.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/stack_trace_compressor.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanBacktraceLibc.armhf.dir/optional/backtrace_linux_libc.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanSegvHandler.armhf.dir/optional/segv_handler_posix.cpp.o projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanOptionsParser.armhf.dir/optional/options_parser.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/checksum.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/common.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/crc32_hw.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/flags_parser.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/flags.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/fuchsia.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/linux.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/release.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/report.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/string_utils.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/wrappers_c.cpp.o projects/compiler-rt/lib/scudo/standalone/CMakeFiles/clang_rt.scudo_standalone-dynamic-armhf.dir/wrappers_cpp.cpp.o -Wl,-rpath,"\$ORIGIN/../lib" && : /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZN8gwp_asan13ErrorToStringERKNS_5ErrorE+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZN8gwp_asan18AllocationMetadata16RecordAllocationEjj+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZN8gwp_asan18AllocationMetadata18RecordDeallocationEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZN8gwp_asan18AllocationMetadata12CallSiteInfo15RecordBacktraceEPFjPjjE+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZNK8gwp_asan14AllocatorState21maximumAllocationSizeEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZNK8gwp_asan14AllocatorState10slotToAddrEj+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZNK8gwp_asan14AllocatorState11isGuardPageEj+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/common.cpp.o:(.ARM.exidx.text._ZNK8gwp_asan14AllocatorState14getNearestSlotEj+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_error_is_mine+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_internal_crash_address+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_diagnose_error+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_metadata+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_allocation_address+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_allocation_size+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_allocation_thread_id+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_allocation_trace+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_is_deallocated+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_deallocation_thread_id+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/crash_handler.cpp.o:(.ARM.exidx.text.__gwp_asan_get_deallocation_trace+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/common_posix.cpp.o:(.ARM.exidx.text._ZN8gwp_asan11getThreadIDEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator8initPRNGEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZNK8gwp_asan20GuardedPoolAllocator3mapEjPKc+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator18reserveGuardedPoolEj+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZNK8gwp_asan20GuardedPoolAllocator21allocateInGuardedPoolEPvj+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZNK8gwp_asan20GuardedPoolAllocator23deallocateInGuardedPoolEPvj+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator19getPlatformPageSizeEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator13installAtForkEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZZN8gwp_asan20GuardedPoolAllocator13installAtForkEvEN3$_08__invokeEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/platform_specific/guarded_pool_allocator_posix.cpp.o:(.ARM.exidx.text._ZZN8gwp_asan20GuardedPoolAllocator13installAtForkEvEN3$_18__invokeEv+0x0): more undefined references to `__aeabi_unwind_cpp_pr0' follow /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator7disableEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator6enableEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator7iterateEPvjPFvjjS1_ES1_+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator8allocateEjj+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator4stopEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator10deallocateEPv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/guarded_pool_allocator.cpp.o:(.ARM.exidx.text._ZN8gwp_asan20GuardedPoolAllocator7getSizeEPKv+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/stack_trace_compressor.cpp.o:(.ARM.exidx.text._ZN8gwp_asan11compression4packEPKjjPhj+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsan.armhf.dir/stack_trace_compressor.cpp.o:(.ARM.exidx.text._ZN8gwp_asan11compression6unpackEPKhjPjj+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanBacktraceLibc.armhf.dir/optional/backtrace_linux_libc.cpp.o:(.ARM.exidx.text._ZN8gwp_asan9backtrace20getBacktraceFunctionEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanBacktraceLibc.armhf.dir/optional/backtrace_linux_libc.cpp.o:(.ARM.exidx.text._ZN12_GLOBAL__N_19BacktraceEPjj+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanBacktraceLibc.armhf.dir/optional/backtrace_linux_libc.cpp.o:(.ARM.exidx.text._ZN8gwp_asan9backtrace25getPrintBacktraceFunctionEv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanBacktraceLibc.armhf.dir/optional/backtrace_linux_libc.cpp.o:(.ARM.exidx.text._ZN12_GLOBAL__N_114PrintBacktraceEPjjPFvPKczE+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanBacktraceLibc.armhf.dir/optional/backtrace_linux_libc.cpp.o:(.ARM.exidx.text._ZN8gwp_asan9backtrace24getSegvBacktraceFunctionEv+0x0): more undefined references to `__aeabi_unwind_cpp_pr0' follow /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanSegvHandler.armhf.dir/optional/segv_handler_posix.cpp.o:(.ARM.exidx.text._ZN8gwp_asan12segv_handler21installSignalHandlersEPNS_20GuardedPoolAllocatorEPFvPKczEPFvPjjS6_EPFjS7_jPvE+0x0): undefined reference to `__aeabi_unwind_cpp_pr1' /usr/bin/ld: projects/compiler-rt/lib/gwp_asan/CMakeFiles/RTGwpAsanSegvHandler.armhf.dir/optional/segv_handler_posix.cpp.o:(.ARM.exidx.text._ZN12_GLOBAL__N_114sigSegvHandlerEiP9siginfo_tPv+0x0): undefined reference to `__aeabi_unwind_cpp_pr0' clang-13: error: linker command failed with exit code 1 (use -v to see invocation) [11/2380] Linking CXX static library lib/libLLVMObject.a Cheers, Florian

3 years, 2 months

2
3
0 0

[ACTIVITY] Report for week #26

by Thiago Jung Bauermann

Hello, # Linaro CI's GDB testsuite results * Implemented new version of change in the Abe shell script to correctly set auto-load-safe-path so that GDB can load libthread_db.so.1. Since GDB's configure script needs to be passed an argument containing literal dollar signs, use '@@' instead of '$' to avoid the shell misinterpreting it and substitute at the point of use. This version worked and was merged to the Abe repo. * Implemented and merged change in the Abe shell script to set variables pointing to language-specific target tools only if they are present in the path. This fixes Ada test failures in the GDB testsuite. * Implemented and merged improvement to our tcwg_gnu-build.sh script to allow specifying on the command line the Abe repo and branch to use. # [GNU-767] Support changing SVE vector length in remote debugging * Analysed and fixed a couple more regressions in my branch. -- Thiago

3 years, 2 months

1
0
0 0

[ACTIVITY] report week ending 1 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Code review (misc, plus another round on the SME patchset) - KVM Forum programme committee work * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - Wrote and sent patches that deal with the last of the "small and uninteresting" dependencies of the V1 support epic (this one covers Feat_DoubleLock, which lets guest OSes suppress debug events as part of their power-down-a-CPU sequence) -- PMM

3 years, 2 months

1
0
0 0

qemu meeting status

by Richard Henderson

Hi guys. I just realized that today's meeting will be right in the middle of dinner plans. I'll organize better next week. Anyway, here's my status: - Fourth SME patch set -- parts merged, and some bugs fixed. - Base/arm-compat portion of semihosting rewrite now upstream. Target-specific bits for m68k, mips, nios2, xtensa outstanding. - Almost done with FEAT_HAFDBS (hardware access/dirty updates). Big changes to ptw.c to make that work: 50+ patches. The reorg should make FEAT_RME easier though. r~

3 years, 2 months

2
1
0 0

[ACTIVITY] Report for weeks #24 and #25

by Thiago Jung Bauermann

Hello, I just noticed that I didn't send a report for week #24. Sorry about that. For that reason, this report covers two weeks. # Linaro CI's GDB testsuite results * Submitted upstream patch fixing gdb_compile regexp to account for our GNATMAKE_FOR_TARGET value containing spaces. This should solve the Ada test failures in our CI. * Fixed the Abe shell script to correctly set auto-load-safe-path so that GDB can load libthread_db.so.1. Unfortunately the CI detected a problem with using the generated manifest to reproduce the toolchain build, so I'm back to the drawing board on this one. * Sent a Gerrit change request for the Abe script updating it to use release 12's branch and tag for GDB and gdbserver, and another one removing a workaround for a build problem fixed in GDB 9. * Sent a Gerrit change request for tcwg-dev-build.sh fixing a couple of issues I found when using it to build and test GDB. # [GNU-767] Support changing SVE vector length in remote debugging * Analysed and fixed a couple more regressions in my branch. # Misc * Attended a few online sessions from Linaro San Francisco Get Together. * Sent Gerrit change request updating the TCWG script that generates our SSH known_hosts file to include the Ed25519 host keys, which are now preferred in Ubuntu 22.04. * Was out one day due to “Corpus Christi” public holiday. -- Thiago

3 years, 2 months

1
0
0 0

[weekly][linaro] report week ending 24 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - First week back after holiday: lots of catchup - Good progress with the code review queue, including getting rid of a few things that had been lurking in it for too long, and another pass through the latest SME series - KVM Forum programme committee work -- PMM

3 years, 2 months

1
0
0 0

[ACTIVITY] Report for week #23

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Debugged and fixed a few issues in my code where gdbserver was having trouble with setting the target description for new threads. Also fixed regressions in a couple more testcases. # Linaro CI's GDB testsuite results * Luis commented on IRC that the GDB testsuite results from the Linaro CI seemed a bit high with about 540 failures, so I set out to investigate. The two biggest sources of failures are: 1. Ada tests were failing because they can't build their test executables. This is expected because we don't have the Ada compiler in the CI, but normally these testcases would just bail out as unsupported. Found out that there was a regex in the GDB testsuite that was (IMHO) too strict for our particular setup and fixed it. 2. All CTF tests are failing. The compiler in the CI seems to be building test executables with CTF debug info, so we do seem to have a problem there. The CI's GDB is also not loading libthread_db.so because of a GDB security setting, so I fixed that as well and expect some more tests to pass now. I still haven't submitted my fixes for 1. to upstream and for the libthread_db.so.1 issue to our CI scripts because I'm still working with jenkins-scripts and Abe to reproduce the CI environment to verify the fixes. -- Thiago

3 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 10 Jun

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - This week was almost entirely code review and similar upstream tasks - managed to review all the preliminary parts of the SME patchset - reviewed several other refactoring series from rth - reviewed a big PS/2 keyboard emulation refactoring patchset - prep for KVM Forum program committee session * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - FEAT_RASv1p1 and FEAT_DoubleFault now upstream -- PMM

3 years, 3 months

1
0
0 0

[ACTIVITY] Report for week #22

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Debugged and fixed issues in my code where gdbserver was in some cases trying to read inferior registers before aarch64_target was fully initialised, and also while the inferior thread was running. This improved reliability but there are still some testsuite regressions to look into. # Sourceware bug 28561 - [gdb/testsuite] Error due to not reading \r\n at end of mi prompt * Posted comment to the bug report summarising my current results. * Tried to reproduce the bug using the upstream v5.3 kernel (since I was able to see it with openSUSE Leap's v5.3 kernel), but failed. Still trying to understand what that implies. -- Thiago

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: rs6000: Harden mma_init_builtins

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: rs6000: Harden mma_init_builtins: commit 6278065af07634278ba30029d92a82b089969baa Author: Peter Bergner <bergner(a)linux.ibm.com> rs6000: Harden mma_init_builtins Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:03:13 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:03:13 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:03:13 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:03:13 make[2]: *** [scripts/gcc-plugins/stackleak_plugin.so] Error 1 # 00:03:13 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:03:13 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:03:13 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:03:14 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 31574 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-aarch64-next-allmodconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Reproduce builds: <cut> mkdir investigate-gcc-6278065af07634278ba30029d92a82b089969baa cd investigate-gcc-6278065af07634278ba30029d92a82b089969baa # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach 6278065af07634278ba30029d92a82b089969baa ../artifacts/test.sh # Reproduce last_good build git checkout --detach a5b5c7c2840ebb0aaa0d0f1e090fb2fc6942196d ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit 6278065af07634278ba30029d92a82b089969baa Author: Peter Bergner <bergner(a)linux.ibm.com> Date: Wed Jul 7 11:39:34 2021 -0500 rs6000: Harden mma_init_builtins The previous MMA patch added some fragile code to initialize its new built-ins. This patch hardens the initialization. 2021-07-07 Peter Bergner <bergner(a)linux.ibm.com> gcc/ * config/rs6000/rs6000-call.c (mma_init_builtins): Use VSX_BUILTIN_LXVP and VSX_BUILTIN_STXVP. --- gcc/config/rs6000/rs6000-call.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 6115e3b34d9..904e104c058 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -14293,7 +14293,8 @@ mma_init_builtins (void) /* Some MMA built-ins that are expanded into gimple are converted into internal MMA built-ins that are expanded into rtl. The internal built-in follows immediately after this built-in. */ - if (d[1].icode != CODE_FOR_nothing) + if (d->code != VSX_BUILTIN_LXVP + && d->code != VSX_BUILTIN_STXVP) { op[nopnds++] = void_type_node; icode = d[1].icode; </cut>

3 years, 3 months

3
2
0 0

[ACTIVITY] report week ending 31 May

by Peter Maydell

Progress (covers two half-weeks): * UM-2 [QEMU upstream maintainership] - investigating a reported bug with semihosting syscalls over gdbstub - reviewed a massive series from RTH refactoring our SVE code in preparation for handling SME * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - looking at exactly what FEAT_RASv1p1 and FEAT_DoubleFault require of a minimal RAS implementation like QEMU's - sent a patch implementing FEAT_RASv1p1 (a no-op for QEMU) - sent a patch implementing FEAT_DoubleFault (turns out to be simpler than I initially feared it might be) -- PMM

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: rs6000: MMA test case ICEs using -O3 [PR99842]

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: rs6000: MMA test case ICEs using -O3 [PR99842]: commit df4e0359dad239854af0ea9eacb8e7e3719557d0 Author: Peter Bergner <bergner(a)linux.ibm.com> rs6000: MMA test case ICEs using -O3 [PR99842] Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:00:57 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:57 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:57 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:57 make[2]: *** [scripts/gcc-plugins/stackleak_plugin.so] Error 1 # 00:00:57 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:00:57 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:00:57 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:00:59 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 21071 # linux build successful: all THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-aarch64-next-allyesconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Reproduce builds: <cut> mkdir investigate-gcc-df4e0359dad239854af0ea9eacb8e7e3719557d0 cd investigate-gcc-df4e0359dad239854af0ea9eacb8e7e3719557d0 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach df4e0359dad239854af0ea9eacb8e7e3719557d0 ../artifacts/test.sh # Reproduce last_good build git checkout --detach e21e93407202e62a10c372595076c593c561bb11 ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit df4e0359dad239854af0ea9eacb8e7e3719557d0 Author: Peter Bergner <bergner(a)linux.ibm.com> Date: Sun May 30 22:45:55 2021 -0500 rs6000: MMA test case ICEs using -O3 [PR99842] The mma_assemble_input_operand predicate does not accept reg+reg indexed addresses which can lead to ICEs. The lxv and lxvp instructions have indexed forms (lxvx and lxvpx), so the simple solution is to just allow indexed addresses in the predicate. 2021-05-30 Peter Bergner <bergner(a)linux.ibm.com> gcc/ PR target/99842 * config/rs6000/predicates.md(mma_assemble_input_operand): Allow indexed form addresses. gcc/testsuite/ PR target/99842 * g++.target/powerpc/pr99842.C: New. --- gcc/config/rs6000/predicates.md | 3 +- gcc/testsuite/g++.target/powerpc/pr99842.C | 188 +++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index e21bc745f72..121cbf14810 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1172,7 +1172,8 @@ (match_test "(mode == V16QImode && (vsx_register_operand (op, mode) || (MEM_P (op) - && quad_address_p (XEXP (op, 0), mode, false))))")) + && (indexed_or_indirect_address (XEXP (op, 0), mode) + || quad_address_p (XEXP (op, 0), mode, false)))))")) ;; Return 1 if this operand is valid for an MMA disassemble insn. (define_predicate "mma_disassemble_output_operand" diff --git a/gcc/testsuite/g++.target/powerpc/pr99842.C b/gcc/testsuite/g++.target/powerpc/pr99842.C new file mode 100644 index 00000000000..922450e2c21 --- /dev/null +++ b/gcc/testsuite/g++.target/powerpc/pr99842.C @@ -0,0 +1,188 @@ +/* PR target/99842 */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power10 -Wno-return-type" } */ + +/* Verify we do not ICE on the following noisy creduced test case. */ + +enum { a, b, c, d }; +template <typename> struct e; +template <typename g, typename h, typename k> struct e<g(h, k)> { + typedef h f; +}; +template <typename> struct ac; +template <typename ab> struct ac<const ab> : ac<ab> {}; +template <typename> struct l; +template <typename, int, int m, int = 0, int = a, int = m> class n; +template <typename> class o; +template <typename, typename, typename> class ag; +template <typename, typename, int = c> class af; +template <typename> struct ad; +template <typename ab> struct an { + typedef n<typename ab ::ah, ac<ab>::ai, ac<ab>::aj> f; +}; +template <typename al> struct am { typedef o<al> f; }; +template <typename al, typename = typename ac<al>::ao, + typename = typename ac<al>::av> +struct ak; +template <typename al, typename ao> struct ak<al, ao, int> { + typedef typename am<al>::f f; +}; +template <typename, typename, typename> struct aq; +template <typename ar, typename as> struct aq<ar, ar, as> { typedef ar at; }; +template <typename ap> ap bf(const typename ad<ap>::f *); +template <typename ap, int> ap aw(typename ad<ap>::f *ax) { return bf<ap>(ax); } +typedef __attribute__((altivec(vector__))) double au; +template <> struct ad<au> { typedef double f; }; +template <> au bf(const double *ax) { return __builtin_vec_vsx_ld(0, ax); } +template <typename> struct az {}; +template <typename al> class o : public l<al> { +public: + typedef typename ac<al>::ah ah; + template <typename ay> al &operator+=(const o<ay> &); +}; +template <typename> struct l {}; +template <typename ba, typename bb, int bd> struct ac<af<ba, bb, bd>> { + typedef typename ba::ah ah; + enum { ai, aj }; +}; +template <typename, typename, int bd> +class af + : public ak< + af<ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3>, bd>, + int, int>::f {}; +template <typename, typename, typename> struct be; +template <typename bj, typename bg, typename g> void bi(bj, bg bm, g) { + typename an<bg>::f bk(bm); +} +template <typename bj, typename bg, typename g> void bl(bj, bg bm, g bp) { + be<bj, bg, g>::bn(a, bm, bp); +} +template <typename, typename, typename, typename> struct bo; +class bs { +public: + bs(double *, int); + double &operator()(int, int) { return bq[br]; } + template <typename bw, int> bw bt(int i, int j) { + double &bu = operator()(i, j); + return aw<bw, b>(&bu); + } + double *bq; + int br; +}; +class ca : public bs { +public: + ca(double *by, int bz) : bs(by, bz) {} +}; +template <typename al> class ce : public am<al>::f { +protected: + template <typename ay> void cb(l<ay>) { + af<ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3>> + cc; + bl(0, cc, az<typename ay::ah>()); + } + template <typename> void ch(long); + template <typename ay> void ch(l<ay> cf) { cb(cf); } +}; +template <typename cg, int aa, int m, int cl, int ci, int cj> +struct ac<n<cg, aa, m, cl, ci, cj>> { + typedef cg ah; + typedef int av; +}; +template <typename cg, int, int m, int, int, int> +class n : public ce<n<cg, m, c>> { +public: + template <typename ab> n(ab p) { n::template ch<ab>(p); } +}; +template <typename bc, typename ba, typename bb> struct ac<ag<bc, ba, bb>> { + typedef ba ao; + typedef typename e<bc(typename ba::ah, typename bb::ah)>::f ah; + typedef typename aq<typename ac<ba>::av, typename ac<bb>::av, bc>::at av; +}; +template <typename> class cm; +template <typename, typename r, typename cs> +class ag + : public cm<typename aq<typename ac<r>::av, typename ac<cs>::av, int>::at> { +}; +template <typename> +class cm : public ak<ag<int, n<double, 1, 1>, n<double, 1, 1>>>::f {}; +template <typename al> +template <typename ay> +al &o<al>::operator+=(const o<ay> &) { + af<ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3>> + co; + bi(0, co, int()); +} +enum { cp }; +template <int> struct cq; +template <typename> struct cr { + enum { q }; + enum { ae = cq<q>::at }; +}; +template <> struct cq<cp> { + enum { at = d }; +}; +struct t { + template <typename ba, typename bb, typename s> static void bn(ba, bb, s) { + typedef typename bb::ah x; + x u; + bo<long, ca, x, ca>::bn(0, 0, ca(0, 0), ca(&u, 1), 0, 0, 0); + } +}; +template <typename, typename bb, int = cr<bb>::ae> struct cu; +template <typename cd, typename ba, typename bb, int ct, typename ah> +struct be<cd, af<ba, bb, ct>, az<ah>> { + static void bn(cd, af<ba, bb> bm, az<ah>) { + ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>> da; + cu<ba, bb>::cv(c, da, bm); + } +}; +template <typename al> struct cw { + template <typename bj> + static void + cv(bj, ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>>, + n<double, -1, 1, 3> bx) { + double alpha; + ag<int, const n<double, -1, -1, 3>, const n<double, -1, -1, 3>> bh; + al::cx(c, bh, bx, alpha); + } +}; +template <typename ba, typename bb> struct cu<ba, bb, d> : cw<cu<ba, bb>> { + template <typename s> static void cx(s, ba, bb bx, typename af<ba, bb>::ah) { + ba cz; + t::bn(cz, bx, c); + } +}; +template <typename dj, typename, bool> +void db(__vector_quad *, __vector_pair &, dj); +template <typename, typename, typename, typename, typename, typename, int> +void dc(ca alhs) { + typedef au dj; + typedef au dd; + ca bh(alhs); + enum { de }; + __vector_quad df, dg; + int j; + dd v; + __vector_pair dh; + __builtin_mma_assemble_pair( + &dh, (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j), + (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j)); + db<dj, dd, true>(&df, dh, v); + __vector_pair di; + __builtin_mma_assemble_pair( + &di, (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j), + (__attribute__((altivec(vector__))) char)bh.bt<dj, de>(0, j)); + db<dj, dd, true>(&dg, di, v); +} +template <typename bv, typename w, typename cy> struct bo<bv, w, double, cy> { + static void bn(bv, bv, w bh, cy, double, bv, double) { + dc<bv, double, w, double, cy, double, d>(bh); + } +}; +void dm() { + n<double, 1, 1> dk(1), y(0); + y += dk; +} </cut>

3 years, 3 months

3
2
0 0

[ACTIVITY] Report for week #21

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Found out that one issue I was having with gdbserver was caused by an incompatibility it has with zsh (sourceware bug 26116). * Fixed a gdbserver crash in my code where a register set was NULL in the target description. * Now working on an issue where the target description says SVE isn't supported, but the regsets information says they are. This is caused by my code sometimes moving the first ptrace call to get the inferior registers to a time before it is properly stopped. # Sourceware bug 28561 - [gdb/testsuite] Error due to not reading \r\n at end of mi prompt * Set up a few containers and KVM guests to attempt to reproduce this bug on different environments. Reproduced it successfully on an openSUSE Leap 15.3 guest, as well as Ubuntu 20.04 and 22.04 containers in said guest. I wasn't able to reproduce on Ubuntu 20.04 nor 22.04 guests. Suspecting it's a kernel issue where the fix was backported to the Ubuntu kernels. -- Thiago

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: c++: designators in single-element init lists

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: c++: designators in single-element init lists: commit 885035eacb36b5bf1aa3b0d05f675ab89665d7be Author: Jason Merrill <jason(a)redhat.com> c++: designators in single-element init lists Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:00:55 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:55 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:55 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:56 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:00:56 make[2]: *** [scripts/gcc-plugins/stackleak_plugin.so] Error 1 # 00:00:56 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:00:56 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:00:57 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 21071 # linux build successful: all THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-aarch64-next-allyesconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Reproduce builds: <cut> mkdir investigate-gcc-885035eacb36b5bf1aa3b0d05f675ab89665d7be cd investigate-gcc-885035eacb36b5bf1aa3b0d05f675ab89665d7be # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach 885035eacb36b5bf1aa3b0d05f675ab89665d7be ../artifacts/test.sh # Reproduce last_good build git checkout --detach 84fd1b5dff70cd74aee7e8b18f66959d8b8e1ce7 ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit 885035eacb36b5bf1aa3b0d05f675ab89665d7be Author: Jason Merrill <jason(a)redhat.com> Date: Wed May 19 21:13:43 2021 -0400 c++: designators in single-element init lists While looking at PR100489, it occurred to me that places that currently use an initializer-list with a single element to initialize an object of the same type shouldn't do that if the element has a designator. gcc/cp/ChangeLog: * call.c (reference_binding): Check for designator. (implicit_conversion_1, build_special_member_call): Likewise. * decl.c (reshape_init_r): Likewise. * pt.c (do_class_deduction): Likewise. * typeck2.c (digest_init_r): Likewise. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/desig19.C: New test. --- gcc/cp/call.c | 5 ++++- gcc/cp/decl.c | 2 ++ gcc/cp/pt.c | 3 ++- gcc/cp/typeck2.c | 1 + gcc/testsuite/g++.dg/cpp2a/desig19.C | 33 +++++++++++++++++++++++++++++++++ 5 files changed, 42 insertions(+), 2 deletions(-) diff --git a/gcc/cp/call.c b/gcc/cp/call.c index fa770f244cb..cfccf273632 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -1731,7 +1731,8 @@ reference_binding (tree rto, tree rfrom, tree expr, bool c_cast_p, int flags, because A[] and A[2] are reference-related. But we don't do it because grok_reference_init has deduced the array size (to 1), and A[1] and A[2] aren't reference-related. */ - if (CONSTRUCTOR_NELTS (expr) == 1) + if (CONSTRUCTOR_NELTS (expr) == 1 + && !CONSTRUCTOR_IS_DESIGNATED_INIT (expr)) { tree elt = CONSTRUCTOR_ELT (expr, 0)->value; if (error_operand_p (elt)) @@ -2095,6 +2096,7 @@ implicit_conversion_1 (tree to, tree from, tree expr, bool c_cast_p, { if (BRACE_ENCLOSED_INITIALIZER_P (expr) && CONSTRUCTOR_NELTS (expr) == 1 + && !CONSTRUCTOR_IS_DESIGNATED_INIT (expr) && !is_list_ctor (cand->fn)) { /* "If C is not an initializer-list constructor and the @@ -10199,6 +10201,7 @@ build_special_member_call (tree instance, tree name, vec<tree, va_gc> **args, if (BRACE_ENCLOSED_INITIALIZER_P (arg) && !TYPE_HAS_LIST_CTOR (class_type) + && !CONSTRUCTOR_IS_DESIGNATED_INIT (arg) && CONSTRUCTOR_NELTS (arg) == 1) arg = CONSTRUCTOR_ELT (arg, 0)->value; diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 6107b553cb4..e7268d5ad18 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -6650,6 +6650,8 @@ reshape_init_r (tree type, reshape_iter *d, tree first_initializer_p, initialized from that element." Even if T is an aggregate. */ if (cxx_dialect >= cxx11 && (CLASS_TYPE_P (type) || VECTOR_TYPE_P (type)) && first_initializer_p + /* But not if it's a designated init. */ + && !d->cur->index && d->end - d->cur == 1 && reference_related_p (type, TREE_TYPE (init))) { diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 3d1787b6fc3..99a9ee5ade2 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -29326,7 +29326,8 @@ do_class_deduction (tree ptype, tree tmpl, tree init, { list_init_p = true; try_list_ctor = TYPE_HAS_LIST_CTOR (type); - if (try_list_ctor && CONSTRUCTOR_NELTS (init) == 1) + if (try_list_ctor && CONSTRUCTOR_NELTS (init) == 1 + && !CONSTRUCTOR_IS_DESIGNATED_INIT (init)) { /* As an exception, the first phase in 16.3.1.7 (considering the initializer list as a single argument) is omitted if the diff --git a/gcc/cp/typeck2.c b/gcc/cp/typeck2.c index 5a7219dec65..6679e247816 100644 --- a/gcc/cp/typeck2.c +++ b/gcc/cp/typeck2.c @@ -1183,6 +1183,7 @@ digest_init_r (tree type, tree init, int nested, int flags, the object is initialized from that element." */ if (cxx_dialect >= cxx11 && BRACE_ENCLOSED_INITIALIZER_P (stripped_init) + && !CONSTRUCTOR_IS_DESIGNATED_INIT (stripped_init) && CONSTRUCTOR_NELTS (stripped_init) == 1 && ((CLASS_TYPE_P (type) && !CLASSTYPE_NON_AGGREGATE (type)) || VECTOR_TYPE_P (type))) diff --git a/gcc/testsuite/g++.dg/cpp2a/desig19.C b/gcc/testsuite/g++.dg/cpp2a/desig19.C new file mode 100644 index 00000000000..3321da85802 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/desig19.C @@ -0,0 +1,33 @@ +// { dg-do compile { target c++11 } } +// { dg-options "" } + +struct A +{ + int i; + constexpr operator int() { return 42; } +}; + +#define SA(X) static_assert ((X),#X) +constexpr A a1 { A() }; +SA(a1.i == 0); +constexpr A a2 { i: A() }; +SA(a2.i == 42); +#if __cpp_constexpr >= 201304L +constexpr int f3 () { A const &r { A() }; return r.i; } +SA(f3() == 0); +constexpr int f4 () { A const &r { i: A() }; return r.i; } +SA(f4() == 42); +constexpr int f5 () { A ar[1]{{ A() }}; return ar[0].i; } +SA(f5() == 0); +constexpr int f5a () { A ar[1]{{ i: A() }}; return ar[0].i; } +SA(f5a() == 42); +#if __cpp_constexpr >= 201907L +constexpr int f6 () { A* p = new A{A()}; int i = p->i; delete p; return i; } +SA(f6() == 0); +constexpr int f6a () { A* p = new A{i:A()}; int i = p->i; delete p; return i; } +SA(f6a() == 42); +#endif +#endif +constexpr int f7 (A a) { return a.i; } +SA(f7({A()}) == 0); +SA(f7({i:A()}) == 42); </cut>

3 years, 3 months

1
0
0 0

[ACTIVITY] week ending May. 29 2022

by Alex Bennée

Project Stratos =============== - posted [RFC PATCH] xen/arm: p2m don't fall over on FEAT_LPA enabled hw Message-Id: <20220426160548.2020794-1-alex.bennee(a)linaro.org> - posted [PATCH v2] xen/arm: p2m don't fall over on FEAT_LPA enabled hw Message-Id: <20220428103410.2723837-1-alex.bennee(a)linaro.org> - many discussions and plans at KWG sprint - posted Remaining Xen enabling work for rust-vmm Message-Id: <87pmk472ii.fsf(a)linaro.org> - posted vhost-device outstanding tasks Message-Id: <87zgj87alq.fsf(a)linaro.org> vhost-device maintainer effort ([UM-196]) - adopted [PATCH 0/2] virtio: Add vhost-user-gpio device's support Message-Id: <5f560cab92d0d789b1c94295ec74b9952907d69d.1641987128.git.viresh.kumar(a)linaro.org> - posted [RFC PATCH v2] tests/qtest: attempt to enable tests for virtio-gpio (!working) Message-Id: <20220408155704.2777166-1-alex.bennee(a)linaro.org> - posted [PATCH v2 00/15] virtio-gpio and various virtio cleanups Message-Id: <20220524154056.2896913-14-alex.bennee(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 00/15] testing, docs, tracepoints and cputlb hacks Message-Id: <20220408164742.2844631-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/i386: avoid copying junk to extended ZMMReg fields Message-Id: <20220411145609.3932882-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] gdb/gic: expose cpu_index via MxTxAttrs Message-Id: <20220412104519.201655-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/guest-debug: better handle gdb crashes Message-Id: <20220413121115.639610-1-alex.bennee(a)linaro.org> - posted [PATCH v2 01/15] contrib/vhost-user-blk: fix 32 bit build and enable Message-Id: <9c313696-6626-0b9e-0625-394fb2b38e21(a)redhat.com> - posted [PATCH v1 00/33] testing/next (gitlab, junit, lcitool, x-compile) Message-Id: <20220527153603.887929-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [7/7] ======================= [PATCH for-7.1 v2 00/39] Logging cleanup and per-thread logfiles Message-Id: <20220326132534.543738-1-richard.henderson(a)linaro.org> [PATCH 00/17] tests/docker and tests/tcg cleanup and diet Message-Id: <20220401141326.1244422-1-pbonzini(a)redhat.com> [PATCH v1] virtio/virtio.c: include virtio prefix in error message Message-Id: <20220414112902.41390-1-codeguy.moteen(a)gmail.com> [PATCH v3 00/39] Logging cleanup and per-thread logfiles Message-Id: <20220417183019.755276-1-richard.henderson(a)linaro.org> [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus Message-Id: <20220417174426.711829-1-richard.henderson(a)linaro.org> - or at least a chunk of it [PATCH] Remove Ubuntu 18.04 support from the repository Message-Id: <20220510195612.677494-1-thuth(a)redhat.com> [PATCH 00/16] Cross compilation of embedded firmware Message-Id: <20220517092616.1272238-1-pbonzini(a)redhat.com> Current Review Queue ==================== TODO [PATCH v4 0/9] Record/replay refactoring and stuff Message-Id: <165364836050.688121.11980415709895333098.stgit@pasha-ThinkPad-X280> ======================================================================================================================================= TODO [PATCH v11 0/2] hw/arm/virt: CXL 2.0 emulation support Message-Id: <20220520163732.27545-3-Jonathan.Cameron(a)huawei.com> =========================================================================================================================== TODO [PATCH v2 0/7] target/arm: SME prep patches Message-Id: <20220517054850.177016-1-richard.henderson(a)linaro.org> ================================================================================================================== -- Alex Bennée

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: Daily bump.

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: Daily bump.: commit b75978d14fc35981ffd8bf060ee52300db4dae50 Author: GCC Administrator <gccadmin(a)gcc.gnu.org> Daily bump. Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:00:52 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:52 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:00:53 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:00:53 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:00:53 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:00:53 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 22769 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-arm-next-allmodconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Reproduce builds: <cut> mkdir investigate-gcc-b75978d14fc35981ffd8bf060ee52300db4dae50 cd investigate-gcc-b75978d14fc35981ffd8bf060ee52300db4dae50 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach b75978d14fc35981ffd8bf060ee52300db4dae50 ../artifacts/test.sh # Reproduce last_good build git checkout --detach ac0bc21bd634a334ba8f323c39a11f01dfdc2aae ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit b75978d14fc35981ffd8bf060ee52300db4dae50 Author: GCC Administrator <gccadmin(a)gcc.gnu.org> Date: Wed Jun 2 00:16:43 2021 +0000 Daily bump. --- gcc/ChangeLog | 132 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 9 ++++ gcc/cp/ChangeLog | 19 +++++++ gcc/fortran/ChangeLog | 38 ++++++++++++++ gcc/testsuite/ChangeLog | 61 ++++++++++++++++++++++ libstdc++-v3/ChangeLog | 38 ++++++++++++++ 7 files changed, 298 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e1ae7fa23f0..ef69e6a04b3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,135 @@ +2021-06-01 Andrew Pinski <apinski(a)marvell.com> + + PR tree-optimization/25290 + * tree-ssa-phiopt.c (match_simplify_replacement): + New function. + (tree_ssa_phiopt_worker): Use match_simplify_replacement. + (two_value_replacement): Change the comment about + conditional_replacement. + (conditional_replacement): Delete. + +2021-06-01 Andrew Pinski <apinski(a)marvell.com> + + PR tree-optimization/95481 + * tree-tailcall.c (find_tail_calls): Handle empty typed + return decls. + +2021-06-01 Andrew Pinski <apinski(a)marvell.com> + + * gimplify.c (zero_sized_field_decl): Delete + (zero_sized_type): Delete + (gimplify_init_ctor_eval): Use is_empty_type instead + of zero_sized_field_decl. + (gimplify_modify_expr): Use is_empty_type instead of + zero_sized_type. + +2021-06-01 Jason Merrill <jason(a)redhat.com> + + PR c++/91859 + * tree.h (CALL_FROM_NEW_OR_DELETE_P): Adjust comment. + +2021-06-01 Jason Merrill <jason(a)redhat.com> + + PR c++/94492 + * diagnostic.h (warning_enabled_at): Declare. + * diagnostic.c (diagnostic_enabled): Factor out from... + (diagnostic_report_diagnostic): ...here. + (warning_enabled_at): New. + +2021-06-01 Aldy Hernandez <aldyh(a)redhat.com> + + * gimple-ssa-evrp.c: Enable exporting of global ranges. + +2021-06-01 Martin Liska <mliska(a)suse.cz> + + PR other/100826 + * doc/invoke.texi: Mention that -fgcse-after-reload + is enabled with -O3. + +2021-06-01 liuhongt <hongtao.liu(a)intel.com> + + PR tree-optimization/98365 + * tree-if-conv.c (strip_nop_cond_scalar_reduction): New function. + (is_cond_scalar_reduction): Handle nop_expr in cond scalar reduction. + (convert_scalar_cond_reduction): Ditto. + (predicate_scalar_phi): Ditto. + +2021-06-01 Andrew MacLeod <amacleod(a)redhat.com> + + PR tree-optimization/100781 + * gimple-range-cache.cc (ranger_cache::ranger_cache): Enable new + value calculation by default. + (ranger_cache::enable_new_values): New. + (ranger_cache::disable_new_values): New. + (ranger_cache::push_poor_value): Check if new values are allowed. + * gimple-range-cache.h (class ranger_cache): New member/methods. + * gimple-range.cc (gimple_ranger::range_of_expr): Check for debug + statement, and disable/renable new value calculation. + +2021-06-01 Andrew MacLeod <amacleod(a)redhat.com> + + * gimple-range-cache.cc (ranger_cache::ssa_range_in_bb): Delete. + (ranger_cache::range_of_def): New. + (ranger_cache::entry_range): New. + (ranger_cache::exit_range): New. + (ranger_cache::range_of_expr): Adjust. + (ranger_cache::range_on_edge): Adjust. + (ranger_cache::propagate_cache): Call exit_range directly. + * gimple-range-cache.h (class ranger_cache): Adjust. + +2021-06-01 Andrew MacLeod <amacleod(a)redhat.com> + + * gimple-range-cache.cc (ranger_cache::ranger_cache): Adjust for + gori_compute being a member rather than base class. + dervied call to member call. + (ranger_cache::dump): No longer dump gori_map. + (ranger_cache::dump_bb): New. + (ranger_cache::get_non_stale_global_range): Adjust for gori_compute + being a member rather than base class. + (ranger_cache::set_global_range): Ditto. + (ranger_cache::ssa_range_in_bb): Ditto. + (ranger_cache::range_of_expr): New. + (ranger_cache::range_on_edge): New. + (ranger_cache::block_range): Adjust for gori_computes. Debug changes. + (ranger_cache::propagate_cache): Adjust debugging output. + (ranger_cache::fill_block_cache): Adjust for gori_computes. Debug + output changes. + * gimple-range-cache.h (class ranger_cache): Make gori_compute a + member, and inherit from range_query instead. + (ranger_cache::dump_bb): New. split from dump. + * gimple-range-gori.cc (gori_compute::ssa_range_in_bb): Delete. + (gori_compute::expr_range_at_stmt): Delete. + (gori_compute::compute_name_range_op): Delete. + (gori_compute::compute_operand_range_switch): Add fur_source. + (gori_compute::compute_operand_range): Add fur_source param, inline + old compute_name_range_op and optimize_logical_operands. + (struct tf_range): Delete. + (gori_compute::logical_combine): Adjust + (gori_compute::optimize_logical_operands): Delete. + (gori_compute::compute_logical_operands_in_chain): Delete. + (gori_compute::compute_logical_operands): Adjust. + (gori_compute::compute_operand1_range): Adjust to fur_source. + (gori_compute::compute_operand2_range): Ditto. + (gori_compute::compute_operand1_and_operand2_range): Ditto. + (gori_compute::outgoing_edge_range_p): Add range_query parameter, + and adjust to fur_source. + * gimple-range-gori.h (class gori_compute): Simplify and adjust to + range_query and fur_source. + * gimple-range.cc (gimple_ranger::range_on_edge): Query range_on_edge + from the ranger_cache.. + (gimple_ranger::fold_range_internal): Adjust to base class change of + ranger_cache. + (gimple_ranger::dump_bb): Adjust dump. + * gimple-range.h (gimple_ranger):export gori computes object. + +2021-06-01 Andrew MacLeod <amacleod(a)redhat.com> + + PR tree-optimization/100774 + * gimple-range-cache.cc (ranger_cache::get_non_stale_global_range): + Constant values are also not stale. + (ranger_cache::set_global_range): Range invariant values should also + have the correct timestamp. + 2021-05-31 Martin Liska <mliska(a)suse.cz> * tree-streamer-in.c (unpack_ts_function_decl_value_fields): diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 6b43bb2aa0c..54b764ae94c 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20210601 +20210602 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index e85a6bf2f75..cb2757c0b32 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,12 @@ +2021-06-01 Martin Liska <mliska(a)suse.cz> + + PR other/100759 + * c-attribs.c (handle_optimize_attribute): Limit sanity check + to a situation where we are not in processing of an optimize + pragma. + * c-pragma.c (handle_pragma_pop_options): Restore target + options. + 2021-05-31 Indu Bhagat <indu.bhagat(a)oracle.com> PR testsuite/100749 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index c764713465c..9a5fa7990f7 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,22 @@ +2021-06-01 Patrick Palka <ppalka(a)redhat.com> + + PR c++/65816 + * init.c (expand_aggr_init_1): Check + type_has_non_user_provided_default_constructor instead of + type_has_user_provided_constructor. + +2021-06-01 Jason Merrill <jason(a)redhat.com> + + PR c++/91859 + * call.c (build_op_delete_call): Don't set CALL_FROM_NEW_OR_DELETE_P + for destroying delete. + * init.c (build_delete): Don't clobber before destroying delete. + +2021-06-01 Jason Merrill <jason(a)redhat.com> + + PR c++/94492 + * decl2.c (cp_warn_deprecated_use): Check warning_enabled_at. + 2021-05-31 Richard Biener <rguenther(a)suse.de> PR c++/88601 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 95857ccfa8c..bab25eb7351 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,41 @@ +2021-06-01 Tobias Burnus <tobias(a)codesourcery.com> + + PR middle-end/99928 + * dump-parse-tree.c (show_omp_node, show_code_node): Handle + (parallel) master taskloop (simd). + * frontend-passes.c (gfc_code_walker): Set in_omp_workshare + to false for parallel master taskloop (simd). + * gfortran.h (enum gfc_statement): + Add ST_OMP_(END_)(PARALLEL_)MASTER_TASKLOOP(_SIMD). + (enum gfc_exec_op): EXEC_OMP_(PARALLEL_)MASTER_TASKLOOP(_SIMD). + * match.h (gfc_match_omp_master_taskloop, + gfc_match_omp_master_taskloop_simd, + gfc_match_omp_parallel_master_taskloop, + gfc_match_omp_parallel_master_taskloop_simd): New prototype. + * openmp.c (gfc_match_omp_parallel_master_taskloop, + gfc_match_omp_parallel_master_taskloop_simd, + gfc_match_omp_master_taskloop, + gfc_match_omp_master_taskloop_simd): New. + (gfc_match_omp_taskloop_simd): Permit 'reduction' clause. + (resolve_omp_clauses): Handle new combined directives; remove + inscan-reduction check to reduce multiple errors; add + task-reduction error for 'taskloop simd'. + (gfc_resolve_omp_parallel_blocks, + resolve_omp_do, omp_code_to_statement, + gfc_resolve_omp_directive): Handle new combined constructs. + * parse.c (decode_omp_directive, next_statement, + gfc_ascii_statement, parse_omp_do, parse_omp_structured_block, + parse_executable): Likewise. + * resolve.c (gfc_resolve_blocks, gfc_resolve_code): Likewise. + * st.c (gfc_free_statement): Likewise. + * trans.c (trans_code): Likewise. + * trans-openmp.c (gfc_split_omp_clauses, + gfc_trans_omp_directive): Likewise. + (gfc_trans_omp_parallel_master): Move after gfc_trans_omp_master_taskloop; + handle parallel master taskloop (simd) as well. + (gfc_trans_omp_taskloop): Take gfc_exec_op as arg. + (gfc_trans_omp_master_taskloop): New. + 2021-05-30 Gerald Pfeifer <gerald(a)pfeifer.com> * gfortran.texi (BOZ literal constants): Fix typo. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e55bbf28c9b..46dc8147391 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,64 @@ +2021-06-01 Patrick Palka <ppalka(a)redhat.com> + + PR c++/65816 + * g++.dg/cpp0x/constexpr-delegating3.C: New test. + * g++.dg/cpp0x/dc10.C: New test. + * g++.dg/cpp0x/initlist-base4.C: New test. + * g++.dg/cpp2a/constexpr-init22.C: New test. + +2021-06-01 Andrew Pinski <apinski(a)marvell.com> + + PR tree-optimization/95481 + * gcc.dg/tree-ssa/tailcall-10.c: New test. + * gcc.dg/tree-ssa/tailcall-11.c: New test. + * gcc.dg/tree-ssa/tailcall-12.c: New test. + * gcc.dg/tree-ssa/tailcall-13.c: New test. + * gcc.dg/tree-ssa/tailrecursion-8.c: New test. + +2021-06-01 Bill Schmidt <wschmidt(a)linux.ibm.com> + + PR testsuite/100750 + * gcc.target/powerpc/rop-5.c: Require ELFv2 ABI. + +2021-06-01 Jason Merrill <jason(a)redhat.com> + + PR c++/91859 + * g++.dg/cpp2a/destroying-delete5.C: New test. + +2021-06-01 Jason Merrill <jason(a)redhat.com> + + PR c++/94492 + * g++.dg/cpp0x/depr-copy4.C: New test. + +2021-06-01 Aldy Hernandez <aldyh(a)redhat.com> + + * gcc.dg/Wstringop-overflow-55.c: Adjust for global ranges changes. + * gcc.dg/pr80776-1.c: Same. + +2021-06-01 Tobias Burnus <tobias(a)codesourcery.com> + + PR middle-end/99928 + * gfortran.dg/gomp/reduction5.f90: Remove dg-error; the issue is + now diagnosed with less error output. + * gfortran.dg/gomp/scan-1.f90: Likewise. + * gfortran.dg/gomp/pr99928-3.f90: New test. + * gfortran.dg/gomp/taskloop-1.f90: New test. + +2021-06-01 liuhongt <hongtao.liu(a)intel.com> + + PR tree-optimization/98365 + * gcc.target/i386/pr98365.c: New test. + +2021-06-01 Andrew MacLeod <amacleod(a)redhat.com> + + PR tree-optimization/100781 + * gcc.dg/pr100781.c: New. + +2021-06-01 Andrew MacLeod <amacleod(a)redhat.com> + + PR tree-optimization/100774 + * g++.dg/pr100774.C: New. + 2021-05-31 Tobias Burnus <tobias(a)codesourcery.com> * gfortran.dg/gomp/depend-iterator-1.f90: Use dg-do compile. diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index e50aeb9217a..3fe0a390799 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,41 @@ +2021-06-01 Patrick Palka <ppalka(a)redhat.com> + + PR c++/65816 + * testsuite/23_containers/deque/allocator/default_init.cc, + testsuite/23_containers/forward_list/allocator/default_init.cc, + testsuite/23_containers/list/allocator/default_init.cc, + testsuite/23_containers/map/allocator/default_init.cc, + testsuite/23_containers/set/allocator/default_init.cc, + testsuite/23_containers/vector/allocator/default_init.cc, + testsuite/23_containers/vector/bool/allocator/default_init.cc: + Remove xfail. + +2021-06-01 Jonathan Wakely <jwakely(a)redhat.com> + + * testsuite/23_containers/unordered_map/96088.cc: Change + effective target to c++17. + * testsuite/23_containers/unordered_set/96088.cc: Likewise. + +2021-06-01 Jonathan Wakely <jwakely(a)redhat.com> + + * testsuite/22_locale/ctype/is/string/89728_neg.cc: Only test + isblank for C++11 and later. + +2021-06-01 Jonathan Wakely <jwakely(a)redhat.com> + + PR libstdc++/100833 + * include/bits/ranges_base.h (ranges::advance(iter, n, sentinel)): + Fix return value for no-op case. + * testsuite/24_iterators/range_operations/advance.cc: Test + return values of three-argument overload. + +2021-06-01 Jonathan Wakely <jwakely(a)redhat.com> + + PR libstdc++/99453 + * python/Makefile.am: Use archive name for printer hook if no + dynamic library name is available. + * python/Makefile.in: Regenerate. + 2021-05-30 Gerald Pfeifer <gerald(a)pfeifer.com> * doc/xml/manual/abi.xml: Remove dead reference to "Intel </cut>

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: Correct handling of variable offset minus constant in -Warray-bounds [PR100137]

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: Correct handling of variable offset minus constant in -Warray-bounds [PR100137]: commit a110855667782dac7b674d3e328b253b3b3c919b Author: Martin Sebor <msebor(a)redhat.com> Correct handling of variable offset minus constant in -Warray-bounds [PR100137] Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 20477 # First few build errors in logs: # 00:03:37 ./include/asm-generic/rwonce.h:44:26: error: array subscript 1 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 make[2]: *** [arch/arm64/mm/flush.o] Error 1 # 00:03:37 ./include/asm-generic/rwonce.h:44:26: error: array subscript 1 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 ./include/asm-generic/rwonce.h:44:26: error: array subscript 1 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 ./include/asm-generic/rwonce.h:44:26: error: array subscript 1 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 ./include/asm-generic/rwonce.h:44:26: error: array subscript 1 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 ./include/asm-generic/rwonce.h:44:26: error: array subscript 0 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 ./include/asm-generic/bitops/non-atomic.h:118:27: error: array subscript 0 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 ./include/linux/mm.h:683:23: error: array subscript 1 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] # 00:03:37 ./include/asm-generic/rwonce.h:44:26: error: array subscript 1 is outside array bounds of ‘struct page[0]’ [-Werror=array-bounds] from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 20799 # linux build successful: all THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-mainli… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-mainli… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-mainli… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-mainli… Reproduce builds: <cut> mkdir investigate-gcc-a110855667782dac7b674d3e328b253b3b3c919b cd investigate-gcc-a110855667782dac7b674d3e328b253b3b3c919b # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-mainli… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-mainli… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-mainli… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach a110855667782dac7b674d3e328b253b3b3c919b ../artifacts/test.sh # Reproduce last_good build git checkout --detach 6278065af07634278ba30029d92a82b089969baa ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit a110855667782dac7b674d3e328b253b3b3c919b Author: Martin Sebor <msebor(a)redhat.com> Date: Wed Jul 7 14:05:25 2021 -0600 Correct handling of variable offset minus constant in -Warray-bounds [PR100137] Resolves: PR tree-optimization/100137 - -Warray-bounds false positive on varying offset plus negative PR tree-optimization/99121 - ICE in -Warray-bounds on a multidimensional PR tree-optimization/97027 - missing warning on buffer overflow storing a larger scalar into a smaller array gcc/ChangeLog: PR tree-optimization/100137 PR tree-optimization/99121 PR tree-optimization/97027 * builtins.c (access_ref::access_ref): Also set offmax. (access_ref::offset_in_range): Define new function. (access_ref::add_offset): Set offmax. (access_ref::inform_access): Handle access_none. (handle_mem_ref): Clear ostype. (compute_objsize_r): Handle ASSERT_EXPR. * builtins.h (struct access_ref): Add offmax member. * gimple-array-bounds.cc (array_bounds_checker::check_mem_ref): Use compute_objsize() and simplify. gcc/testsuite/ChangeLog: PR tree-optimization/100137 PR tree-optimization/99121 PR tree-optimization/97027 * c-c++-common/Warray-bounds-3.c: Remove xfail * c-c++-common/Warray-bounds-4.c: Add an expected warning. * c-c++-common/Warray-bounds-9.c: New test. * c-c++-common/Warray-bounds-10.c: New test. * g++.dg/asan/asan_test.C: Suppress expected warnings. * g++.dg/pr95768.C: Same. * g++.dg/warn/Warray-bounds-10.C: Adjust text of expected messages. * g++.dg/warn/Warray-bounds-11.C: Same. * g++.dg/warn/Warray-bounds-12.C: Same. * g++.dg/warn/Warray-bounds-13.C: Same. * g++.dg/warn/Warray-bounds-17.C: Same. * g++.dg/warn/Warray-bounds-20.C: Same. * gcc.dg/Warray-bounds-29.c: Same. * gcc.dg/Warray-bounds-30.c: Add xfail. * gcc.dg/Warray-bounds-31.c: Adjust text of expected messages. * gcc.dg/Warray-bounds-32.c: Same. * gcc.dg/Warray-bounds-52.c: Same. * gcc.dg/Warray-bounds-53.c: Same. * gcc.dg/Warray-bounds-58.c: Remove xfail. * gcc.dg/Warray-bounds-63.c: Adjust text of expected messages. * gcc.dg/Warray-bounds-66.c: Same. * gcc.dg/Warray-bounds-69.c: Same. * gcc.dg/Wstringop-overflow-34.c: Same. * gcc.dg/Wstringop-overflow-47.c: Same. * gcc.dg/Wstringop-overflow-61.c: Same. * gcc.dg/Warray-bounds-77.c: New test. * gcc.dg/Warray-bounds-78.c: New test. * gcc.dg/Warray-bounds-79.c: New test. --- gcc/builtins.c | 69 +++++- gcc/builtins.h | 5 + gcc/gimple-array-bounds.cc | 336 ++++---------------------- gcc/testsuite/c-c++-common/Warray-bounds-10.c | 114 +++++++++ gcc/testsuite/c-c++-common/Warray-bounds-3.c | 4 +- gcc/testsuite/c-c++-common/Warray-bounds-4.c | 12 +- gcc/testsuite/c-c++-common/Warray-bounds-9.c | 144 +++++++++++ gcc/testsuite/g++.dg/asan/asan_test.C | 2 +- gcc/testsuite/g++.dg/pr95768.C | 2 +- gcc/testsuite/g++.dg/warn/Warray-bounds-10.C | 4 +- gcc/testsuite/g++.dg/warn/Warray-bounds-11.C | 4 +- gcc/testsuite/g++.dg/warn/Warray-bounds-12.C | 4 +- gcc/testsuite/g++.dg/warn/Warray-bounds-13.C | 4 +- gcc/testsuite/g++.dg/warn/Warray-bounds-17.C | 2 +- gcc/testsuite/g++.dg/warn/Warray-bounds-20.C | 8 +- gcc/testsuite/gcc.dg/Warray-bounds-29.c | 22 +- gcc/testsuite/gcc.dg/Warray-bounds-30.c | 2 +- gcc/testsuite/gcc.dg/Warray-bounds-31.c | 8 +- gcc/testsuite/gcc.dg/Warray-bounds-32.c | 26 +- gcc/testsuite/gcc.dg/Warray-bounds-52.c | 6 +- gcc/testsuite/gcc.dg/Warray-bounds-53.c | 6 +- gcc/testsuite/gcc.dg/Warray-bounds-58.c | 2 +- gcc/testsuite/gcc.dg/Warray-bounds-63.c | 6 +- gcc/testsuite/gcc.dg/Warray-bounds-66.c | 12 +- gcc/testsuite/gcc.dg/Warray-bounds-69.c | 2 +- gcc/testsuite/gcc.dg/Warray-bounds-77.c | 135 +++++++++++ gcc/testsuite/gcc.dg/Warray-bounds-78.c | 109 +++++++++ gcc/testsuite/gcc.dg/Warray-bounds-79.c | 112 +++++++++ gcc/testsuite/gcc.dg/Wstringop-overflow-34.c | 8 +- gcc/testsuite/gcc.dg/Wstringop-overflow-47.c | 14 +- gcc/testsuite/gcc.dg/Wstringop-overflow-61.c | 4 +- 31 files changed, 817 insertions(+), 371 deletions(-) diff --git a/gcc/builtins.c b/gcc/builtins.c index e52fe4291c8..39ab139b7e1 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -206,6 +206,7 @@ access_ref::access_ref (tree bound /* = NULL_TREE */, { /* Set to valid. */ offrng[0] = offrng[1] = 0; + offmax[0] = offmax[1] = 0; /* Invalidate. */ sizrng[0] = sizrng[1] = -1; @@ -457,6 +458,21 @@ access_ref::size_remaining (offset_int *pmin /* = NULL */) const return sizrng[1] - or0; } +/* Return true if the offset and object size are in range for SIZE. */ + +bool +access_ref::offset_in_range (const offset_int &size) const +{ + if (size_remaining () < size) + return false; + + if (base0) + return offmax[0] >= 0 && offmax[1] <= sizrng[1]; + + offset_int maxoff = wi::to_offset (TYPE_MAX_VALUE (ptrdiff_type_node)); + return offmax[0] > -maxoff && offmax[1] < maxoff; +} + /* Add the range [MIN, MAX] to the offset range. For known objects (with zero-based offsets) at least one of whose offset's bounds is in range, constrain the other (or both) to the bounds of the object (i.e., zero @@ -493,6 +509,8 @@ void access_ref::add_offset (const offset_int &min, const offset_int &max) if (max >= 0) { offrng[0] = 0; + if (offmax[0] > 0) + offmax[0] = 0; return; } @@ -509,6 +527,12 @@ void access_ref::add_offset (const offset_int &min, const offset_int &max) offrng[0] = 0; } + /* Set the minimum and maximmum computed so far. */ + if (offrng[1] < 0 && offrng[1] < offmax[0]) + offmax[0] = offrng[1]; + if (offrng[0] > 0 && offrng[0] > offmax[1]) + offmax[1] = offrng[0]; + if (!base0) return; @@ -4571,23 +4595,46 @@ access_ref::inform_access (access_mode mode) const return; } + if (mode == access_read_only) + { + if (allocfn == NULL_TREE) + { + if (*offstr) + inform (loc, "at offset %s into source object %qE of size %s", + offstr, ref, sizestr); + else + inform (loc, "source object %qE of size %s", ref, sizestr); + + return; + } + + if (*offstr) + inform (loc, + "at offset %s into source object of size %s allocated by %qE", + offstr, sizestr, allocfn); + else + inform (loc, "source object of size %s allocated by %qE", + sizestr, allocfn); + return; + } + if (allocfn == NULL_TREE) { if (*offstr) - inform (loc, "at offset %s into source object %qE of size %s", + inform (loc, "at offset %s into object %qE of size %s", offstr, ref, sizestr); else - inform (loc, "source object %qE of size %s", ref, sizestr); + inform (loc, "object %qE of size %s", ref, sizestr); return; } if (*offstr) inform (loc, - "at offset %s into source object of size %s allocated by %qE", + "at offset %s into object of size %s allocated by %qE", offstr, sizestr, allocfn); else - inform (loc, "source object of size %s allocated by %qE", + inform (loc, "object of size %s allocated by %qE", sizestr, allocfn); } @@ -5433,16 +5480,16 @@ handle_mem_ref (tree mref, int ostype, access_ref *pref, if (VECTOR_TYPE_P (TREE_TYPE (mref))) { - /* Hack: Give up for MEM_REFs of vector types; those may be - synthesized from multiple assignments to consecutive data - members (see PR 93200 and 96963). + /* Hack: Handle MEM_REFs of vector types as those to complete + objects; those may be synthesized from multiple assignments + to consecutive data members (see PR 93200 and 96963). FIXME: Vectorized assignments should only be present after vectorization so this hack is only necessary after it has run and could be avoided in calls from prior passes (e.g., tree-ssa-strlen.c). FIXME: Deal with this more generally, e.g., by marking up such MEM_REFs at the time they're created. */ - return false; + ostype = 0; } tree mrefop = TREE_OPERAND (mref, 0); @@ -5796,6 +5843,12 @@ compute_objsize_r (tree ptr, int ostype, access_ref *pref, tree rhs = gimple_assign_rhs1 (stmt); + if (code == ASSERT_EXPR) + { + rhs = TREE_OPERAND (rhs, 0); + return compute_objsize_r (rhs, ostype, pref, snlim, qry); + } + if (code == POINTER_PLUS_EXPR && TREE_CODE (TREE_TYPE (rhs)) == POINTER_TYPE) { diff --git a/gcc/builtins.h b/gcc/builtins.h index e71f40c300a..a64ece3f1cd 100644 --- a/gcc/builtins.h +++ b/gcc/builtins.h @@ -222,6 +222,9 @@ struct access_ref argument to the minimum. */ offset_int size_remaining (offset_int * = NULL) const; +/* Return true if the offset and object size are in range for SIZE. */ + bool offset_in_range (const offset_int &) const; + /* Return true if *THIS is an access to a declared object. */ bool ref_declared () const { @@ -261,6 +264,8 @@ struct access_ref /* Range of byte offsets into and sizes of the object(s). */ offset_int offrng[2]; offset_int sizrng[2]; + /* The minimum and maximum offset computed. */ + offset_int offmax[2]; /* Range of the bound of the access: denotes that the access is at least BNDRNG[0] bytes but no more than BNDRNG[1]. For string functions the size of the actual access is diff --git a/gcc/gimple-array-bounds.cc b/gcc/gimple-array-bounds.cc index 13f08685f8f..83b8db9755e 100644 --- a/gcc/gimple-array-bounds.cc +++ b/gcc/gimple-array-bounds.cc @@ -414,269 +414,72 @@ array_bounds_checker::check_mem_ref (location_t location, tree ref, if (warning_suppressed_p (ref, OPT_Warray_bounds)) return false; - tree arg = TREE_OPERAND (ref, 0); - /* The constant and variable offset of the reference. */ - tree cstoff = TREE_OPERAND (ref, 1); - tree varoff = NULL_TREE; - - const offset_int maxobjsize = tree_to_shwi (max_object_size ()); - - /* The zero-based array or string constant bounds in bytes. Initially - set to [-MAXOBJSIZE - 1, MAXOBJSIZE] until a tighter bound is - determined. */ - offset_int arrbounds[2] = { -maxobjsize - 1, maxobjsize }; - - /* The minimum and maximum intermediate offset. For a reference - to be valid, not only does the final offset/subscript must be - in bounds but all intermediate offsets should be as well. - GCC may be able to deal gracefully with such out-of-bounds - offsets so the checking is only enabled at -Warray-bounds=2 - where it may help detect bugs in uses of the intermediate - offsets that could otherwise not be detectable. */ - offset_int ioff = wi::to_offset (fold_convert (ptrdiff_type_node, cstoff)); - offset_int extrema[2] = { 0, wi::abs (ioff) }; - - /* The range of the byte offset into the reference. */ - offset_int offrange[2] = { 0, 0 }; - /* The statement used to allocate the array or null. */ gimple *alloc_stmt = NULL; /* For an allocation statement, the low bound of the size range. */ offset_int minbound = 0; + /* The type and size of the access. */ + tree axstype = TREE_TYPE (ref); + offset_int axssize = 0; + if (TREE_CODE (axstype) != UNION_TYPE) + if (tree access_size = TYPE_SIZE_UNIT (axstype)) + if (TREE_CODE (access_size) == INTEGER_CST) + axssize = wi::to_offset (access_size); - /* Determine the offsets and increment OFFRANGE for the bounds of each. - The loop computes the range of the final offset for expressions such - as (A + i0 + ... + iN)[CSTOFF] where i0 through iN are SSA_NAMEs in - some range. */ - const unsigned limit = param_ssa_name_def_chain_limit; - for (unsigned n = 0; TREE_CODE (arg) == SSA_NAME && n < limit; ++n) - { - gimple *def = SSA_NAME_DEF_STMT (arg); - if (is_gimple_call (def)) - { - /* Determine the byte size of the array from an allocation call. */ - wide_int sizrng[2]; - if (gimple_call_alloc_size (def, sizrng)) - { - arrbounds[0] = 0; - arrbounds[1] = offset_int::from (sizrng[1], UNSIGNED); - minbound = offset_int::from (sizrng[0], UNSIGNED); - alloc_stmt = def; - } - break; - } - - if (gimple_nop_p (def)) - { - /* For a function argument try to determine the byte size - of the array from the current function declaratation - (e.g., attribute access or related). */ - wide_int wr[2]; - tree ref = gimple_parm_array_size (arg, wr); - if (!ref) - break; - arrbounds[0] = offset_int::from (wr[0], UNSIGNED); - arrbounds[1] = offset_int::from (wr[1], UNSIGNED); - arg = ref; - break; - } - - if (!is_gimple_assign (def)) - break; - - tree_code code = gimple_assign_rhs_code (def); - if (code == POINTER_PLUS_EXPR) - { - arg = gimple_assign_rhs1 (def); - varoff = gimple_assign_rhs2 (def); - } - else if (code == ASSERT_EXPR) - { - arg = TREE_OPERAND (gimple_assign_rhs1 (def), 0); - continue; - } - else - return false; - - /* VAROFF should always be a SSA_NAME here (and not even - INTEGER_CST) but there's no point in taking chances. */ - if (TREE_CODE (varoff) != SSA_NAME) - break; - - const value_range* const vr = get_value_range (varoff); - if (!vr || vr->undefined_p () || vr->varying_p ()) - break; - - if (!vr->constant_p ()) - break; - - if (vr->kind () == VR_RANGE) - { - offset_int min - = wi::to_offset (fold_convert (ptrdiff_type_node, vr->min ())); - offset_int max - = wi::to_offset (fold_convert (ptrdiff_type_node, vr->max ())); - if (min < max) - { - offrange[0] += min; - offrange[1] += max; - } - else - { - /* When MIN >= MAX, the offset is effectively in a union - of two ranges: [-MAXOBJSIZE -1, MAX] and [MIN, MAXOBJSIZE]. - Since there is no way to represent such a range across - additions, conservatively add [-MAXOBJSIZE -1, MAXOBJSIZE] - to OFFRANGE. */ - offrange[0] += arrbounds[0]; - offrange[1] += arrbounds[1]; - } - } - else - { - /* For an anti-range, analogously to the above, conservatively - add [-MAXOBJSIZE -1, MAXOBJSIZE] to OFFRANGE. */ - offrange[0] += arrbounds[0]; - offrange[1] += arrbounds[1]; - } - - /* Keep track of the minimum and maximum offset. */ - if (offrange[1] < 0 && offrange[1] < extrema[0]) - extrema[0] = offrange[1]; - if (offrange[0] > 0 && offrange[0] > extrema[1]) - extrema[1] = offrange[0]; - - if (offrange[0] < arrbounds[0]) - offrange[0] = arrbounds[0]; - - if (offrange[1] > arrbounds[1]) - offrange[1] = arrbounds[1]; - } + access_ref aref; + if (!compute_objsize (ref, 1, &aref, ranges)) + return false; - tree reftype = NULL_TREE; - offset_int eltsize = -1; - if (arrbounds[0] >= 0) - { - /* The byte size of the array has already been determined above - based on a pointer ARG. Set ELTSIZE to the size of the type - it points to and REFTYPE to the array with the size, rounded - down as necessary. */ - reftype = TREE_TYPE (TREE_TYPE (arg)); - if (TREE_CODE (reftype) == ARRAY_TYPE) - reftype = TREE_TYPE (reftype); - if (tree refsize = TYPE_SIZE_UNIT (reftype)) - if (TREE_CODE (refsize) == INTEGER_CST) - eltsize = wi::to_offset (refsize); - - if (eltsize < 0) - return false; + if (aref.offset_in_range (axssize)) + return false; - offset_int nelts = arrbounds[1] / eltsize; - reftype = build_printable_array_type (reftype, nelts.to_uhwi ()); - } - else if (TREE_CODE (arg) == ADDR_EXPR) + if (TREE_CODE (aref.ref) == SSA_NAME) { - arg = TREE_OPERAND (arg, 0); - if (TREE_CODE (arg) != STRING_CST - && TREE_CODE (arg) != PARM_DECL - && TREE_CODE (arg) != VAR_DECL) - return false; - - /* The type of the object being referred to. It can be an array, - string literal, or a non-array type when the MEM_REF represents - a reference/subscript via a pointer to an object that is not - an element of an array. Incomplete types are excluded as well - because their size is not known. */ - reftype = TREE_TYPE (arg); - if (POINTER_TYPE_P (reftype) - || !COMPLETE_TYPE_P (reftype) - || TREE_CODE (TYPE_SIZE_UNIT (reftype)) != INTEGER_CST) - return false; - - /* Except in declared objects, references to trailing array members - of structs and union objects are excluded because MEM_REF doesn't - make it possible to identify the member where the reference - originated. */ - if (RECORD_OR_UNION_TYPE_P (reftype) - && (!VAR_P (arg) - || (DECL_EXTERNAL (arg) && array_at_struct_end_p (ref)))) - return false; - - /* FIXME: Should this be 1 for Fortran? */ - arrbounds[0] = 0; - - if (TREE_CODE (reftype) == ARRAY_TYPE) - { - /* Set to the size of the array element (and adjust below). */ - eltsize = wi::to_offset (TYPE_SIZE_UNIT (TREE_TYPE (reftype))); - /* Use log2 of size to convert the array byte size in to its - upper bound in elements. */ - const offset_int eltsizelog2 = wi::floor_log2 (eltsize); - if (tree dom = TYPE_DOMAIN (reftype)) - { - tree bnds[] = { TYPE_MIN_VALUE (dom), TYPE_MAX_VALUE (dom) }; - if (TREE_CODE (arg) == COMPONENT_REF) - { - offset_int size = maxobjsize; - if (tree fldsize = component_ref_size (arg)) - size = wi::to_offset (fldsize); - arrbounds[1] = wi::lrshift (size, eltsizelog2); - } - else if (array_at_struct_end_p (arg) || !bnds[0] || !bnds[1]) - arrbounds[1] = wi::lrshift (maxobjsize, eltsizelog2); - else - arrbounds[1] = (wi::to_offset (bnds[1]) - wi::to_offset (bnds[0]) - + 1) * eltsize; - } - else - arrbounds[1] = wi::lrshift (maxobjsize, eltsizelog2); - - /* Determine a tighter bound of the non-array element type. */ - tree eltype = TREE_TYPE (reftype); - while (TREE_CODE (eltype) == ARRAY_TYPE) - eltype = TREE_TYPE (eltype); - eltsize = wi::to_offset (TYPE_SIZE_UNIT (eltype)); - } - else + gimple *def = SSA_NAME_DEF_STMT (aref.ref); + if (is_gimple_call (def)) { - eltsize = 1; - tree size = TYPE_SIZE_UNIT (reftype); - if (VAR_P (arg)) - if (tree initsize = DECL_SIZE_UNIT (arg)) - if (tree_int_cst_lt (size, initsize)) - size = initsize; - - arrbounds[1] = wi::to_offset (size); + /* Save the allocation call and the low bound on the size. */ + alloc_stmt = def; + minbound = aref.sizrng[0]; } } - else - return false; - - offrange[0] += ioff; - offrange[1] += ioff; + + /* The range of the byte offset into the reference. Adjusted below. */ + offset_int offrange[2] = { aref.offrng[0], aref.offrng[1] }; + + /* The type of the referenced object. */ + tree reftype = TREE_TYPE (aref.ref); + /* The size of the referenced array element. */ + offset_int eltsize = 1; + /* The byte size of the array has already been determined above + based on a pointer ARG. Set ELTSIZE to the size of the type + it points to and REFTYPE to the array with the size, rounded + down as necessary. */ + if (POINTER_TYPE_P (reftype)) + reftype = TREE_TYPE (reftype); + if (TREE_CODE (reftype) == ARRAY_TYPE) + reftype = TREE_TYPE (reftype); + if (tree refsize = TYPE_SIZE_UNIT (reftype)) + if (TREE_CODE (refsize) == INTEGER_CST) + eltsize = wi::to_offset (refsize); + + const offset_int nelts = aref.sizrng[1] / eltsize; + reftype = build_printable_array_type (reftype, nelts.to_uhwi ()); /* Compute the more permissive upper bound when IGNORE_OFF_BY_ONE is set (when taking the address of the one-past-last element of an array) but always use the stricter bound in diagnostics. */ - offset_int ubound = arrbounds[1]; + offset_int ubound = aref.sizrng[1]; if (ignore_off_by_one) ubound += eltsize; - bool warned = false; /* Set if the lower bound of the subscript is out of bounds. */ - const bool lboob = (arrbounds[0] == arrbounds[1] + const bool lboob = (aref.sizrng[1] == 0 || offrange[0] >= ubound - || offrange[1] < arrbounds[0]); + || offrange[1] < 0); /* Set if only the upper bound of the subscript is out of bounds. This can happen when using a bigger type to index into an array of a smaller type, as is common with unsigned char. */ - tree axstype = TREE_TYPE (ref); - offset_int axssize = 0; - if (TREE_CODE (axstype) != UNION_TYPE) - if (tree access_size = TYPE_SIZE_UNIT (axstype)) - if (TREE_CODE (access_size) == INTEGER_CST) - axssize = wi::to_offset (access_size); - const bool uboob = !lboob && offrange[0] + axssize > ubound; if (lboob || uboob) { @@ -689,9 +492,7 @@ array_bounds_checker::check_mem_ref (location_t location, tree ref, to compute the index to print in the diagnostic; arrays in MEM_REF don't mean anything. A type with no size like void is as good as having a size of 1. */ - tree type = TREE_TYPE (ref); - while (TREE_CODE (type) == ARRAY_TYPE) - type = TREE_TYPE (type); + tree type = strip_array_types (TREE_TYPE (ref)); if (tree size = TYPE_SIZE_UNIT (type)) { offrange[0] = offrange[0] / wi::to_offset (size); @@ -699,6 +500,7 @@ array_bounds_checker::check_mem_ref (location_t location, tree ref, } } + bool warned = false; if (lboob) { if (offrange[0] == offrange[1]) @@ -720,7 +522,7 @@ array_bounds_checker::check_mem_ref (location_t location, tree ref, /* If the memory was dynamically allocated refer to it as if it were an untyped array of bytes. */ backtype = build_array_type_nelts (unsigned_char_type_node, - arrbounds[1].to_uhwi ()); + aref.sizrng[1].to_uhwi ()); warned = warning_at (location, OPT_Warray_bounds, "array subscript %<%T[%wi]%> is partly " @@ -730,46 +532,8 @@ array_bounds_checker::check_mem_ref (location_t location, tree ref, if (warned) { - if (DECL_P (arg)) - inform (DECL_SOURCE_LOCATION (arg), "while referencing %qD", arg); - else if (alloc_stmt) - { - location_t loc = gimple_location (alloc_stmt); - if (gimple_call_builtin_p (alloc_stmt, BUILT_IN_ALLOCA_WITH_ALIGN)) - { - if (minbound == arrbounds[1]) - inform (loc, "referencing a variable length array " - "of size %wu", minbound.to_uhwi ()); - else - inform (loc, "referencing a variable length array " - "of size between %wu and %wu", - minbound.to_uhwi (), arrbounds[1].to_uhwi ()); - } - else if (tree fndecl = gimple_call_fndecl (alloc_stmt)) - { - if (minbound == arrbounds[1]) - inform (loc, "referencing an object of size %wu " - "allocated by %qD", - minbound.to_uhwi (), fndecl); - else - inform (loc, "referencing an object of size between " - "%wu and %wu allocated by %qD", - minbound.to_uhwi (), arrbounds[1].to_uhwi (), fndecl); - } - else - { - tree fntype = gimple_call_fntype (alloc_stmt); - if (minbound == arrbounds[1]) - inform (loc, "referencing an object of size %wu " - "allocated by %qT", - minbound.to_uhwi (), fntype); - else - inform (loc, "referencing an object of size between " - "%wu and %wu allocated by %qT", - minbound.to_uhwi (), arrbounds[1].to_uhwi (), fntype); - } - } - + /* TODO: Determine the access from the statement and use it. */ + aref.inform_access (access_none); suppress_warning (ref, OPT_Warray_bounds); return true; } @@ -779,9 +543,9 @@ array_bounds_checker::check_mem_ref (location_t location, tree ref, /* At level 2 check also intermediate offsets. */ int i = 0; - if (extrema[i] < -arrbounds[1] || extrema[i = 1] > ubound) + if (aref.offmax[i] < -aref.sizrng[1] || aref.offmax[i = 1] > ubound) { - HOST_WIDE_INT tmpidx = extrema[i].to_shwi () / eltsize.to_shwi (); + HOST_WIDE_INT tmpidx = aref.offmax[i].to_shwi () / eltsize.to_shwi (); if (warning_at (location, OPT_Warray_bounds, "intermediate array offset %wi is outside array bounds " diff --git a/gcc/testsuite/c-c++-common/Warray-bounds-10.c b/gcc/testsuite/c-c++-common/Warray-bounds-10.c new file mode 100644 index 00000000000..cfe9a383410 --- /dev/null +++ b/gcc/testsuite/c-c++-common/Warray-bounds-10.c @@ -0,0 +1,114 @@ +/* PR tree-optimization/99475 - bogus -Warray-bounds accessing an array + element of empty structs + { dg-do compile } + { dg-options "-O2 -Wall" } */ + +struct S +{ +#if SOME_CONFIG_MACRO + /* Suppose the contents are empty in the development configuration + but non-empty in others. Out of bounds accesses to elements of + the arrays below should be diagnosed in all configurations, + including when S is empty, even if they are folded away. */ + int member; +#endif +}; + +extern struct S sa3[3]; +extern struct S sa2_3[2][3]; +extern struct S sa3_4_5[3][4][5]; + +void sink (void*); + + +void access_sa3 (struct S s) +{ + sa3[0] = s; + sa3[1] = s; + sa3[2] = s; + sa3[3] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } +} + +void access_sa3_ptr (struct S s) +{ + struct S *p = &sa3[0]; + + p[0] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[1] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[2] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[3] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } +} + +void access_sa2_3_ptr (struct S s) +{ + struct S *p = &sa2_3[0][0]; + + p[0] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[1] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[2] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[6] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } +} + +void access_sa3_4_5_ptr (struct S s, int i) +{ + struct S *p = &sa3_4_5[0][0][0]; + + p[0] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[1] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[2] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[60] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } +} + + +void access_vla3 (struct S s, unsigned n) +{ + struct S vla3[3 < n ? 3 : n]; + + vla3[0] = s; + vla3[1] = s; + vla3[2] = s; + vla3[3] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } + + sink (vla3); +} + +void access_vla3_ptr (struct S s, unsigned n) +{ + struct S vla3[3 < n ? 3 : n]; + struct S *p = &vla3[0]; + + p[0] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[1] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[2] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[3] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } + + sink (vla3); +} + +void access_vla2_3_ptr (struct S s, unsigned n) +{ + struct S vla2_3[2 < n ? 2 : n][3 < n ? 3 : n]; + struct S *p = &vla2_3[0][0]; + + p[0] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[1] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[2] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[6] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } + + sink (vla2_3); +} + +void access_vla3_4_5_ptr (struct S s, unsigned n) +{ + struct S vla3_4_5[3 < n ? 3 : n][4 < n ? 4 : n][5 < n ? 5 : n]; + struct S *p = &vla3_4_5[0][0][0]; + + p[0] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[1] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[2] = s; // { dg-bogus "\\\[-Warray-bounds" } + p[60] = s; // { dg-warning "\\\[-Warray-bounds" "pr?????" { xfail *-*-* } } + + sink (vla3_4_5); +} + +// { dg-prune-output "empty struct has size 0 in C" } diff --git a/gcc/testsuite/c-c++-common/Warray-bounds-3.c b/gcc/testsuite/c-c++-common/Warray-bounds-3.c index aae4999ea13..3d7c7687374 100644 --- a/gcc/testsuite/c-c++-common/Warray-bounds-3.c +++ b/gcc/testsuite/c-c++-common/Warray-bounds-3.c @@ -158,7 +158,7 @@ void test_memcpy_overflow (char *d, const char *s, size_t n) but known access size is detected. This works except with small sizes that are powers of 2 due to bug . */ T (char, 1, arr + SR (DIFF_MAX - 1, DIFF_MAX), s, 1); - T (char, 1, arr + SR (DIFF_MAX - 1, DIFF_MAX), s, 2); /* { dg-warning "pointer overflow between offset \\\[\[0-9\]+, \[0-9\]+] and size 2 accessing array " "bug " { xfail non_strict_align } } */ + T (char, 1, arr + SR (DIFF_MAX - 1, DIFF_MAX), s, 2); /* { dg-warning "\\\[-Warray-bounds" } */ T (char, 1, arr + SR (DIFF_MAX - 2, DIFF_MAX), s, 3); /* { dg-warning "pointer overflow between offset \\\[\[0-9\]+, \[0-9\]+] and size 3 accessing array " "memcpy" } */ T (char, 1, arr + SR (DIFF_MAX - 4, DIFF_MAX), s, 5); /* { dg-warning "pointer overflow between offset \\\[\[0-9\]+, \[0-9\]+] and size 5 accessing array " "memcpy" } */ } @@ -178,7 +178,7 @@ void test_memcpy_bounds_memarray_range (void) TM (ma.a5, ma.a5 + i, ma.a5, 1); TM (ma.a5, ma.a5 + i, ma.a5, 3); - TM (ma.a5, ma.a5 + i, ma.a5, 5); + TM (ma.a5, ma.a5 + i, ma.a5, 5); /* { dg-warning "\\\[-Warray-bounds" } */ TM (ma.a5, ma.a5 + i, ma.a5, 7); /* diagnosed with -Warray-bounds=2 */ } diff --git a/gcc/testsuite/c-c++-common/Warray-bounds-4.c b/gcc/testsuite/c-c++-common/Warray-bounds-4.c index 22a23a12651..1f73f11943f 100644 --- a/gcc/testsuite/c-c++-common/Warray-bounds-4.c +++ b/gcc/testsuite/c-c++-common/Warray-bounds-4.c @@ -43,7 +43,17 @@ void test_memcpy_bounds_memarray_range (void) TM (ma.a5, ma.a5 + j, ma.a5, 1); TM (ma.a5, ma.a5 + j, ma.a5, 3); - TM (ma.a5, ma.a5 + j, ma.a5, 5); + + /* The copy below is invalid for two reasons: 1) it overlaps and 2) it + writes past the end of ma.a5. The warning is a little cryptic here + because the GIMPLE is: + _4 = &ma.a5 + prephitmp_14; + MEM <unsigned char[5]> [(char * {ref-all})_4] + = MEM <unsigned char[5]> [(char * {ref-all})&ma]; + and could be improved. Just verify that one is issued but not its + full text. */ + TM (ma.a5, ma.a5 + j, ma.a5, 5); /* { dg-warning "\\\[-Warray-bounds" } */ + TM (ma.a5, ma.a5 + j, ma.a5, 7); /* { dg-warning "offset \\\[5, 7] from the object at .ma. is out of the bounds of referenced subobject .$MA::$?a5. with type .char ?\\\[5]. at offset 0" } */ TM (ma.a5, ma.a5 + j, ma.a5, 9); /* { dg-warning "offset \\\[5, 9] from the object at .ma. is out of the bounds of referenced subobject .$MA::$?a5. with type .char ?\\\[5]. at offset 0" } */ } diff --git a/gcc/testsuite/c-c++-common/Warray-bounds-9.c b/gcc/testsuite/c-c++-common/Warray-bounds-9.c new file mode 100644 index 00000000000..be05775fa91 --- /dev/null +++ b/gcc/testsuite/c-c++-common/Warray-bounds-9.c @@ -0,0 +1,144 @@ +/* PR tree-optimization/99121 - ICE in -Warray-bounds on a multidimensional + VLA + { dg-do compile } + { dg-options "-O2 -Wall -ftrack-macro-expansion=0" } */ + +#define NOIPA __attribute__ ((noipa)) + +void sink (void*, ...); +#define T(a, x) sink (a, x) + + +NOIPA void a_0_n (int n) +{ + int a[0][n]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_n_0 (int n) +{ + int a[n][0]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + + +NOIPA void a_1_n_0 (int n) +{ + int a[1][n][0]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_1_0_n (int n) +{ + int a[1][0][n]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_0_1_n (int n) +{ + int a[0][1][n]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_0_n_1 (int n) +{ + int a[0][n][1]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_n_0_n (int n) +{ + int a[n][0][n]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_n_n_0 (int n) +{ + int a[n][n][0]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_0_n_n (int n) +{ + int a[0][n][n]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_0_0_n (int n) +{ + int a[0][0][n]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_n_0_0 (int n) +{ + int a[n][0][0]; + + sink (a); + + T (a, ((int *) a)[0]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((char *) a)[1]); // { dg-warning "\\\[-Warray-bounds" } + T (a, ((float *) a)[n]); // { dg-warning "\\\[-Warray-bounds" } +} + +NOIPA void a_n_n_n (int n) +{ + int a[n][n][n]; + + sink (a); + + T (a, ((int *) a)[-1]); // { dg-warning "\\\[-Warray-bounds" "pr99140" } + T (a, ((int *) a)[0]); + T (a, ((char *) a)[1]); + T (a, ((float *) a)[n]); +} diff --git a/gcc/testsuite/g++.dg/asan/asan_test.C b/gcc/testsuite/g++.dg/asan/asan_test.C index c62568f48ec..49933ab8e4d 100644 --- a/gcc/testsuite/g++.dg/asan/asan_test.C +++ b/gcc/testsuite/g++.dg/asan/asan_test.C @@ -2,7 +2,7 @@ // { dg-skip-if "" { *-*-* } { "*" } { "-O2" } } // { dg-skip-if "" { *-*-* } { "-flto" } { "" } } // { dg-additional-sources "asan_globals_test-wrapper.cc" } -// { dg-options "-std=c++11 -fsanitize=address -fno-builtin -Wall -Werror -Wno-alloc-size-larger-than -Wno-stringop-overflow -g -DASAN_UAR=0 -DASAN_HAS_EXCEPTIONS=1 -DASAN_HAS_BLACKLIST=0 -DSANITIZER_USE_DEJAGNU_GTEST=1 -lasan -lpthread" } +// { dg-options "-std=c++11 -fsanitize=address -fno-builtin -Wall -Werror -Wno-alloc-size-larger-than -Wno-array-bounds -Wno-stringop-overflow -g -DASAN_UAR=0 -DASAN_HAS_EXCEPTIONS=1 -DASAN_HAS_BLACKLIST=0 -DSANITIZER_USE_DEJAGNU_GTEST=1 -lasan -lpthread" } // { dg-additional-options "-ldl" { target { ! *-*-freebsd* } } } // { dg-additional-options "-DASAN_NEEDS_SEGV=1" { target { ! arm*-*-* } } } // { dg-additional-options "-DASAN_LOW_MEMORY=1 -DASAN_NEEDS_SEGV=0" { target arm*-*-* } } diff --git a/gcc/testsuite/g++.dg/pr95768.C b/gcc/testsuite/g++.dg/pr95768.C index 5e2c8c44ad0..d34d5133134 100644 --- a/gcc/testsuite/g++.dg/pr95768.C +++ b/gcc/testsuite/g++.dg/pr95768.C @@ -1,6 +1,6 @@ /* PR c++/95768 - pretty-printer ICE on -Wuninitialized with allocated storage { dg-do compile } - { dg-options "-O2 -Wall" } */ + { dg-options "-O2 -Wall -Wno-array-bounds" } */ </cut>

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: phiopt: Optimize partial_ordering spaceship >= 0 -ffinite-math-only [PR94589]

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: phiopt: Optimize partial_ordering spaceship >= 0 -ffinite-math-only [PR94589]: commit 65061ea287a80cfb214e402cfd2373a14bfec95a Author: Jakub Jelinek <jakub(a)redhat.com> phiopt: Optimize partial_ordering spaceship >= 0 -ffinite-math-only [PR94589] Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:01:16 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:01:16 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:01:16 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:01:16 make[2]: *** [scripts/gcc-plugins/stackleak_plugin.so] Error 1 # 00:01:16 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:01:16 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:01:16 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:01:17 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 21070 # linux build successful: all THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-aarch64-next-allyesconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… Reproduce builds: <cut> mkdir investigate-gcc-65061ea287a80cfb214e402cfd2373a14bfec95a cd investigate-gcc-65061ea287a80cfb214e402cfd2373a14bfec95a # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-aarch64-next-a… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach 65061ea287a80cfb214e402cfd2373a14bfec95a ../artifacts/test.sh # Reproduce last_good build git checkout --detach b2a09773155892e426b90ce8367e2ed6996b44ef ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit 65061ea287a80cfb214e402cfd2373a14bfec95a Author: Jakub Jelinek <jakub(a)redhat.com> Date: Tue May 18 10:08:51 2021 +0200 phiopt: Optimize partial_ordering spaceship >= 0 -ffinite-math-only [PR94589] As mentioned earlier, spaceship_replacement didn't optimize partial_ordering >= 0 comparisons, because the possible values are -1, 0, 1, 2 and the >= comparison is implemented as (res & 1) == res to choose the 0 and 1 cases from that. As we optimize that only with -ffinite-math-only, the 2 case is assumed not to happen and my earlier match.pd change optimizes (res & 1) == res into (res & ~1) == 0, so this patch pattern matches that case and handles it like res >= 0. 2021-05-18 Jakub Jelinek <jakub(a)redhat.com> PR tree-optimization/94589 * tree-ssa-phiopt.c (spaceship_replacement): Pattern match phi result used in (res & ~1) == 0 comparison as res >= 0 as res == 2 would be UB with -ffinite-math-only. * g++.dg/opt/pr94589-2.C: Adjust scan-tree-dump count from 14 to 12. --- gcc/testsuite/g++.dg/opt/pr94589-2.C | 4 +- gcc/tree-ssa-phiopt.c | 72 +++++++++++++++++++++++++++++++----- 2 files changed, 65 insertions(+), 11 deletions(-) diff --git a/gcc/testsuite/g++.dg/opt/pr94589-2.C b/gcc/testsuite/g++.dg/opt/pr94589-2.C index dda947e22b1..e9ef84b1912 100644 --- a/gcc/testsuite/g++.dg/opt/pr94589-2.C +++ b/gcc/testsuite/g++.dg/opt/pr94589-2.C @@ -1,8 +1,8 @@ // PR tree-optimization/94589 // { dg-do compile { target c++20 } } // { dg-options "-O2 -g0 -ffast-math -fdump-tree-optimized" } -// { dg-final { scan-tree-dump-times "\[ij]_\[0-9]+\$D\$ (?:<|<=|==|!=|>|>=) \[ij]_\[0-9]+\$D\$" 14 "optimized" } } -// { dg-final { scan-tree-dump-times "i_\[0-9]+\$D\$ (?:<|<=|==|!=|>|>=) 5\\.0" 14 "optimized" } } +// { dg-final { scan-tree-dump-times "\[ij]_\[0-9]+\$D\$ (?:<|<=|==|!=|>|>=) \[ij]_\[0-9]+\$D\$" 12 "optimized" } } +// { dg-final { scan-tree-dump-times "i_\[0-9]+\$D\$ (?:<|<=|==|!=|>|>=) 5\\.0" 12 "optimized" } } #include <compare> diff --git a/gcc/tree-ssa-phiopt.c b/gcc/tree-ssa-phiopt.c index e0a41d41fba..8e8a08bc679 100644 --- a/gcc/tree-ssa-phiopt.c +++ b/gcc/tree-ssa-phiopt.c @@ -1887,8 +1887,9 @@ spaceship_replacement (basic_block cond_bb, basic_block middle_bb, edge e0, edge e1, gphi *phi, tree arg0, tree arg1) { - if (!INTEGRAL_TYPE_P (TREE_TYPE (PHI_RESULT (phi))) - || TYPE_UNSIGNED (TREE_TYPE (PHI_RESULT (phi))) + tree phires = PHI_RESULT (phi); + if (!INTEGRAL_TYPE_P (TREE_TYPE (phires)) + || TYPE_UNSIGNED (TREE_TYPE (phires)) || !tree_fits_shwi_p (arg0) || !tree_fits_shwi_p (arg1) || !IN_RANGE (tree_to_shwi (arg0), -1, 2) @@ -1902,12 +1903,32 @@ spaceship_replacement (basic_block cond_bb, basic_block middle_bb, use_operand_p use_p; gimple *use_stmt; - if (SSA_NAME_OCCURS_IN_ABNORMAL_PHI (PHI_RESULT (phi))) + if (SSA_NAME_OCCURS_IN_ABNORMAL_PHI (phires)) return false; - if (!single_imm_use (PHI_RESULT (phi), &use_p, &use_stmt)) + if (!single_imm_use (phires, &use_p, &use_stmt)) return false; enum tree_code cmp; tree lhs, rhs; + gimple *orig_use_stmt = use_stmt; + tree orig_use_lhs = NULL_TREE; + int prec = TYPE_PRECISION (TREE_TYPE (phires)); + if (is_gimple_assign (use_stmt) + && gimple_assign_rhs_code (use_stmt) == BIT_AND_EXPR + && TREE_CODE (gimple_assign_rhs2 (use_stmt)) == INTEGER_CST + && (wi::to_wide (gimple_assign_rhs2 (use_stmt)) + == wi::shifted_mask (1, prec - 1, false, prec))) + { + /* For partial_ordering result operator>= with unspec as second + argument is (res & 1) == res, folded by match.pd into + (res & ~1) == 0. */ + orig_use_lhs = gimple_assign_lhs (use_stmt); + if (SSA_NAME_OCCURS_IN_ABNORMAL_PHI (orig_use_lhs)) + return false; + if (EDGE_COUNT (phi_bb->preds) != 4) + return false; + if (!single_imm_use (orig_use_lhs, &use_p, &use_stmt)) + return false; + } if (gimple_code (use_stmt) == GIMPLE_COND) { cmp = gimple_cond_code (use_stmt); @@ -1948,10 +1969,19 @@ spaceship_replacement (basic_block cond_bb, basic_block middle_bb, default: return false; } - if (lhs != PHI_RESULT (phi) + if (lhs != (orig_use_lhs ? orig_use_lhs : phires) || !tree_fits_shwi_p (rhs) || !IN_RANGE (tree_to_shwi (rhs), -1, 1)) return false; + if (orig_use_lhs) + { + if ((cmp != EQ_EXPR && cmp != NE_EXPR) || !integer_zerop (rhs)) + return false; + /* As for -ffast-math we assume the 2 return to be + impossible, canonicalize (res & ~1) == 0 into + res >= 0 and (res & ~1) != 0 as res < 0. */ + cmp = cmp == EQ_EXPR ? GE_EXPR : LT_EXPR; + } if (!empty_block_p (middle_bb)) return false; @@ -2092,7 +2122,7 @@ spaceship_replacement (basic_block cond_bb, basic_block middle_bb, ? EDGE_TRUE_VALUE : EDGE_FALSE_VALUE)) == 0) return false; - /* lhs1 one_cmp rhs1 results in PHI_RESULT (phi) of 1. */ + /* lhs1 one_cmp rhs1 results in phires of 1. */ enum tree_code one_cmp; if ((cmp1 == LT_EXPR) ^ (!integer_onep ((e1->flags & EDGE_TRUE_VALUE) ? arg1 : arg0))) @@ -2185,13 +2215,29 @@ spaceship_replacement (basic_block cond_bb, basic_block middle_bb, use_operand_p use_p; imm_use_iterator iter; bool has_debug_uses = false; - FOR_EACH_IMM_USE_FAST (use_p, iter, PHI_RESULT (phi)) + FOR_EACH_IMM_USE_FAST (use_p, iter, phires) { gimple *use_stmt = USE_STMT (use_p); + if (orig_use_lhs && use_stmt == orig_use_stmt) + continue; gcc_assert (is_gimple_debug (use_stmt)); has_debug_uses = true; break; } + if (orig_use_lhs) + { + if (!has_debug_uses) + FOR_EACH_IMM_USE_FAST (use_p, iter, orig_use_lhs) + { + gimple *use_stmt = USE_STMT (use_p); + gcc_assert (is_gimple_debug (use_stmt)); + has_debug_uses = true; + } + gimple_stmt_iterator gsi = gsi_for_stmt (orig_use_stmt); + tree zero = build_zero_cst (TREE_TYPE (orig_use_lhs)); + gimple_assign_set_rhs_with_ops (&gsi, INTEGER_CST, zero); + update_stmt (orig_use_stmt); + } if (has_debug_uses) { @@ -2203,7 +2249,7 @@ spaceship_replacement (basic_block cond_bb, basic_block middle_bb, Ignore the value of 2, because if NaNs aren't expected, all floating point numbers should be comparable. */ gimple_stmt_iterator gsi = gsi_after_labels (gimple_bb (phi)); - tree type = TREE_TYPE (PHI_RESULT (phi)); + tree type = TREE_TYPE (phires); tree temp1 = make_node (DEBUG_EXPR_DECL); DECL_ARTIFICIAL (temp1) = 1; TREE_TYPE (temp1) = type; @@ -2221,10 +2267,18 @@ spaceship_replacement (basic_block cond_bb, basic_block middle_bb, t = build3 (COND_EXPR, type, t, build_zero_cst (type), temp1); g = gimple_build_debug_bind (temp2, t, phi); gsi_insert_before (&gsi, g, GSI_SAME_STMT); - replace_uses_by (PHI_RESULT (phi), temp2); + replace_uses_by (phires, temp2); + if (orig_use_lhs) + replace_uses_by (orig_use_lhs, temp2); } } + if (orig_use_lhs) + { + gimple_stmt_iterator gsi = gsi_for_stmt (orig_use_stmt); + gsi_remove (&gsi, true); + } + gimple_stmt_iterator psi = gsi_for_stmt (phi); remove_phi_node (&psi, true); </cut>

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: c++: value-init vs zero-init in expand_aggr_init_1 [PR65816]

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: c++: value-init vs zero-init in expand_aggr_init_1 [PR65816]: commit ac0bc21bd634a334ba8f323c39a11f01dfdc2aae Author: Patrick Palka <ppalka(a)redhat.com> c++: value-init vs zero-init in expand_aggr_init_1 [PR65816] Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 33 # First few build errors in logs: # 00:01:23 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:01:23 make[2]: *** [scripts/gcc-plugins/latent_entropy_plugin.so] Error 1 # 00:01:23 cc1plus: fatal error: ./include/generated/utsrelease.h: No such file or directory # 00:01:23 make[2]: *** [scripts/gcc-plugins/randomize_layout_plugin.so] Error 1 # 00:01:23 make[1]: *** [scripts/gcc-plugins] Error 2 # 00:01:24 make: *** [scripts] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 22769 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-arm-next-allmodconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… Reproduce builds: <cut> mkdir investigate-gcc-ac0bc21bd634a334ba8f323c39a11f01dfdc2aae cd investigate-gcc-ac0bc21bd634a334ba8f323c39a11f01dfdc2aae # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-next-allmo… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach ac0bc21bd634a334ba8f323c39a11f01dfdc2aae ../artifacts/test.sh # Reproduce last_good build git checkout --detach 9f55df63154a39d67ef5b24def7044bf87300831 ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit ac0bc21bd634a334ba8f323c39a11f01dfdc2aae Author: Patrick Palka <ppalka(a)redhat.com> Date: Tue Jun 1 12:23:49 2021 -0400 c++: value-init vs zero-init in expand_aggr_init_1 [PR65816] In the case of value-initializing an object of class type T, [dcl.init.general]/8 says: - if T has either no default constructor ([class.default.ctor]) or a default constructor that is user-provided or deleted, then the object is default-initialized; - otherwise, the object is zero-initialized and ... if T has a non-trivial default constructor, the object is default-initialized; But when determining whether to first zero-initialize the object, expand_aggr_init_1 incorrectly considers the user-providedness of _all_ constructors rather than only that of the _default_ constructors. This causes us to skip the zero-initialization step when the class type has a defaulted default constructor alongside a user-defined constructor. It seems the predicate type_has_non_user_provided_default_constructor accurately captures the above rule for when to first perform a zero-initialization during value-initialization, so this patch adjusts expand_aggr_init_1 to use this predicate instead. PR c++/65816 gcc/cp/ChangeLog: * init.c (expand_aggr_init_1): Check type_has_non_user_provided_default_constructor instead of type_has_user_provided_constructor. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/constexpr-delegating3.C: New test. * g++.dg/cpp0x/dc10.C: New test. * g++.dg/cpp0x/initlist-base4.C: New test. * g++.dg/cpp2a/constexpr-init22.C: New test. libstdc++-v3/ChangeLog: * testsuite/23_containers/deque/allocator/default_init.cc, testsuite/23_containers/forward_list/allocator/default_init.cc, testsuite/23_containers/list/allocator/default_init.cc, testsuite/23_containers/map/allocator/default_init.cc, testsuite/23_containers/set/allocator/default_init.cc, testsuite/23_containers/vector/allocator/default_init.cc, testsuite/23_containers/vector/bool/allocator/default_init.cc: Remove xfail. --- gcc/cp/init.c | 4 ++-- gcc/testsuite/g++.dg/cpp0x/constexpr-delegating3.C | 10 +++++++++ gcc/testsuite/g++.dg/cpp0x/dc10.C | 19 ++++++++++++++++ gcc/testsuite/g++.dg/cpp0x/initlist-base4.C | 26 ++++++++++++++++++++++ gcc/testsuite/g++.dg/cpp2a/constexpr-init22.C | 14 ++++++++++++ .../23_containers/deque/allocator/default_init.cc | 1 - .../forward_list/allocator/default_init.cc | 1 - .../23_containers/list/allocator/default_init.cc | 1 - .../23_containers/map/allocator/default_init.cc | 1 - .../23_containers/set/allocator/default_init.cc | 1 - .../23_containers/vector/allocator/default_init.cc | 1 - .../vector/bool/allocator/default_init.cc | 1 - 12 files changed, 71 insertions(+), 9 deletions(-) diff --git a/gcc/cp/init.c b/gcc/cp/init.c index 04d495807ef..b1123287300 100644 --- a/gcc/cp/init.c +++ b/gcc/cp/init.c @@ -2078,9 +2078,9 @@ expand_aggr_init_1 (tree binfo, tree true_exp, tree exp, tree init, int flags, that's value-initialization. */ if (init == void_type_node) { - /* If the type has data but no user-provided ctor, we need to zero + /* If the type has data but no user-provided default ctor, we need to zero out the object. */ - if (!type_has_user_provided_constructor (type) + if (type_has_non_user_provided_default_constructor (type) && !is_really_empty_class (type, /*ignore_vptr*/true)) { tree field_size = NULL_TREE; diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-delegating3.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-delegating3.C new file mode 100644 index 00000000000..2263ec89488 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-delegating3.C @@ -0,0 +1,10 @@ +// PR c++/65816 +// { dg-do compile { target c++11 } } + +struct test { + int m; + test() = default; + constexpr test(int) : test() {} +}; + +static_assert(test(0).m == 0, ""); diff --git a/gcc/testsuite/g++.dg/cpp0x/dc10.C b/gcc/testsuite/g++.dg/cpp0x/dc10.C new file mode 100644 index 00000000000..c008a1703e8 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/dc10.C @@ -0,0 +1,19 @@ +// PR c++/65816 +// { dg-do run { target c++11 } } + +void* operator new(decltype(sizeof(int)), void* ptr) { return ptr; } + +struct test { + int i; + test() = default; + test(int) : test() {} +}; + +int main() { + alignas(test) unsigned char space[sizeof(test)]; + for (auto& c : space) c = 0xff; + + auto ptr = ::new(&space) test(42); + int& i = static_cast<test&>(*ptr).i; + if (i != 0) __builtin_abort(); +} diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist-base4.C b/gcc/testsuite/g++.dg/cpp0x/initlist-base4.C new file mode 100644 index 00000000000..4a02af92799 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/initlist-base4.C @@ -0,0 +1,26 @@ +// PR c++/65816 +// { dg-do run { target c++11 } } + +void* operator new(decltype(sizeof(int)), void* ptr) { return ptr; } + +struct item { int i; }; + +struct collector : item { + int j; + collector() = default; + collector(int) {} +}; + +struct tuple : collector { + tuple() : collector() {} +}; + +int main() { + alignas(tuple) unsigned char space[sizeof(tuple)]; + for (auto& c : space) c = 0xff; + + auto ptr = ::new(&space) tuple; + int& i = static_cast<tuple&>(*ptr).i; + int& j = static_cast<tuple&>(*ptr).j; + if (i != 0 || j != 0) __builtin_abort(); +} diff --git a/gcc/testsuite/g++.dg/cpp2a/constexpr-init22.C b/gcc/testsuite/g++.dg/cpp2a/constexpr-init22.C new file mode 100644 index 00000000000..50e4a95dbda --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/constexpr-init22.C @@ -0,0 +1,14 @@ +// PR c++/65816 +// { dg-do compile { target c++20 } } + +struct X { + int i; + X() = default; + constexpr X(int) { } +}; + +struct Y : X { + constexpr Y() : X() { } +}; + +static_assert(Y().i == 0); diff --git a/libstdc++-v3/testsuite/23_containers/deque/allocator/default_init.cc b/libstdc++-v3/testsuite/23_containers/deque/allocator/default_init.cc index f51cc5b49b9..9428206f2ef 100644 --- a/libstdc++-v3/testsuite/23_containers/deque/allocator/default_init.cc +++ b/libstdc++-v3/testsuite/23_containers/deque/allocator/default_init.cc @@ -17,7 +17,6 @@ // { dg-do run { target c++11 } } // { dg-options "-O0" } -// { dg-xfail-run-if "PR c++/65816" { *-*-* } } #include <deque> #include <testsuite_hooks.h> diff --git a/libstdc++-v3/testsuite/23_containers/forward_list/allocator/default_init.cc b/libstdc++-v3/testsuite/23_containers/forward_list/allocator/default_init.cc index a60192641d4..4298fa5ffa5 100644 --- a/libstdc++-v3/testsuite/23_containers/forward_list/allocator/default_init.cc +++ b/libstdc++-v3/testsuite/23_containers/forward_list/allocator/default_init.cc @@ -17,7 +17,6 @@ // { dg-do run { target c++11 } } // { dg-options "-O0" } -// { dg-xfail-run-if "PR c++/65816" { *-*-* } } #include <forward_list> #include <testsuite_hooks.h> diff --git a/libstdc++-v3/testsuite/23_containers/list/allocator/default_init.cc b/libstdc++-v3/testsuite/23_containers/list/allocator/default_init.cc index 62bfd78df18..03d8cfc89e8 100644 --- a/libstdc++-v3/testsuite/23_containers/list/allocator/default_init.cc +++ b/libstdc++-v3/testsuite/23_containers/list/allocator/default_init.cc @@ -17,7 +17,6 @@ // { dg-do run { target c++11 } } // { dg-options "-O0" } -// { dg-xfail-run-if "PR c++/65816" { *-*-* } } #include <list> #include <testsuite_hooks.h> diff --git a/libstdc++-v3/testsuite/23_containers/map/allocator/default_init.cc b/libstdc++-v3/testsuite/23_containers/map/allocator/default_init.cc index bc9027703fc..6e3f36d60a4 100644 --- a/libstdc++-v3/testsuite/23_containers/map/allocator/default_init.cc +++ b/libstdc++-v3/testsuite/23_containers/map/allocator/default_init.cc @@ -17,7 +17,6 @@ // { dg-do run { target c++11 } } // { dg-options "-O0" } -// { dg-xfail-run-if "PR c++/65816" { *-*-* } } #include <map> #include <testsuite_hooks.h> diff --git a/libstdc++-v3/testsuite/23_containers/set/allocator/default_init.cc b/libstdc++-v3/testsuite/23_containers/set/allocator/default_init.cc index 8a99b491c25..b031cb81504 100644 --- a/libstdc++-v3/testsuite/23_containers/set/allocator/default_init.cc +++ b/libstdc++-v3/testsuite/23_containers/set/allocator/default_init.cc @@ -17,7 +17,6 @@ // { dg-do run { target c++11 } } // { dg-options "-O0" } -// { dg-xfail-run-if "PR c++/65816" { *-*-* } } #include <set> #include <testsuite_hooks.h> diff --git a/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc b/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc index c16d3b046e4..4673db71b6c 100644 --- a/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc +++ b/libstdc++-v3/testsuite/23_containers/vector/allocator/default_init.cc @@ -17,7 +17,6 @@ // { dg-do run { target c++11 } } // { dg-options "-O0" } -// { dg-xfail-run-if "PR c++/65816" { *-*-* } } #include <vector> #include <testsuite_hooks.h> diff --git a/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc b/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc index 4111e3ac3eb..61cc7859d74 100644 --- a/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc +++ b/libstdc++-v3/testsuite/23_containers/vector/bool/allocator/default_init.cc @@ -17,7 +17,6 @@ // { dg-do run { target c++11 } } // { dg-options "-O0" } -// { dg-xfail-run-if "PR c++/65816" { *-*-* } } #include <vector> #include <testsuite_hooks.h> </cut>

3 years, 3 months

1
0
0 0

[TCWG CI] Regression caused by gcc: Fold sign of LSHIFT_EXPR to eliminate no-op conversions.

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: Fold sign of LSHIFT_EXPR to eliminate no-op conversions.: commit 1d244020246cb155e4de62ca3b302b920a1f513f Author: Roger Sayle <roger(a)nextmovesoftware.com> Fold sign of LSHIFT_EXPR to eliminate no-op conversions. Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 22170 # First few build errors in logs: # 00:17:02 drivers/gpu/drm/amd/amdgpu/amdgpu.h:1238:53: error: ‘<<’ in boolean context, did you mean ‘<’? [-Werror=int-in-bool-context] # 00:17:03 make[4]: *** [drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o] Error 1 # 00:23:50 drivers/net/wireless/intel/iwlwifi/mvm/tx.c:2226:1: error: type mismatch in ‘lshift_expr’ # 00:23:50 drivers/net/wireless/intel/iwlwifi/mvm/tx.c:2226:1: internal compiler error: verify_gimple failed # 00:23:50 make[6]: *** [drivers/net/wireless/intel/iwlwifi/mvm/tx.o] Error 1 # 00:24:56 make[5]: *** [drivers/net/wireless/intel/iwlwifi/mvm] Error 2 # 00:26:51 make[4]: *** [drivers/net/wireless/intel/iwlwifi] Error 2 # 00:26:51 make[3]: *** [drivers/net/wireless/intel] Error 2 # 00:29:27 make[2]: *** [drivers/net/wireless] Error 2 # 00:34:08 make[3]: *** [drivers/gpu/drm/amd/amdgpu] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 30479 # linux build successful: all THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-release-arm-stable-allmodconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-stable-all… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-stable-all… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-stable-all… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-stable-all… Reproduce builds: <cut> mkdir investigate-gcc-1d244020246cb155e4de62ca3b302b920a1f513f cd investigate-gcc-1d244020246cb155e4de62ca3b302b920a1f513f # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-stable-all… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-stable-all… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-release-arm-stable-all… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach 1d244020246cb155e4de62ca3b302b920a1f513f ../artifacts/test.sh # Reproduce last_good build git checkout --detach b320edc0c29c838b0090c3c9be14187d132f73f2 ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit 1d244020246cb155e4de62ca3b302b920a1f513f Author: Roger Sayle <roger(a)nextmovesoftware.com> Date: Mon Aug 23 12:37:04 2021 +0100 Fold sign of LSHIFT_EXPR to eliminate no-op conversions. This short patch teaches fold that it is "safe" to change the sign of a left shift, to reduce the number of type conversions in gimple. As an example: unsigned int foo(unsigned int i) { return (int)i << 8; } is currently optimized to: unsigned int foo (unsigned int i) { int i.0_1; int _2; unsigned int _4; <bb 2> [local count: 1073741824]: i.0_1 = (int) i_3(D); _2 = i.0_1 << 8; _4 = (unsigned int) _2; return _4; } with this patch, this now becomes: unsigned int foo (unsigned int i) { unsigned int _2; <bb 2> [local count: 1073741824]: _2 = i_1(D) << 8; return _2; } which generates exactly the same assembly language. Aside from the reduced memory usage, the real benefit is that no-op conversions tend to interfere with many folding optimizations. For example, unsigned int bar(unsigned char i) { return (i ^ (i<<16)) | (i<<8); } currently gets (tangled in conversions and) optimized to: unsigned int bar (unsigned char i) { unsigned int _1; unsigned int _2; int _3; int _4; unsigned int _6; unsigned int _8; <bb 2> [local count: 1073741824]: _1 = (unsigned int) i_5(D); _2 = _1 * 65537; _3 = (int) i_5(D); _4 = _3 << 8; _8 = (unsigned int) _4; _6 = _2 | _8; return _6; } but with this patch, bar now optimizes down to: unsigned int bar(unsigned char i) { unsigned int _1; unsigned int _4; <bb 2> [local count: 1073741824]: _1 = (unsigned int) i_3(D); _4 = _1 * 65793; return _4; } 2021-08-23 Roger Sayle <roger(a)nextmovesoftware.com> gcc/ChangeLog * match.pd (shift transformations): Change the sign of an LSHIFT_EXPR if it reduces the number of explicit conversions. gcc/testsuite/ChangeLog * gcc.dg/fold-convlshift-1.c: New test case. * gcc.dg/fold-convlshift-2.c: New test case. --- gcc/match.pd | 9 +++++++++ gcc/testsuite/gcc.dg/fold-convlshift-1.c | 20 ++++++++++++++++++++ gcc/testsuite/gcc.dg/fold-convlshift-2.c | 20 ++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/gcc/match.pd b/gcc/match.pd index 0fcfd0ea62c..978a1b0172e 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3385,6 +3385,15 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (if (integer_zerop (@2) || integer_all_onesp (@2)) (cmp @0 @2))))) +/* Both signed and unsigned lshift produce the same result, so use + the form that minimizes the number of conversions. */ +(simplify + (convert (lshift:s@0 (convert:s@1 @2) INTEGER_CST@3)) + (if (tree_nop_conversion_p (type, TREE_TYPE (@0)) + && INTEGRAL_TYPE_P (TREE_TYPE (@2)) + && TYPE_PRECISION (TREE_TYPE (@2)) <= TYPE_PRECISION (type)) + (lshift (convert @2) @3))) + /* Simplifications of conversions. */ /* Basic strip-useless-type-conversions / strip_nops. */ diff --git a/gcc/testsuite/gcc.dg/fold-convlshift-1.c b/gcc/testsuite/gcc.dg/fold-convlshift-1.c new file mode 100644 index 00000000000..b6f57f81e72 --- /dev/null +++ b/gcc/testsuite/gcc.dg/fold-convlshift-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +unsigned int foo(unsigned int i) +{ + int t1 = i; + int t2 = t1 << 8; + return t2; +} + +int bar(int i) +{ + unsigned int t1 = i; + unsigned int t2 = t1 << 8; + return t2; +} + +/* { dg-final { scan-tree-dump-not "\$int\$" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "\$unsigned int\$" "optimized" } } */ + diff --git a/gcc/testsuite/gcc.dg/fold-convlshift-2.c b/gcc/testsuite/gcc.dg/fold-convlshift-2.c new file mode 100644 index 00000000000..f21358c4584 --- /dev/null +++ b/gcc/testsuite/gcc.dg/fold-convlshift-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +unsigned int foo(unsigned char c) +{ + int t1 = c; + int t2 = t1 << 8; + return t2; +} + +int bar(unsigned char c) +{ + unsigned int t1 = c; + unsigned int t2 = t1 << 8; + return t2; +} + +/* { dg-final { scan-tree-dump-times "\$int\$" 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\$unsigned int\$" 1 "optimized" } } */ + </cut>

3 years, 3 months

1
0
0 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

linaro-toolchain