- linaro-toolchain - lists.linaro.org

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI - Committed ABE change suggested by Maxim to mention failures that cause additional testsuite runs. - Tried to update Python MinGW build to 3.x, but it's a rabbit hole. Proposing to disable Python support when cross-building GDB with MinGW instead. - First regression detected by the tcwg_gnu_native_check_gdb CI job reported upstream¹. Started investigating it. [GNU-767] Support changing SVE vector length in remote debugging - Created a testcase to exercise the corner case mentioned by Pedro. Found out that GDB is also susceptible to it. Fixed both GDB and gdbserver. Posted patch series upstream². -- Thiago ¹ https://inbox.sourceware.org/gdb-patches/871ql6dhf4.fsf@linaro.org/ ² https://inbox.sourceware.org/gdb-patches/20230331034432.3037148-1-thiago.ba…

2 years, 1 month

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[ACTIVITY] week ending Apr. 2 2023

by Alex Bennée

Project Orko ============ - more card generation for GPU tasks - started on virtio-gpu blog post - posted [RFC PATCH] tests/avocado: Test Xen guest support under KVM Message-Id: <20230324160719.1790792-1-alex.bennee(a)linaro.org> [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Generic vhost-user-device ([ORKO-19]) ===================================== - got an initial working [branch for generic and rng] [ORKO-19] <https://linaro.atlassian.net/browse/ORKO-19> [branch for generic and rng] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-device> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH 00/10] accel/tcg: refactor the cpu-exec loop Message-Id: <20230320101035.2214196-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] more misc fixes for 8.0 (tests, gdbstub, meta, docs) Message-Id: <20230330101141.30199-1-alex.bennee(a)linaro.org> - preparing for next week's GSoC assessments [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [1/1] ======================= [PATCH v2 0/3] Enable avocado testing for Xen guests Message-Id: <20230308111952.2728440-1-dwmw2(a)infradead.org> Other ===== Absences ======== - Travelling Weds afternoon Current Review Queue ==================== TODO [PATCH 00/13] {tcg,aarch64}: Add TLB_CHECK_ALIGNED Message-Id: <20230223204342.1093632-1-richard.henderson(a)linaro.org> ========================================================================================================================== TODO [RFC QEMU PATCH 00/18] Add VirtIO GPU and Passthrough GPU support on Xen Message-Id: <20230312092244.451465-1-ray.huang(a)amd.com> ==================================================================================================================================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 1 month

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[ACTIVITY] report week ending 31 Mar

by Peter Maydell

Progress (short week, holiday and recovering from covid...): * UM-2 [QEMU upstream maintainership] * 8.0 release related work rumbles on * debugged and fixed a regression caused by my work on HSTR_EL2 traps * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] * implemented FEAT_PAN3 (and fixed a minor bug in syndrome reporting that I noticed in the process) -- PMM

2 years, 1 month

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[ACTIVITY] Report for week #12

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Enabled gdb.gdb/unittest.exp in fast_check_gdb job. It should be stable now that tcwg-jade-02's kernel has been upgraded. - Enabled bisections for check_gdb jobs. - Implemented Maxim's idea to handle GDB testsuite's tests that can FAIL but are silent when they pass (i.e., the "gdb_test -nopass" statements). [GNU-767] Support changing SVE vector length in remote debugging - Back in February I upstreamed a couple of preparation patches and Pedro noticed an unintended change in behaviour that can affect a corner case, so I am working on a fix for that now. -- Thiago

2 years, 1 month

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[ACTIVITY] Report for week #11

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Finished implementing ABE's support for rerunning failed tests using Maxim's idea of leveraging validate_failures.py to determine which tests need to be rerun. Submitted v3 and v4 versions, and committed v4. - Investigated why tcwg-abet-tested jobs have been failing in the CI. Found out that Jenkins sets a bogus core.hooksPath in the git repo config. Submitted and merged a gerrit request fixing the problem. - Investigated why cross-build gdbserver needs GMP and MPFR (and is thus failing to build) in tcwg-gnu-build jobs. Submitted Gerrit review request to fix it. - Started looking into why re-enabling GDB testsuite parallelism makes it run fewer tests. -- Thiago

2 years, 1 month

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[ACTIVITY] report week ending 17 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - went through and made estimates for a pile of JIRA tasks relating to implementing features we're missing to get to ARMv9.4 - diagnosed why --enable-werror wasn't affecting warnings from the kerneldoc docs generator, and sent a patch fixing it - some bug triage, looking for issues that ought to be fixed for 8.0 - fixed a division-by-zero bug in the cadence UART model - fixed a documentation markup mistake that made the docs look odd - investigating/fixing some more CI failures - minor bits of travel/conference related admin -- PMM

2 years, 1 month

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[ACTIVITY] Report for week #10

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Submitted and merged a couple of review requests removing obsolete CI jobs related to release automation and release regression detection - Finished version of scripts that have most of the logic for rerunning testsuites in ABE. Submitted as a review request. Addressed review comments and submitted v2. - Maxim found out a way to simplify the logic of determining whether a new testsuite run is warranted by using validate_failures.py, which I'm now implementing. -- Thiago

2 years, 2 months

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[ACTIVITY] week ending Mar. 12 2023

by Alex Bennée

Project Orko ============ - various syncs and lining up for resources [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Enable Arm Architecture in QEMU =============================== - bunch of sync meetings with various partners and members QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/30] gdbstub refactor for smaller build Message-Id: <20230307212139.883112-1-alex.bennee(a)linaro.org> - posted [PATCH 00/11] tweaks and fixes for 8.0-rc1 (tests, plugins, docs) Message-Id: <20230310103123.2118519-1-alex.bennee(a)linaro.org> - posted [PULL 0/5] gitdm updates Message-Id: <20230310155726.2222233-1-alex.bennee(a)linaro.org> - posted [PATCH v2 00/10] gitdm metadata updates Message-Id: <20230310180332.2274827-1-alex.bennee(a)linaro.org> - posted [kvm-unit-tests PATCH v10 0/7] MTTCG sanity tests for ARM Message-Id: <20230307112845.452053-1-alex.bennee(a)linaro.org> - various GSoC and Outreachy wranglings Completed Reviews [6/6] ======================= [PATCH v2] TCG plugin API extension to read guest memory content by an address Message-Id: <5c50db42136d4a908b261c66b132b043(a)yadro.com> [PATCH] plugin: fix clearing of plugin_mem_cbs before TB exit Message-Id: <20230222043204.941336-1-cota(a)braap.org> [PATCH 0/8] Inter-plugin interactions with QPP Message-Id: <20221213213757.4123265-1-fasano(a)mit.edu> [PATCH v4.5 00/29] gdbstub/next: re-organise and split build Message-Id: <20230303025805.625589-1-richard.henderson(a)linaro.org> [PATCH 0/3] softfloat: FloatRelation cleanups Message-Id: <20220401132240.79730-1-richard.henderson(a)linaro.org> [PATCH v2 0/3] Enable avocado testing for Xen guests Message-Id: <20230308111952.2728440-1-dwmw2(a)infradead.org> Absences ======== - Away on Tuesday Current Review Queue ==================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== TODO [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Message-Id: <20230226220650.1480786-1-smostafa(a)google.com> ====================================================================================================================== TODO [RFC PATCH] hw: arm: Support direct boot for Linux/arm64 EFI zboot images Message-Id: <20230223105308.559632-1-ardb(a)kernel.org> =================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 2 months

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[ACTIVITY] report week ending Mar 10

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Softfreeze was this Tuesday; lots of wrangling of pull requests - Code review; last arm pullreq before softfreeze - various admin type bits and pieces -- PMM

2 years, 2 months

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[ACTIVITY] Report for week #9

by Thiago Jung Bauermann

Hello, [GNU-796] Stabilize GDB testsuite results in the CI: - Moved most of logic to rerun failed tests from tcwg_gnu-build.sh to Abe and a new script based on the sum file parser of compare_dg_tests.pl. The new script creates a "merged" sum file from all the runs. Currently changing Abe to make use of it. - Did a few cleanups in compare_dg_tests.pl as I was going through its code. Also added KFAIL status support to it, which the GDB testsuite needs. - Removed a few obsolete CI jobs which came out of the woodwork when I merged the compare_dg_tests.pl cleanups. -- Thiago

2 years, 2 months

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[ACTIVITY] week ending Mar. 5 2023

by Alex Bennée

Project Orko ============ - did [launch presentation] for SOAFEE and LEDGE SC [launch presentation] <https://docs.google.com/presentation/d/1CGYIK2W0VSo0kih9ExwfFlkGww7rL5fjMIb…> Enable Arm Architecture in QEMU =============================== - bunch of planning for FEAT_GCS, see [QEMU-517] and related - spoke to Lauterbach on behalf of QC, gave pointers on debug [QEMU-517] <https://linaro.atlassian.net/browse/QEMU-517> FEAT_RME, CCA Realms ([QEMU-466]) ================================= - did a bit of review of rth's precursor patches [QEMU-466] <https://linaro.atlassian.net/browse/QEMU-466> QEMU Upstream Work ([UM-2]) =========================== - finished up [MR for using locally built QEMU in TuxRun] - posted [PATCH v4 00/26] gdbstub/next: re-organise and split build Message-Id: <20230302190846.2593720-1-alex.bennee(a)linaro.org> - posted [PULL v2 00/24] testing updates (gitlab, cirrus, docker, avocado, windows) Message-Id: <20230301151604.1948813-1-alex.bennee(a)linaro.org> - these help address the CI minutes we are burning through monthly now [UM-2] <https://linaro.atlassian.net/browse/UM-2> [testing/next] <https://github.com/stsquad/qemu/tree/testing/next> [MR for using locally built QEMU in TuxRun] <https://gitlab.com/Linaro/tuxrun/-/merge_requests/179> Completed Reviews [6/6] ======================= [PATCH v2 0/4] Fix deadlock when dying because of a signal Message-Id: <20230213125238.331881-1-iii(a)linux.ibm.com> [PATCH 0/8] hw/arm: Cleanups around QOM style Message-Id: <20230220115114.25237-1-philmd(a)linaro.org> [PATCH v2 00/24] hw/ide: QOM/QDev housekeeping Message-Id: <20230220091358.17038-1-philmd(a)linaro.org> [PATCH v2] gdbstub: move update guest debug to accel ops Message-Id: <20230207131721.49233-1-mads(a)ynddal.dk> [PATCH 0/5] iotests: make meson aware of individual I/O tests Message-Id: <20230302184606.418541-1-berrange(a)redhat.com> [PATCH v2] TCG plugin API extension to read guest memory content by an address Message-Id: <5c50db42136d4a908b261c66b132b043(a)yadro.com> Other ===== Absences ======== Current Review Queue ==================== TODO [PATCH 1/6] Add the Android Emulator hypervisor driver (AEHD) accelerator. Message-Id: <20230303022618.4098825-1-hshan(a)google.com> ====================================================================================================================================== TODO [RFC PATCH v2 00/11] Add stage-2 translation for SMMUv3 Message-Id: <20230226220650.1480786-1-smostafa(a)google.com> ====================================================================================================================== TODO [PATCH v2 00/28] tcg: Simplify temporary usage Message-Id: <20230222232715.15034-1-richard.henderson(a)linaro.org> ==================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 2 months

1
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[TCWG CI] Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC

by ci_notify＠linaro.org

Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC: Results changed to -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 from -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-17-init-3240-g02828abd0845 commit for tcwg_aosp-code_size-surfaceflinger: commit 02828abd084536bb758d65043e9747dc2f0e990c Author: Sanjay Patel <spatel(a)rotateright.com> Date: Fri Feb 24 12:05:14 2023 -0500 [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC * oriole-master ** Failure after llvmorg-17-init-3240-g02828abd0845: [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC: ** https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Bad build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Good build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Reproduce current build: <cut> mkdir -p investigate-llvm-02828abd084536bb758d65043e9747dc2f0e990c cd investigate-llvm-02828abd084536bb758d65043e9747dc2f0e990c # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 02828abd084536bb758d65043e9747dc2f0e990c Author: Sanjay Patel <spatel(a)rotateright.com> Date: Fri Feb 24 12:05:14 2023 -0500 [InstCombine] add tests for redundant-via-demanded-elts vec binops; NFC --- .../Transforms/InstCombine/vec_demanded_elts.ll | 317 ++++++++++++++++++++- 1 file changed, 313 insertions(+), 4 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll index e18865f9b95f..0f33eb58f080 100644 --- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -2,6 +2,9 @@ ; RUN: opt < %s -passes=instcombine -S | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +declare void @use(<2 x i4>) +declare void @use_fp(<2 x float>) + define i32 @test2(float %f) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: [[T5:%.*]] = fmul float [[F:%.*]], [[F]] @@ -76,8 +79,8 @@ define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind { define <2 x float> @test_fptrunc(double %f) { ; CHECK-LABEL: @test_fptrunc( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[F:%.*]], i64 0 -; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float> -; CHECK-NEXT: ret <2 x float> [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float> +; CHECK-NEXT: ret <2 x float> [[RET]] ; %t9 = insertelement <4 x double> undef, double %f, i32 0 %t10 = insertelement <4 x double> %t9, double 0.000000e+00, i32 1 @@ -91,8 +94,8 @@ define <2 x float> @test_fptrunc(double %f) { define <2 x double> @test_fpext(float %f) { ; CHECK-LABEL: @test_fpext( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[F:%.*]], i64 0 -; CHECK-NEXT: [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double> -; CHECK-NEXT: ret <2 x double> [[TMP2]] +; CHECK-NEXT: [[RET:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double> +; CHECK-NEXT: ret <2 x double> [[RET]] ; %t9 = insertelement <4 x float> undef, float %f, i32 0 %t10 = insertelement <4 x float> %t9, float 0.000000e+00, i32 1 @@ -842,3 +845,309 @@ define <8 x i4> @ins_of_ext_undef_elts_propagation2(<8 x i4> %v, <8 x i4> %v2, i %i21 = shufflevector <8 x i4> %i20, <8 x i4> %v, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15> ret <8 x i4> %i21 } + +define void @common_binop_demand_via_splat_op0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define void @common_binop_demand_via_splat_op1(<2 x i4> %p, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op1( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_X_YSHUF:%.*]] = mul <2 x i4> [[X]], [[YSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_X_YSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_x_yshuf = mul <2 x i4> %x, %yshuf + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_x_yshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 1, i4 2>, [[Q:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = mul <2 x i4> [[Y]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 1, i4 2>, %q ; thwart complexity-based canonicalization + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = mul <2 x i4> %y, %xshuf + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op1_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_splat_op1_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 2, i4 3>, [[Q:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = mul <2 x i4> [[YSHUF]], [[X]] +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 2, i4 3>, %q ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = mul <2 x i4> %yshuf, %x + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_wrong_commute(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_wrong_commute( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = sub <2 x i4> [[Y:%.*]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = sub <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret void +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = sub <2 x i4> %y, %xshuf + %b_xy = sub <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xy_splat) + call void @use(<2 x i4> %b_y_xshuf) + ret void +} + +define void @common_binop_demand_via_splat_op0_not_dominated1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_not_dominated1( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %b_xy = mul <2 x i4> %x, %y + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define void @common_binop_demand_via_splat_op0_not_dominated2(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_splat_op0_not_dominated2( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY_SPLAT:%.*]] = shufflevector <2 x i4> [[B_XY]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: call void @use(<2 x i4> [[B_XY_SPLAT]]) +; CHECK-NEXT: ret void +; + %b_xy = mul <2 x i4> %x, %y + %b_xy_splat = shufflevector <2 x i4> %b_xy, <2 x i4> poison, <2 x i32> zeroinitializer + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + call void @use(<2 x i4> %b_xshuf_y) + call void @use(<2 x i4> %b_xy_splat) + ret void +} + +define i4 @common_binop_demand_via_extelt_op0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define float @common_binop_demand_via_extelt_op1(<2 x float> %p, <2 x float> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op1( +; CHECK-NEXT: [[X:%.*]] = fsub <2 x float> <float 0.000000e+00, float 1.000000e+00>, [[P:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_X_YSHUF:%.*]] = fdiv <2 x float> [[X]], [[YSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = fdiv <2 x float> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x float> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use_fp(<2 x float> [[B_X_YSHUF]]) +; CHECK-NEXT: ret float [[B_XY0]] +; + %x = fsub <2 x float> <float 0.0, float 1.0>, %p ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x float> %y, <2 x float> poison, <2 x i32> zeroinitializer + %b_x_yshuf = fdiv <2 x float> %x, %yshuf + %b_xy = fdiv <2 x float> %x, %y + %b_xy0 = extractelement <2 x float> %b_xy, i32 0 + call void @use_fp(<2 x float> %b_x_yshuf) + ret float %b_xy0 +} + +define float @common_binop_demand_via_extelt_op0_commute(<2 x float> %p, <2 x float> %q) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_commute( +; CHECK-NEXT: [[X:%.*]] = fsub <2 x float> <float 0.000000e+00, float 1.000000e+00>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = fsub <2 x float> <float 3.000000e+00, float 2.000000e+00>, [[Q:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = fmul nnan <2 x float> [[Y]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = fmul ninf <2 x float> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x float> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use_fp(<2 x float> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret float [[B_XY0]] +; + %x = fsub <2 x float> <float 0.0, float 1.0>, %p ; thwart complexity-based canonicalization + %y = fsub <2 x float> <float 3.0, float 2.0>, %q ; thwart complexity-based canonicalization + %xshuf = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> zeroinitializer + %b_y_xshuf = fmul nnan <2 x float> %y, %xshuf + %b_xy = fmul ninf <2 x float> %x, %y + %b_xy0 = extractelement <2 x float> %b_xy, i32 0 + call void @use_fp(<2 x float> %b_y_xshuf) + ret float %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op1_commute(<2 x i4> %p, <2 x i4> %q) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op1_commute( +; CHECK-NEXT: [[X:%.*]] = sub <2 x i4> <i4 0, i4 1>, [[P:%.*]] +; CHECK-NEXT: [[Y:%.*]] = sub <2 x i4> <i4 2, i4 3>, [[Q:%.*]] +; CHECK-NEXT: [[YSHUF:%.*]] = shufflevector <2 x i4> [[Y]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = or <2 x i4> [[YSHUF]], [[X]] +; CHECK-NEXT: [[B_XY:%.*]] = or <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %x = sub <2 x i4> <i4 0, i4 1>, %p ; thwart complexity-based canonicalization + %y = sub <2 x i4> <i4 2, i4 3>, %q ; thwart complexity-based canonicalization + %yshuf = shufflevector <2 x i4> %y, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = or <2 x i4> %yshuf, %x + %b_xy = or <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_y_xshuf) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_wrong_commute(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_wrong_commute( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_Y_XSHUF:%.*]] = sub <2 x i4> [[Y:%.*]], [[XSHUF]] +; CHECK-NEXT: [[B_XY:%.*]] = sub <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_Y_XSHUF]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_y_xshuf = sub <2 x i4> %y, %xshuf + %b_xy = sub <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_y_xshuf) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_not_dominated1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_not_dominated1( +; CHECK-NEXT: [[B_XY:%.*]] = xor <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = xor <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %b_xy = xor <2 x i4> %x, %y + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = xor <2 x i4> %xshuf, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_not_dominated2(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_not_dominated2( +; CHECK-NEXT: [[B_XY:%.*]] = mul <2 x i4> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = mul <2 x i4> [[XSHUF]], [[Y]] +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %b_xy = mul <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = mul <2 x i4> %xshuf, %y + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_mismatch_elt0(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_mismatch_elt0( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> <i32 1, i32 1> +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 0 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> <i32 1, i32 1> + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 0 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} + +define i4 @common_binop_demand_via_extelt_op0_mismatch_elt1(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @common_binop_demand_via_extelt_op0_mismatch_elt1( +; CHECK-NEXT: [[XSHUF:%.*]] = shufflevector <2 x i4> [[X:%.*]], <2 x i4> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[B_XSHUF_Y:%.*]] = sub <2 x i4> [[XSHUF]], [[Y:%.*]] +; CHECK-NEXT: [[B_XY:%.*]] = sub nsw <2 x i4> [[X]], [[Y]] +; CHECK-NEXT: [[B_XY0:%.*]] = extractelement <2 x i4> [[B_XY]], i64 1 +; CHECK-NEXT: call void @use(<2 x i4> [[B_XSHUF_Y]]) +; CHECK-NEXT: ret i4 [[B_XY0]] +; + %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer + %b_xshuf_y = sub <2 x i4> %xshuf, %y + %b_xy = sub nsw <2 x i4> %x, %y + %b_xy0 = extractelement <2 x i4> %b_xy, i32 1 + call void @use(<2 x i4> %b_xshuf_y) + ret i4 %b_xy0 +} </cut>

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[TCWG CI] Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage

by ci_notify＠linaro.org

Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage: Results changed to -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 from -10 # build_aosp_toolchain: -2 # build_shadow_llvm: -1 # build_aosp: 0 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-692 . Status of llvmorg-17-init-3239-g025952b00e0d commit for tcwg_aosp-code_size-surfaceflinger: commit 025952b00e0d5392d31387a4ed4e1d342003a37a Author: Simon Pilgrim <llvm-dev(a)redking.me.uk> Date: Sun Feb 26 15:19:46 2023 +0000 [X86] Add PR46472 bitselect test coverage As noted on Issue #45817 we didn't have scalar coverage for this * oriole-master ** Failure after llvmorg-17-init-3239-g025952b00e0d: [X86] Add PR46472 bitselect test coverage: ** https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Bad build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Good build: https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… Reproduce current build: <cut> mkdir -p investigate-llvm-025952b00e0d5392d31387a4ed4e1d342003a37a cd investigate-llvm-025952b00e0d5392d31387a4ed4e1d342003a37a # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_aosp-code_size-surfaceflinger--oriole-master… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_aosp-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 025952b00e0d5392d31387a4ed4e1d342003a37a Author: Simon Pilgrim <llvm-dev(a)redking.me.uk> Date: Sun Feb 26 15:19:46 2023 +0000 [X86] Add PR46472 bitselect test coverage As noted on Issue #45817 we didn't have scalar coverage for this --- llvm/test/CodeGen/X86/bitselect.ll | 202 +++++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/llvm/test/CodeGen/X86/bitselect.ll b/llvm/test/CodeGen/X86/bitselect.ll new file mode 100644 index 000000000000..5f1f6bd83a9a --- /dev/null +++ b/llvm/test/CodeGen/X86/bitselect.ll @@ -0,0 +1,202 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-bmi | FileCheck %s --check-prefixes=X64,X64-NOBMI +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefixes=X64,X64-BMI + +; PR46472 +; bitselect(a,b,m) == or(and(a,not(m)),and(b,m)) +; bitselect(a,b,m) == xor(and(xor(a,b),m),a) + +define i8 @bitselect_i8(i8 %a, i8 %b, i8 %m) nounwind { +; X86-LABEL: bitselect_i8: +; X86: # %bb.0: +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorb %cl, %al +; X86-NEXT: andb {{[0-9]+}}(%esp), %al +; X86-NEXT: xorb %cl, %al +; X86-NEXT: retl +; +; X64-LABEL: bitselect_i8: +; X64: # %bb.0: +; X64-NEXT: andl %edx, %esi +; X64-NEXT: movl %edx, %eax +; X64-NEXT: notb %al +; X64-NEXT: andb %dil, %al +; X64-NEXT: orb %sil, %al +; X64-NEXT: retq + %not = xor i8 %m, -1 + %ma = and i8 %a, %not + %mb = and i8 %b, %m + %or = or i8 %ma, %mb + ret i8 %or +} + +define i16 @bitselect_i16(i16 %a, i16 %b, i16 %m) nounwind { +; X86-LABEL: bitselect_i16: +; X86: # %bb.0: +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorw %ax, %cx +; X86-NEXT: andw {{[0-9]+}}(%esp), %cx +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i16: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %eax +; X64-NOBMI-NEXT: andl %edx, %esi +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: orl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i16: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnl %edi, %edx, %eax +; X64-BMI-NEXT: andl %edx, %esi +; X64-BMI-NEXT: orl %esi, %eax +; X64-BMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-BMI-NEXT: retq + %not = xor i16 %m, -1 + %ma = and i16 %a, %not + %mb = and i16 %b, %m + %or = or i16 %ma, %mb + ret i16 %or +} + +define i32 @bitselect_i32(i32 %a, i32 %b, i32 %m) nounwind { +; X86-LABEL: bitselect_i32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i32: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: xorl %edi, %eax +; X64-NOBMI-NEXT: andl %edx, %eax +; X64-NOBMI-NEXT: xorl %edi, %eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i32: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnl %edi, %edx, %eax +; X64-BMI-NEXT: andl %edx, %esi +; X64-BMI-NEXT: orl %esi, %eax +; X64-BMI-NEXT: retq + %not = xor i32 %m, -1 + %ma = and i32 %a, %not + %mb = and i32 %b, %m + %or = or i32 %ma, %mb + ret i32 %or +} + +define i64 @bitselect_i64(i64 %a, i64 %b, i64 %m) nounwind { +; X86-LABEL: bitselect_i64: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: xorl %esi, %edx +; X86-NEXT: andl {{[0-9]+}}(%esp), %edx +; X86-NEXT: xorl %esi, %edx +; X86-NEXT: popl %esi +; X86-NEXT: retl +; +; X64-NOBMI-LABEL: bitselect_i64: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rsi, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: andq %rdx, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i64: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnq %rdi, %rdx, %rax +; X64-BMI-NEXT: andq %rdx, %rsi +; X64-BMI-NEXT: orq %rsi, %rax +; X64-BMI-NEXT: retq + %not = xor i64 %m, -1 + %ma = and i64 %a, %not + %mb = and i64 %b, %m + %or = or i64 %ma, %mb + ret i64 %or +} + +define i128 @bitselect_i128(i128 %a, i128 %b, i128 %m) nounwind { +; X86-LABEL: bitselect_i128: +; X86: # %bb.0: +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorl %edi, %ecx +; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: xorl %edi, %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: xorl %ebx, %edi +; X86-NEXT: andl {{[0-9]+}}(%esp), %edi +; X86-NEXT: xorl %ebx, %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: xorl %esi, %ebx +; X86-NEXT: andl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: xorl %esi, %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: andl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: movl %esi, 12(%eax) +; X86-NEXT: movl %ebx, 8(%eax) +; X86-NEXT: movl %edi, 4(%eax) +; X86-NEXT: movl %ecx, (%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: retl $4 +; +; X64-NOBMI-LABEL: bitselect_i128: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rdx, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: andq %r8, %rax +; X64-NOBMI-NEXT: xorq %rdi, %rax +; X64-NOBMI-NEXT: xorq %rsi, %rcx +; X64-NOBMI-NEXT: andq %r9, %rcx +; X64-NOBMI-NEXT: xorq %rsi, %rcx +; X64-NOBMI-NEXT: movq %rcx, %rdx +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: bitselect_i128: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: andnq %rsi, %r9, %rsi +; X64-BMI-NEXT: andnq %rdi, %r8, %rax +; X64-BMI-NEXT: andq %r9, %rcx +; X64-BMI-NEXT: orq %rcx, %rsi +; X64-BMI-NEXT: andq %r8, %rdx +; X64-BMI-NEXT: orq %rdx, %rax +; X64-BMI-NEXT: movq %rsi, %rdx +; X64-BMI-NEXT: retq + %not = xor i128 %m, -1 + %ma = and i128 %a, %not + %mb = and i128 %b, %m + %or = or i128 %ma, %mb + ret i128 %or +} </cut>

2 years, 2 months

1
0
0 0

[ACTIVITY] Report for week #8

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilize GDB testsuite results in the CI - Cleaned up change in tcwg_gnu-build.sh that reruns failed tests and created Gerrit review request¹. - Based on Laurent's and Maxim's suggestions, decided to put the code which retries the failed tests in Abe, so now I'm working on that. -- Thiago ¹ https://review.linaro.org/c/toolchain/jenkins-scripts/+/43265

2 years, 2 months

1
0
0 0

[ACTIVITY] report week ending 24 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Code review: big FEAT_LSE2 support series, 8.3 pointer auth, gdbstub support for M-profile sysregs, another round of FEAT_RME, and more - discussions about how to handle the fact that QEMU has run out of gitlab CI minutes, and some tweaking of my scripts to work around the lack of minutes -- PMM

2 years, 2 months

1
0
0 0

[ACTIVITY] Report for week #7

by Thiago Jung Bauermann

Hello, # [GNU-796] Stabilize GDB testsuite results in the CI - Merged Gerrit review requests removing unsupported and flaky tests from the fast_check_gdb CI job, and also one that makes it flag regressions in the stable tests. - Implemented change in Abe to build glibc with SystemTap probes enabled, but there's a kludge I still need to cleanup before submitting it for review. - Working on change to tcwg_gnu-build.sh to make it run failed tests again to see if they change to passing status. I have a working prototype. Now running further tests and cleaning up the code. -- Thiago

2 years, 2 months

1
0
0 0

Re: Seeking toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi

by Maxim Kuvyrkov

Hi Bryan, > On Feb 7, 2023, at 9:13 PM, Bryan Phillippe <bp(a)darkforest.org> wrote: > ... > -rwxr-xr-x 1 config root 2765178 Dec 9 2018 /lib/libuClibc-1.0.14.so > /root # strings /lib/libuClibc-1.0.14.so |grep -i linaro|head -n 1 > GCC: (OpenWrt/Linaro GCC 4.8-2014.04 r35193) 4.8.3 This indicates that it was built with an OpenWRT toolchain, and OpenWRT project maintainers used Linaro GCC 4.8 source release, instead of FSF GCC 4.8 source release. In the days of GCC 4.8 it was very common to use Linaro GCC source release instead of FSF ones for building compilers for 32-bit and 64-bit ARM. Try searching in OpenWRT archives for a copy of GCC 4.8-based toolchain. > /root # strings /lib/libuClibc-1.0.14.so |grep -i gcc-4.8|head -n 1 > /home/test/work/sudhan-qsdk/qsdk/build_dir/toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi/uClibc-ng-1.0.14 > /root # > > I only need to rebuild a single binary on this platform, and I don't have the source or the toolchain for the existing binaries. If I have to recreate a toolchain based on the versions only, it should be possible, but will be a good deal of work and effort. If you know where I can find this toolchain - or have any advice on how I can build my own compatible version - I would be very grateful. If you want to rebuild a single executable, then it may be easier to use a modern toolchain for arm-linux-gnueabihf [1] and build the static binary of your package (add "-static" to compiler flags). This was the binary will include all necessary bits of system libraries. This is a good approach if your package does not have dependencies outside of C library; otherwise you would need to find static versions of all other libraries. -- Maxim Kuvyrkov https://www.linaro.org > > Thank you so much! > > -- > -bp > >> On Feb 7, 2023, at 04:24, Maxim Kuvyrkov <maxim.kuvyrkov(a)linaro.org> wrote: >> >> [CC: linaro-toolchain@] >> >> Hi Bryan, >> >> I don't think that Linaro has ever released a toolchain with uClibc, but I may be wrong. Could you provide additional information about the target, rootfs and your setup? >> >> -- >> Maxim Kuvyrkov >> https://www.linaro.org >> >> >> >> >>> On Feb 7, 2023, at 10:31 AM, Bryan Phillippe <bp(a)darkforest.org> wrote: >>> >>> >>> Hello! I know this is a long shot, but I have a few devices with code that was built using this toolchain: toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi >>> >>> I'm trying to find a copy of that so I can rebuild 1 binary/package on the system without blowing everything up. Do you have any idea where I can find this toolchain? Thank you so much in advance! >>> >>> -- >>> -bp >>> >> >

2 years, 2 months

1
0
0 0

Clang C++ linkage problem

by Bartosz Golaszewski

Hey! I'm the author and maintainer of libgpiod. I'm currently getting ready to do a new major release. After giving some exposure to the release candidate, I noticed that when using clang, I can't link against the C++ bindings, while it works just fine in GCC. The tree in question is here: https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/log/ You can trigger the linking program by trying to build the C++ tests with clang like that: CC=clang CXX=clang++ ./autogen.sh --enable-bindings-cxx --enable-tests && make -j16 You'll get the following error: /usr/bin/ld: tests-chip.o:(.data+0x0): undefined reference to `typeinfo for gpiod::chip_closed' /usr/bin/ld: tests-line-request.o:(.data+0x0): undefined reference to `typeinfo for gpiod::request_released' /usr/bin/ld: .libs/gpiod-cxx-test: hidden symbol `_ZTIN5gpiod11chip_closedE' isn't defined /usr/bin/ld: final link failed: bad value The typoinfo is missing for exception types that should be visible to users of the library. The culprit is here: https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/tree/bindings/cxx… I added the GPIOD_CXX_BUILD macro in order to not re-export the visible symbols if any user of the library would include the gpiod.hpp header. When the library is being built, the symbols are visible, when someone includes the header, the symbols are hidden. If I make the symbols unconditionally visible here, clang starts to work but I have no idea why and would like to avoid re-exporting the symbols if I can. I'm using the following version: Ubuntu clang version 15.0.6 Target: x86_64-pc-linux-gnu Thread model: posix InstalledDir: /usr/bin Host is: x86_64 GNU/Linux It's not like gcc links fine but then fails to obtain typeid - I can catch exceptions coming out from libgpiod just fine in external apps linked using gcc and see their type. Any hints? Thanks Bart

2 years, 2 months

2
12
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[ACTIVITY] Report for week #6

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continued addressing review comments on v3 of the patches. Implemented some of the suggestions in my local branch, and also engaged in discussions. # [GNU-796] Stabilize GDB testsuite results in the CI - Fixed the problem in tcwg_gnu-build.sh noticed by Maxim where no_regression_p ignored regressions in the fast_check_gdb CI job. - Removed gdb.gdb/unittest.exp and gdb.server/unittest.exp from the fast_check_gdb stable tests list. The former only temporarily while its flakiness isn't fixed, and the latter because we don't run remote CI jobs. - Found out why gdb.base/break-probes.exp is unsupported in the fast_check_gdb CI job: we don't build glibc with SystemTap static probes. I have local changes to add them — and which do fix the GDB test — but I need to clean them up a bit before pushing them. -- Thiago

2 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 10 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Code review. In particular: reviewed RTH's FEAT_RME series - Wrote and sent an RFC patchset proposing renaming of the badly misnamed '-singlestep' command line option (it actually does "put only one guest instruction in each JIT basic block") -- PMM

2 years, 3 months

1
0
0 0

[ACTIVITY] week ending Feb. 12 2023

by Alex Bennée

Project Stratos =============== - more prep work for Project Orko FEAT_RME, CCA Realms ([QEMU-466]) ================================= - sync up meeting with Huawei - see QEMU, FEAT_RME/CCA and next steps Message-Id: <87mt5ln2t6.fsf(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py Message-Id: <20230203181632.2919715-1-alex.bennee(a)linaro.org> - continued working on [testing/next] with tuxrun tests - hacked up [PoC to use local QEMU in TuxRun] [UM-2] <https://linaro.atlassian.net/browse/UM-2> [testing/next] <https://github.com/stsquad/qemu/tree/testing/next> [PoC to use local QEMU in TuxRun] <https://gitlab.com/stsquad/tuxrun/-/commit/0f9711c18b7e723e1c50c8a8fd116b93…> Completed Reviews [3/3] ======================= [PATCH v3 0/9] virtio-gpu: Support Venus Vulkan driver Message-Id: <20220926142422.22325-1-antonio.caggiano(a)collabora.com> [PATCH] gdbstub: move update guest debug to accel ops Message-Id: <20221123121712.72817-1-mads(a)ynddal.dk> [PATCH v2 0/3] Add gdbstub support to HVF Message-Id: <20221116174749.65175-1-fcagnin(a)quarkslab.com> Current Review Queue ==================== TODO [PATCH 00/22] target/arm: Implement FEAT_RME Message-Id: <20230124000027.3565716-1-richard.henderson(a)linaro.org> ==================================================================================================================== TODO [RFC PATCH 00/16] Add stage-2 translation for SMMUv3 Message-Id: <20230205094411.793816-1-smostafa(a)google.com> ================================================================================================================== TODO [PATCH v2 0/2] fix for #285 Message-Id: <20230205163758.416992-1-cota(a)braap.org> ==================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

1
0
0 0

Re: Seeking toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi

by Maxim Kuvyrkov

[CC: linaro-toolchain@] Hi Bryan, I don't think that Linaro has ever released a toolchain with uClibc, but I may be wrong. Could you provide additional information about the target, rootfs and your setup? -- Maxim Kuvyrkov https://www.linaro.org > On Feb 7, 2023, at 10:31 AM, Bryan Phillippe <bp(a)darkforest.org> wrote: > > > Hello! I know this is a long shot, but I have a few devices with code that was built using this toolchain: toolchain-arm_cortex-a7_gcc-4.8-linaro_uClibc-1.0.14_eabi > > I'm trying to find a copy of that so I can rebuild 1 binary/package on the system without blowing everything up. Do you have any idea where I can find this toolchain? Thank you so much in advance! > > -- > -bp >

2 years, 3 months

1
0
0 0

[ACTIVITY] Report for week #5

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - The patches were already reviewed by 3 maintainers, so started addressing their review comments and answering questions. - Committed first two patches in the series, which were self-contained code improvements. -- Thiago

2 years, 3 months

1
0
0 0

[ACTIVITY] week ending Feb. 5 2023

by Alex Bennée

Project Stratos =============== - posted [PATCH v2] backends/vhost-user: remove the ioeventfd check Message-Id: <20230130124728.175610-1-alex.bennee(a)linaro.org> - bunch of sync and planning for Project Orko - see Project Orko requirements from TRS Message-Id: <87sffmke2i.fsf(a)linaro.org> - also debugging some TRS <-> QEMU interactions - posted [RFC PATCH] target/arm: disable FEAT_SME if we turn off SVE Message-Id: <20230203100551.2445547-1-alex.bennee(a)linaro.org> [proposal for Unprivilaged VirtIO API] <https://docs.google.com/document/d/18ijlX2Lguejyo3BV8Tri5Y_d1SmozocBIk2ajgq…> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL v2 00/36] Testing, docs, semihosting and plugin updates Message-Id: <20230202160109.2061994-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py Message-Id: <20230203181632.2919715-1-alex.bennee(a)linaro.org> Other ===== - Did some investigation into LKFT regressions - posted Initial investigation of slowness kselftest job Message-Id: <1ba91912e18492c7dafedc5fbd5aef817f109d53fdc95554870edf077a6e21dc(a)mu.id> - posted Candidate patches for Debian's 7.2 release (and backports) Message-Id: <87edr8kqqq.fsf(a)linaro.org> Completed Reviews [4/4] ======================= [PATCH v6 00/36] tcg: Support for Int128 with helpers Message-Id: <20230130214844.1158612-1-richard.henderson(a)linaro.org> [PATCH] vhost-user-gpio: Configure vhost_dev when connecting Message-Id: <20230130140320.77999-1-akihiko.odaki(a)daynix.com> [PATCH] configure: Bump minimum Clang version to 10.0 Message-Id: <20230131180239.1582302-1-thuth(a)redhat.com> [PATCH v3 0/9] virtio-gpu: Support Venus Vulkan driver Message-Id: <20220926142422.22325-1-antonio.caggiano(a)collabora.com> Current Review Queue ==================== TODO [PATCH 0/4] Fix deadlock when dying because of a signal Message-Id: <20230201004609.3005029-1-iii(a)linux.ibm.com> ==================================================================================================================== TODO [RFC PATCH v1 0/8] Look Ma! We made a XenStore Message-Id: <20230201144358.1744876-1-dwmw2(a)infradead.org> ============================================================================================================= TODO [QEMU][PATCH v5 00/10] Introduce xenpvh machine for arm architecture Message-Id: <20230131225149.14764-1-vikram.garhwal(a)amd.com> ==================================================================================================================================== -- Alex Bennée Virtualisation Tech Lead @ Linaro

2 years, 3 months

1
0
0 0

[ACTIVITY] report week ending 3 Feb

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual upstream maintenance tasks - the CI/tests have got rather flaky of late: trying to find out why... * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - FEAT_FGT: is now upstream -- PMM

2 years, 3 months

1
0
0 0

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