Just FYI.
This test is just bogus and fixing it might be simple as using -fsanitize=undefined to check at runtime there is no undefined behavior being hit.
In this case even if we do the comparison in `signed` and do the negate in `unsigned` types. we can still remove the negate in this case since we know the only value that will be still negative in that branch is LONG_MIN. So my patch just simplifies the inner comparison to that instead of `a < 0` and then be able to remove the neg.
Someone else will have to fix the testcase since it is a testcase issue ...
________________________________________
From: ci_notify(a)linaro.org <ci_notify(a)linaro.org>
Sent: Friday, September 1, 2023 3:07 PM
To: Andrew Pinski
Subject: [EXT] [Linaro-TCWG-CI] 2 patches in gcc: FAIL: 1 regressions
External Email
----------------------------------------------------------------------
Dear contributor, our automatic CI has detected problems related to your patch(es).
Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list.
In CI config tcwg_gcc_check/master-aarch64 after:
| 2 patches in gcc
| Patchwork URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.sourceware.o…
| 504821491ff VR-VALUES: Rewrite test_for_singularity using range_op_handler
| f6d1540c3e0 VR-VALUES: Rename op0/op1 to op1/op2 for test_for_singularity
| ... applied on top of baseline commit:
| b0d75f7d3bb libstdc++: Fix debug-mode tests for constexpr algorithms
FAIL: 1 regressions
regressions.sum:
=== gcc tests ===
Running gcc:gcc.target/aarch64/aarch64.exp ...
FAIL: gcc.target/aarch64/vnegd_s64.c scan-assembler-times neg\\tx[0-9]+, x[0-9]+ 1
=== Results Summary ===
-----------------8<--------------------------8<--------------------------8<--------------------------
The information below can be used to reproduce a debug environment:
Current build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…
Reference build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- code review:
+ RTH's linux-user ESR signal frame patchset
+ iMX6/7 cleanup patchset
+ some other minor bits and pieces
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- FEAT_MOPS:
* SETG* instructions (memset + MTE tag setting) implemented and
given some basic testing
-- PMM
Hi Jan,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I am having some trouble to reproduce it outside
our CI environment, but it has been hitting this issues consistently
and it does seems related to your patch.
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_pr…
Hi Richard,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I did a quick analysis and it seems that for
test_copy_lane_f32, test_copy_lane_s32, test_copy_lane_u32, gcc
is now generating zip1 instead of a ins; which does not seem
fully correct.
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/91…
Hello,
# TCWG CI
- GCC regression GNU-884: Prathamesh confirmed that the new generated
code is better so I posted a patch adjusting the testcase.
- GCC regression GNU-885: Confirmed that the problem is still present in
trunk as of commit 829c0c06fe7b from yesterday, so opened bugzilla
111125 and copied the patch author. He fixed the regression.
- Posted Gerrit review request to increase timeout for GDB check jobs to
accommodate longer times for Armv8l builds.
# GDB Upstream
- Reviewed v4 of Luis' patch series adding SME support to GDB and
gdbserver.
--
Thiago
Hi Andrew,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I did a quick analysis and it seems that the
expected 18 for aarch64 is now 17:
$ grep "Jumps threaded" a-ssa-dom-thread-7.c.197t.thread2
Jumps threaded: 17
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_gnu_native_check_gcc--master-aarch64-build/5…
Hi Richard,
Your patch below ICEs on aarch64-linux-gnu. Should reproduce easily on native or cross aarch64-linux-gnu build.
Let me know if you need any assistance in reproducing this.
Thanks,
--
Maxim Kuvyrkov
https://www.linaro.org
> On Aug 24, 2023, at 22:03, ci_notify(a)linaro.org wrote:
>
> Dear contributor, our automatic CI has detected problems related to your patch.
> Please find below some details about it. If you have any questions, please
> follow up on linaro-toolchain(a)lists.linaro.org mailing list.
>
> In CI config tcwg_gcc_check/master-aarch64 after:
>
> | commit a1558e9ad856938f165f838733955b331ebbec09
> | Author: Richard Biener <rguenther(a)suse.de>
> | Date: Wed Aug 23 14:28:26 2023 +0200
> |
> | tree-optimization/111115 - SLP of masked stores
> |
> | The following adds the capability to do SLP on .MASK_STORE, I do not
> | plan to add interleaving support.
> |
> | PR tree-optimization/111115
> | ... 21 lines of the commit log omitted.
>
> FAIL: 6 regressions
>
> regressions.sum:
> === gcc tests ===
>
> Running gcc:gcc.target/aarch64/sve/aarch64-sve.exp ...
> FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (internal compiler error: in get_group_load_store_type, at tree-vect-stmts.cc:2121)
> FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (test for excess errors)
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2b\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2d\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2h\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2w\\t.z[0-9]
>
> ... and 1 more entries
>
>
>
> -----------------8<--------------------------8<--------------------------8<--------------------------
> The information below can be used to reproduce a debug environment:
>
> Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/artifact…
> Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/856/artifact…
>
> Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/…
>
> Full commit : https://github.com/gcc-mirror/gcc/commit/a1558e9ad856938f165f838733955b331e…
>
> Latest bug report status : https://linaro.atlassian.net/browse/GNU-893
>
> List of configurations that regressed due to this commit :
> * tcwg_gcc_check
> ** master-aarch64
> *** FAIL: 6 regressions
> *** https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- code review:
+ Xilinx Versal CFI support series
+ v2 of RTH's Cortex-A710 series
- a few more -Wvla patches
- put together and sent the first arm pullreq for the 8.2 cycle
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- FEAT_MOPS:
+ updated to use a refactoring suggested by RTH
+ started looking at SETG operation (memset with MTE tag setting)
-- PMM
Hi Julian,
Your patch series causes regressions on aarch64-linux-gnu. Would you please investigate?
Let me know if you need any assistance in reproducing these.
Thanks!
--
Maxim Kuvyrkov
https://www.linaro.org
> On Aug 19, 2023, at 09:32, ci_notify(a)linaro.org wrote:
>
> [Linaro-TCWG-CI] FAIL: 10 regressions after gcc commit: 5 commits in gcc
>
> Dear contributor, our automatic CI has detected problems related to your patch.
> Please find below some details about it.
>
> In CI config tcwg_gcc_check/master-aarch64 after:
>
> | gcc commits:
> | dce6c135fb52fd631c2fc82d8048d32ce41ece21 OpenMP/OpenACC: Reorganise OMP map clause handling in gimplify.cc
> | dd49dd178e3eac8e9925baa3d71325d8d5f69215 OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic
> | bd5a53e6b47907d05672cbb603af363a665b45a4 OpenMP: Pointers and member mappings
> | 4e0359d8a659c8abdca3297fc9b0e20ff89f7f82 OpenMP/OpenACC: Rework clause expansion and nested struct handling
> | a855174e5461d2b423af7f892fd31dfb10ce09ec OpenMP/OpenACC: Reindent TO/FROM/_CACHE_ stanza in {c_}finish_omp_clause
>
> FAIL: 10 regressions
>
> regressions.sum:
> === libgomp tests ===
>
> Running libgomp:libgomp.c++/c++.exp ...
> FAIL: libgomp.c++/../libgomp.c-c++-common/map-arrayofstruct-2.c output pattern test
> FAIL: libgomp.c++/../libgomp.c-c++-common/map-arrayofstruct-3.c output pattern test
>
> Running libgomp:libgomp.c/c.exp ...
> FAIL: libgomp.c/../libgomp.c-c++-common/map-arrayofstruct-2.c output pattern test
> FAIL: libgomp.c/../libgomp.c-c++-common/map-arrayofstruct-3.c output pattern test
>
> ... and 9 more entries
>
>
>
> -----------------8<--------------------------8<--------------------------8<--------------------------
> The information below can be used to reproduce a debug environment:
>
> Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1593/art…
> Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/836/artifact…
Hi Manos,
New tests in your patch [1] fail on aarch64-linux-gnu build in our CI. Would you please investigate why? Testing logs are at [2].
[1] https://patchwork.sourceware.org/project/gcc/patch/20230818074943.41754-1-m…
[2] https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art…
--
Maxim Kuvyrkov
https://www.linaro.org
> On Aug 19, 2023, at 08:37, ci_notify(a)linaro.org wrote:
>
> [Linaro-TCWG-CI] FAIL: 6 regressions after gcc commit: basepoints/gcc-14-3331-gcddc26e0274 aarch64: Fine-grained ldp and stp policies with test-cases.
>
> Dear contributor, our automatic CI has detected problems related to your patch.
> Please find below some details about it.
>
> In CI config tcwg_gcc_check/master-aarch64 after:
>
> | commit cddc26e0274b51e775929e497f89d203211689d2
> | Author: Manos Anagnostakis <manos.anagnostakis(a)vrull.eu>
> | Date: Fri Aug 18 10:49:43 2023 +0300
> |
> | aarch64: Fine-grained ldp and stp policies with test-cases.
> |
> | This patch implements the following TODO in gcc/config/aarch64/aarch64.cc
> | to provide the requested behaviour for handling ldp and stp:
> |
> | /* Allow the tuning structure to disable LDP instruction formation
> | ... 47 lines of the commit log omitted.
>
> FAIL: 6 regressions
>
> regressions.sum:
> === gcc tests ===
>
> Running gcc:gcc.target/aarch64/aarch64.exp ...
> FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tq[0-9]+, q[0-9] 1
> FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tw[0-9]+, w[0-9] 3
> FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tx[0-9]+, x[0-9] 3
> FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tq[0-9]+, q[0-9] 2
> FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tw[0-9]+, w[0-9] 6
> FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tx[0-9]+, x[0-9] 6
>
> ... and 1 more entries
>
>
>
> -----------------8<--------------------------8<--------------------------8<--------------------------
> The information below can be used to reproduce a debug environment:
>
> Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art…
> Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/836/artifact…
>
> Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/…
>
> Full commit : https://github.com/gcc-mirror/gcc/commit/cddc26e0274b51e775929e497f89d20321…
>
> Latest bug report status : https://linaro.atlassian.net/browse/GNU-692
>
> List of configurations that regressed due to this commit :
> * tcwg_gcc_check
> ** master-aarch64
> *** FAIL: 6 regressions
> *** https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Continued working on new approach to support changing SVE vector
length in remote debugging.
# TCWG CI
- Analysed GCC regression GNU-880 which is actually an XFAIL → XPASS so
I sent a patch removing the xfail annotation.
- Analysed GCC regression GNU-881. The problem is that we don't have
Python in the ABE sysroot so a new Python GCC plugin testcase fails to
build. Sent a patch to detect that situation and mark the test as
unsupported. It was committed upstream.
- Tested a couple of new versions of a GDB mailing list patch to see if
it fixed the failure reported by the precommit CI. Reported results to
patch author.
- Fixed silly mistake spotted by Laurent in ABE Gerrit requests to use
TIMEOUTFACTOR for DejaGnu testsuites. Adjusted it to not use the
factor in GDB on armhf and sent new version for review.
- Reviewed a couple of Gerrit requests.
--
Thiago
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- sent out another couple of "avoid VLA" patches
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- managed to write some first-pass code for the MTE checks for
FEAT_MOPS memset operations. Got something together enough to
send to RTH for some pre-review before I roll the approach out
to the other insns.
-- PMM
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Returned to implementing support for changing SVE vector length in
remote debugging. The patch series I sent earlier this year used an
approach that some maintainers weren't enthusiastic about (modifying
the Remote Serial Protocol to request XML target descriptions). Now
trying the approach they suggested, which is to extend target
descriptions to support expressing vector registers whose length is
given by the contents of another register.
# TCWG CI
- Following Maxim's suggestion, sent and merged Gerrit review requests
to increase chance of tcwg_gdb_check jobs to be faster at detecting
new or newly expired flaky tests:
- 45151: tcwg_gdb: Increase job frequency
- 45152: round-robin.sh (build_abe): Increase time to re-detect GDB
flaky tests
- Implemented change in ABE to support glibc's TIMEOUTFACTOR environment
variable for DejaGnu testsuites. Testing on armv8l and aarch64.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- code review, notably:
+ RTH's setnegcond series
+ Jean-Philippe's fixes for various FEAT_RME bugs
+ Akihiko's series to make KVM '-machine none' not default to 40 bits
of IPA space if the host doesn't supoprt that (like the Apple CPUs)
- sent a patch to catch the illegal exception return case from
EL3 with bad SCR_EL3.{NSE,NS}
- respin and resend of ptw cleanup patchset
- tidied another 'BiteSizedTask' entry into a gitlab issue
- went back to an old minor cleanup task: getting rid of the
last dozen or so uses of variable-length arrays in the codebase
(so we can enforce not using them in the compiler, and avoid
unchecked-on-stack-allocation security bugs). Sent patches to
zap a few more.
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- thinking a bit more about FEAT_MOPS and MTE checks, but ultimately
not much progress: didn't find enough hours with a sufficiently
alert mind...
-- PMM
Hello,
# TCWG CI
- Implemented increasing testsuite timeout for each testsuite try in GDB
check jobs. Sent a Gerrit review request for it but then found out that
it makes armhf jobs take a lot longer, so abandoned it.
# Community
- Finished reviewing SME patches for GDB and gdbserver.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- some bits and pieces for release
- code review, notably:
+ raspberry pi 4 support patchseries (a big 44-patch set)
+ Xilinx Versal CFI support patches
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- more work on FEAT_MOPS: tested my memset implementation, and
fixed various bugs. Still no MTE tag checking support.
-- PMM
Hello,
# TCWG CI
- CI Babysitting: Worked on two regressions detected at the end of last
week.
- Enabled precommit testing for GDB patches.
# Misc
- Reviewing SME patches for GDB and gdbserver.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- release related stuff: handling merge requests, etc (now passed
back to RTH again)
- sent some patches for a few easy coverity issues
- worked through some code review (in particular some patches
from new contributors)
- created a gitlab "bite sized task" issue that better explains
and has more detail on the "convert from malloc to g_malloc"
suggested task for new contributors
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- a little more progress with FEAT_MOPS. I now have an untested
implementation of the memset insns which I think is complete
except for MTE tag checking
-- PMM
Hello,
# TCWG CI
- Babysat the CI: Investigated 9 regressions in GCC, 2 in GDB, 1 in LLVM
and 1 in glibc. Reported 4 in GCC (GNU-855, GNU-857, GNU-858 and
GNU-859). 3 of which are fixed and another has a tentative fix.
- Reviewed a couple of Gerrit requests.
--
Thiago