Hi Michael,
Spec2000 is now running successfully: there are results at
http://ex.seabright.co.nz/benchmarks/gcc-linaro-4.7%2bbzr114965/logs/armv7l…
However, they seem to have been run in 'train' mode, and none of the
runs are long enough for comparison.
I thought the a9-ref queue was supposed to run in full 'ref' mode?
Andrew
Hi,
OpenEmbedded:
* removed the recipe for building the linux-linaro-3.1 kernel
* add support for the default OE-core kernel
* allows to build the linux-yocto_3.2 kernel for the
qemuarmv7a MACHINE using a vexpress defconfig
* updated the wiki on how to build OE-core with meta-linaro
https://wiki.linaro.org/KenWerner/Sandbox/OpenEmbedded-Core
* worked OEMetaLinaroCard
* started to talk to CI folks about automating the oe-core+meta-linaro
* wrote a script that automates the process
* ran it on tcserver01 to build the qt4e and sato images against the
source gcc-linaro-4.6-2012.02
Regards,
Ken
Hi Ken. In follow up to our 1-on-1 yesterday, here's what I'd like done next.
The goal is to use OE Core as a release test suite. The releases are
tarballs so we can keep the current recipe format and punt bzr support
for later. The first step is to be able to reliably build a release
in the cloud or validation lab.
In all cases keep the other teams in mind. Much of this is related to
Validation. Platform will be involved later. Ping them early.
Kernel:
We're starting with GCC and need a kernel to supply headers and to
boot some type of ARMv7 image. I don't want a linux-linaro recipe as
people will use it and it's too early for that.
Find a kernel, preferably from OE Core, that is recent, ARMv7, >= 512
MB RAM, and works well with qemu-linaro. Prefer vexpress-a9, else
OMAP?
Talking:
Say Hi to Validation re: EC2 and plans
Say Hi to the ARM landing team re: vexpress upstream support
Say Hi to Beth Flanagan re: Yocto's existing auto builders and any hints
Cloud builds:
Find out who is already doing OE builds in the cloud and how
Run a build locally and time
Push ~/downloads into the cloud, build, and time[1]
Figure how much this build will cost in dollars
[1] c1.xlarge might be best. Builds are normally I/O bound and the
cloud is I/O poor. Put /tmp and other chunks in a tmpfs? EC2 rounds
up to the nearest hour as well.
If the cloud is too expensive then we'll get a machine installed.
S3 for storage:
(only proceed if affordable)
Use S3 for storing the input tarballs
Use S3 either as a pre-mirror by serving over HTTP, or use s3cmd to
sync down the tarballs before starting the build
Scripting:
Re-use existing scripts if feasible. Integrate with LAVA providing we
can run exactly the same scripts on a laptop for debugging.
Script the bitbake, OE meta layer, and Linaro meta layer setup.
Script the configuration including setting the release tarball URL and
GCC preferred version.
Script the build and result capture, especially the log, any ICEs, and
the final sizes
Future:
OE can grab a repository seed then update based on that. Check if the
bzr backend supports this. If so, play with seeding to do tip builds.
Let me know what you think then we'll spawn blueprints. Let's keep an
eye on this as it's sounding expensive.
-- Michael
Hi Ken, Thiago. Could you try your hand at writing cards for the
OpenEmbedded Core meta-layer and GDB and Android? Here are some past
cards:
https://linaro-public.papyrs.com/TCWG2011-GCC-O3https://linaro-public.papyrs.com/TCWG2011-OPENOCD-SUPPORThttps://linaro-public.papyrs.com/TCWG2011-WINDOWS-TOOLCHAIN
They cover:
* An introduction
* The why/advantages
* The what/features
* The how/steps
* Dependencies
* Acceptance criteria (which is a post-tense version of the body)
A card should cover three calendar months. Check the unknowns - we
need to investigate the acceptance criteria and make sure there is no
unexpected side work in there.
We use roadmap cards as the highest level of organising our work.
Cards are the interface between working groups and the TSC and sit at
the project brief / deep but concise level.
Draft them on the wiki (cf https://wiki.linaro.org/KenWerner/Sandbox)
and we'll go from there.
-- Michael
== Issues ==
It would be nice to have perf installed on the porter boxes in the
canonical data center as well if we are allowed to run benchmarks
there. Filed RT request.
==Progress===
* Understood STB_GNU_UNIQUE_NOTE - Helped fix a problem with compiz
crashing but then it was a very nice testcase to investigate the
toolchain issue with. Thanks Alexandros.
* Merged pending patches.
* ABI fix
* Fix for ICE - LP bug 942307
* Off sick on Monday.
* Did some work to improve code generation for addressing modes in VFP
registers.
* Did some work in setting up SPEC2k for running hc partitioning
patches. Still needs to be completed.
=== Plans ===
* Ping configure.ac changes.
* Complete pending benchmark run with hc partitioning and look at
results with hc partitioning and run things. Was unable to run the vfp
benchmarks today as ex.seabright.co.nz was down.
* Resurrect partial-partial PRE
Absences.
* 1 week holiday sometime before that - to be booked.
* Linaro Connect Q2.12 - May 28 - June 1 - travel booked - hotel to be booked.
Hi Ken. This month's release is next week. Let's be aggressive and
see if we can use your meta-linaro layer to check the source release.
I want to use tcserver01 in the validation lab instead of the cloud
until we know how much it costs. I've added you an account and done a
test build to check that the dependencies are there. There's a shared
directory in /home/shared that includes downloads and a sstate-cache.
The machine seems fast enough for the job.
The tarball should be ready around Tuesday next week. Once ready,
could you mix it in with the meta-linaro layer, do a build, boot the
rootfs in qemu, and document as you go? Anything past that is
welcome.
It's all manual but a nice proof of concept. Can we check the binary
build as well?
-- Michael
Current Milestones:
|| || Planned || Estimate || Actual ||
||cp15-rework || 2012-01-06 || 2012-??-?? || ||
(new blueprints & reestimate for this one pending still; will try to
do this early next week)
Historical Milestones:
||a15-usermode-support || 2011-11-10 || 2011-11-10 || 2011-10-27 ||
||upstream-omap3-cleanup || 2011-11-10 || 2011-12-15 || 2011-12-12 ||
||initial-a15-system-model || 2012-01-27 || 2012-01-27 || 2012-01-17 ||
||qemu-kvm-getting-started || 2012-03-04?|| 2012-03-04?|| 2012-02-01 ||
== cp15-rework ==
* converted cp15 crn={6,7,9}, still TODO just crn={0,1}. These take
longer than I was expecting because to find some useful compromise
between QEMU's previous (usually broken) behaviour and reality I
have to cross reference half a dozen different TRMs and several
revisions of the ARM ARM.
== other ==
* getting qemu-linaro into shape for next week's release:
applying patches, writing changelog, etc
* patch review for more exynos4 devices
* tracked down a regression in the spitz (zaurus) model,
sent patch
* first pass comments on blueprints for this quarter
* investigating LP:947888 (gpg crashes under qemu)
-- PMM
Hi Alexandros,
Could you use the linaro-toolchain list for stuff like this please?
You're more likely to find somebody who knows the answer that way.
I'm pretty sure the problem is not the compiler because, as far as I can
see, both architectures' compilers emit ".weak" directives. If there is
a problem, I'd say it's in the linker.
Your test case gives two different addresses on Lucid x86, and on ARM
(so you say, I've not tested it), but the same address twice on Precise.
This is a surprising result. *I* would have expected that static values
in different dlopen'd libraries would not be unified, but apparently
they are ... somtimes.
I'm afraid I don't really have any insight here. :(
Anyway, regardless of whether one is correct, or not, I'd suggest *not*
relying on this behaviour - it's clearly not portable. I say leave it at
arm's length in production software for a few years.
Andrew
On 06/03/12 14:27, Alexandros Frantzis wrote:
> On Tue, Mar 06, 2012 at 09:51:01AM +0800, Sam Spilsbury wrote:
>> On Mon, Mar 5, 2012 at 11:50 PM, Alexandros Frantzis
>> <alexandros.frantzis(a)linaro.org> wrote:
>>> Hi all,
>>>
>>> this is an update on my progress with the updated compiz branches.
>>>
>>> I have been trying to run our update compiz branches
>>> (compiz-*/linaro-gles2-update) on ARM (precise armhf), but I have stumbled onto
>>> the same issue Marc reported some days ago. In particular, I get:
>>>
>>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeWindow_index_4" already stored in screen.
>>> /usr/bin/compiz (core) - Fatal: Private index value "15CompositeScreen_index_4" already stored in screen.
>>>
>>> and then a segfault when I try to run compiz.
>>>
>>> Note that I *don't* have this problem when running on x86_64 precise.
>>>
>>> The issue can be recreated with:
>>>
>>> $ compiz composite opengl
>>>
>>> I added some debugging messages to pluginclasshandler.h to get a better
>>> feeling of what is going on, and ran on both my desktop and on ARM.
>>> This is the output near the point when GLScreen get initialized:
>>>
>>> ...
>>>
>>> compiz (core) - Info: get(): mIndex.initiated for "8GLScreen_index_4" : 0
>>> compiz (core) - Info: initializeIndex(): Initializining index value "8GLScreen_index_4"
>>> compiz (core) - Info: initializeIndex(): Private index value added for "8GLScreen_index_4"
>>> compiz (core) - Info: getInstance(): Get instance for "8GLScreen_index_4"
>>> compiz (core) - Info: getInstance(): Spawning new class for "8GLScreen_index_4"
>>> compiz (core) - Info: ctor(): mIndex.initiated for "8GLScreen_index_4" : 1
>>> compiz (core) - Info: ctor(): Increasing reference count for "8GLScreen_index_4": 1
>>>
>>> --- x86_64 ---
>>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 1
>>> --- armhf ---
>>> compiz (core) - Info: get(): mIndex.initiated for "15CompositeScreen_index_4" : 0
>>> compiz (core) - Info: initializeIndex(): Initializining index value "15CompositeScreen_index_4"
>>> compiz (core) - Fatal: initializeIndex(): Private index value "15CompositeScreen_index_4" already stored in screen.
>>
>> After the composite plugin loads and mIndex.initiated is set to 1,
>> place a watchpoint on mIndex.initiated (it should be a separate
>> template instantiation for each different class) and check if it
>> changes, or check if we are reading mIndex.initiated from a different
>> address, and if so, check the addresses of this for each constructor
>> and destructor being called. (could be a compiler bug, I've hit these
>> on this part of the code before).
>>
>>> -------------
>>>
>>> In the armhf case, CompositeScreen is erroneously considered not
>>> initialized, and is initialiazed again, therefore messing up the plugin system.
>>>
>>> I am trying to figure out if this is a manifestation of some kind of memory
>>> corruption that doesn't affect us on x86_64 for whatever reason (alignment,
>>> integer size etc), or something completely different.
>>>
>>> Thoughts?
>>>
>>> Thanks,
>>> Alexandros
>>
>>
>>
>> --
>> Sam Spilsbury
>>
>
> Hi all,
>
> (I have also added Michael, Andrew and Ulrich from the Linaro toolchain group
> to the recipients. Hi!)
>
> Checking the addresses, as Sam suggested, I found that there are two different
> PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex and
> PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex objects.
>
> After a bit of investigation, objdump gave an explanation:
>
> objdump -t /usr/lib/compiz/libcomposite.so | c++filt | grep mIndex
>
> -- x86_64 --
> 0000000000277a80 u O .bss 0000000000000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex
> 0000000000277a70 u O .bss 0000000000000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex
> -- armhf --
> 00065648 w O .bss 00000010 PluginClassHandler<CompositeWindow, CompWindow, 4>::mIndex
> 00065658 w O .bss 00000010 PluginClassHandler<CompositeScreen, CompScreen, 4>::mIndex
> ------------
>
> And the same kind of output for libopengl.so
>
> On x86_64 the symbols are marked 'u': 'unique global', whereas on armhf
> they are marked 'w': 'weak'. This seems to be causing our troubles.
>
> I have produced a small test case for this:
>
> http://people.linaro.org/~afrantzis/cpp_unique_global.tar.gz
>
> Building and running 'LD_LIBRARY_PATH=. ./main' on x86_64 prints out f1 and f2
> with the same address, whereas on armhf the addresses are different (i.e. two
> different objects). On x86_64 the symbol A<int>::a is 'u', on armhf it is 'w'.
>
> For completeness, when running without templates (edit a.h to change) the two
> printed addresses are different on both x86_64 and armhf. Also A::a is 'g':
> 'normal global' for both.
>
> Michael, Andrew, Ulrich can you please give us some insight into the situation?
> Does this seem like a compiler or linker bug on ARM, or is the code depending
> on undefined behavior, or something different? I have pasted the used g++
> versions at the end of the email.
>
> Thanks,
> Alexandros
>
> --- g++ x86_64 --
> Using built-in specs.
> COLLECT_GCC=g++
> COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-linux-gnu/4.6/lto-wrapper
> Target: x86_64-linux-gnu
> Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++,go --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --disable-werror --with-arch-32=i686 --with-tune=generic --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=x86_64-linux-gnu
> Thread model: posix
> gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2)
>
> --- g++ armhf --
> Using built-in specs.
> COLLECT_GCC=g++
> COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabihf/4.6/lto-wrapper
> Target: arm-linux-gnueabihf
> Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.6.3-1ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.6/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.6 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.6 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --enable-multilib --disable-sjlj-exceptions --with-arch=armv7-a --with-float=hard --with-fpu=vfpv3-d16 --with-mode=thumb --disable-werror --enable-checking=release --build=arm-linux-gnueabihf --host=arm-linux-gnueabihf --target=arm-linux-gnueabihf
> Thread model: posix
> gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu2)
>
Hi!
* Bug reports
Made an effort clean up among the remaining not-triaged bug. Michael will
help out with 941676, where the failure is on power-pc.
* Wiki
Created a wiki page for running benchmarks in cbuild:
https://wiki.linaro.org/WorkingGroups/ToolChain/Benchmarks/RunningBenchmark…
* V8
Build system has changed in V8 from SCones to GYP. With GYP I can pass the
normal flags like CXXFLAGS to control the build, so this looks like a good
change.
I have created a cbuild make file, patterned after the other benchmark make
files.
Working on x86 sofar, will go for arm next week. Will also add a parser for
the results.
Regards
Åsa
== GCC ==
* Checked patch to generate usat/ssat instructions into
Linaro GCC 4.6 and 4.7.
* Submitted (first part of) fwprop-subreg patch for mainline.
* Submitted Ira's vectorizer patches for mainline.
* Ongoing work on improving end-of-loop value computation.
* Patch review week.
== Misc ==
* On leave 3/9 - 3/14.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi
Updated sysroots for binary toolchain are available at [1]. This time I
split -dev and -dbg sysroots so as long as dbgsym are not needed less
disk space is used.
Please take a look at them and report any issues.
1. http://people.linaro.org/~hrw/generic-linux/sysroots/20120301/
Hello,
My name is Jiandong Zheng and am working on a few ARM specific projects.
I have been using Linaro toolchain coming with Ubuntu to do Cortext-A9
building. I also need to maintain code for old ARM11 SoC so that Linaro
toolchain is my preference and it did the job well back in Maverick days
if I remember correctly.
However, in Precise, I have troubles running this ARM11 u-boot and
kernel built with Linaro toolchain, eventually I found that my old gcc
4.3.2 toolchain can still build workable u-boot and kernel so that
Linaro toolchain (gcc 4.6.2) seems the problem. I understand that
Linaro's focus has been ARMv7 or above but I am wondering if its
toolchain can still be used for older ARM architectures.
Thanks,
JD
Hi Michael,
A new bug triaging question.
https://bugs.launchpad.net/ubuntu/+source/ppl/+bug/941676
This one is special too because the failure is on powerpc.
This means, I cannot reproduce it easily, and scan through the toolchains
(without building).
Matthias has given some information and a guess of what is failing. My idea
was to just summarize this, and let the person who takes on the bug make
the powerpc investigation.
How do we handle bugs on other architectures in general?
Best regards
Åsa
Hi!
I need a little help with triaging of this bug, it is a little different
from the ones I have triaged so far:
https://bugs.launchpad.net/launchpad/+bug/945503 - gcc-4.7 branch imports
fail (timeouts)
It is already set to Confirmed, my question is what is needed to go to the
triaged stage?
Also, the comments from wgrant and jelmer somewhat indicates that there is
no problem.
Best regards
Åsa
Hello,
since this long-standing problem just hit me again, I had a quick look at
test failures in our farm that appear to occur whenever the directory name
contains a string that is being checked for via a "scan-assembler" test,
e.g.:
+FAIL: gcc.target/arm/sat-1.c scan-assembler-times ssat 4
+FAIL: gcc.target/arm/sat-1.c scan-assembler-times usat 4
I had been assuming this happens because the directory name somehow finds
its name into the assembler file, e.g. via a .file directive or DWARF data,
and therefore an additional instance of the search string is being detected
erroneously.
However, when I attemted to re-create the scenario by building myself
within a directory that has the same name, but on my local machine, the
tests when through fine. And indeed, inspecting the assembler source shows
that that there is no debug info at all; while there is a .file directive,
it contains just the file base name without any directory name; and in fact
the directory name does not show up at all within the assembler file.
Something must still be different in the runs that take place on the build
farm; but I currently do not understand what that might be.
Michael, is there a way to interact with the build process on the build
farm machines themselves to try and find out what's going on here?
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
Hi toolchain folks,
I have a problem with U-boot compiled for an ARMv4 system (Integrator)
using Linaro 2012.02-20120222, it just crashes. Compiling the same
U-Boot with CodeSourcery 2010-q1 works fine.
Symptom:
Resetting CPU ...
undefined instruction
pc : [<07fdecd4>] lr : [<07fdeb34>]
sp : 07f91380 ip : 00000000 fp : 00000001
r10: 010258fc r9 : 00000000 r8 : 07f94f64
r7 : 07f94eb0 r6 : 00989680 r5 : 000186a0 r4 : 000186a0
r3 : 000003e8 r2 : 000f423f r1 : 000f4240 r0 : 05f5e100
Flags: nzCv IRQs on FIQs on Mode SVC_32
(repeated ad nauseam)
The only hint I have is the constant 000186a0, which appears
here in the put_dec() routine from U-boots vsprintf(), which is
nothing special, it's Douglas Jones' binary to decimal conversion
code from the Linux kernel, but the compiles objects DOES
contain calls to __aeabi_uidivmod, __udivsi3, __div64_32.
Do we know of any potential trouble in these helpers on ARMv4?
The file containing these functions is compiled like this:
arm-linux-gnueabi-gcc -M -g -Os -fno-common -ffixed-r8 -msoft-float
-D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x01000000
-I/var/linus/u-boot/build-integrator/include2
-I/var/linus/u-boot/build-integrator/include
-I/var/linus/u-boot/include -fno-builtin -ffreestanding -nostdinc
-isystem /home/linus/src/gcc-linaro-arm-linux-gnueabi-2012.02-20120222_linux/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/include
-pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux
-mno-thumb-interwork -march=armv4 -MQ
/var/linus/u-boot/build-integrator/lib/vsprintf.o vsprintf.c
>/var/linus/u-boot/build-integrator/lib/.depend.vsprintf
Yours,
Linus Walleij
Hi,
GDB on Android:
* Spent some time understanding the intricate build process used
to compile NDK's gdbserver.
* After a lot of tinkering and trial and error I was finally able
to produce a gdbserver binary which when running on the Android
emulator and talking to a GDB (also compiled by me) on the host
is able to show all threads and provide a useful backtrace.
--
[]'s
Thiago Jung Bauermann
Linaro Toolchain Working Group
Hi there. When you do a commit that fixes a bug, try adding a
'--fixes lp:123456' to the bzr commit. Launchpad recognises these and
automatically link the branch and merge request to the bug report.
This makes it easier for the reporter to see progress. If you forget
to update the bug status (such as bumping it from 'Triaged' to 'In
progress') then it's obvious that it's being worked on.
See https://bugs.launchpad.net/gcc-linaro/+bug/942307 for an example.
The status was 'Triaged' but there's an approved merge request which
shows work is being done.
-- Michael
Merged FSF GCC 4.7 to the Linaro GCC 4.7 branch.
Merged from GCC 4.6.3 release to Linaro GCC 4.6 branch.
Wrote and posted a patch to load DImode immediate constant into NEON
registers properly. Unfortunately, testing showed a bootstrap stage 2
vs. 3 miscompare, so there's something not quite right. However,
disassembly of the binaries hasn't revealed any problems, so this
failure is still a mystery. More investigation required.
Wrote and posted a patch to do DImode negation in NEON. Realised that I
had forgotten to do the core-register fall-back case; posted a new
version. Again, there's something annoyingly subtle that prevents
bootstrap. This time it looks like some sort of wrong code bug.
Investigating.
Wrote and posted a patch to do DImode one's complement in NEON. Richard
E questioned how it was written though. The tests passed successfully,
so that's a novelty this week!
Looked for other NEON instructions missing support. Didn't find any ...
but the machine description isn't exactly straight forward.
Considered the problems with choosing whether or not to do an operation
in NEON, or not. Discussed the existing state and possible solutions
with Ramana and Benrd (thanks Guys). Thought about it some more. Posted
a vague description of what might fix it to the linaro-toolchain list.
Awaiting replies.
Hi!
* Development benchmarks:
Finished the first implementation, sent to Michael for review.
* This became a very short week because of sickness.
Plans for week 10 is to triage existing bugs, and to get going again with
the SunSpider benchmark.
Regards
Åsa
Summary:
* Multilib on linaro toolchain.
Details:
1. Multilib test for linaro toolchain.
* Fix the multilib build issue when multiarch patch is applied.
* Fix a bug in crosstool-ng upstream to build multilib for glibc/eglibc.
* Successfully build multilib toolchain for armv6t2, cortex-a8 and
cortex-a9. And tests show it can link the correct libraries.
2. Still issues:
* Multilib and multiarch uses different directory structures.
Multilib build can not find the correct directories in the prebuilt
oneiric-sysroot.
* Build armv5t arm mode lib when default mode is thumb for armv7-a.
Annual leaves:
* Mar. 1-2.
Plans:
* Finalize the multilib solution for linaro binary toolchain.
* Work on code size optimization for the embedded toolchain.
Best regards!
-Zhenqiang
> The basic idea is that we add a new RTL optimization pass (or two) that
> assesses the usage of pseudo registers, and makes recommendations about
> what register class each should end up in, if there's a choice. These
> recommendations would then be used by later passes to get a better use
> of NEON. I might call this the "prealloc" pass, or something.
That sounds very much like the pre-reload that "new-ra" had at one
point (http://gcc.gnu.org/viewcvs/branches/new-regalloc-branch/gcc/pre-reload.c).
The problem with pre-reload for new-ra was that it was basically
reload instead of something nicer and cleaner. It also only ran just
before the register allocator, which is too late for the problem you
are trying to solve.
> Firstly, for each pseudo-register in a function, the pass would look at
> the insn constraints for each "def" and "use", and see how the registers
> relate to one another. This might determine things like "if rN is in
> class A, then rM must be also in class A".
At SUSE I tried to do this with the webizer pass (web.c). I wrote down
the ideas we implemented at the time (see
http://gcc.gnu.org/ml/gcc/2005-01/msg00179.html):
- web class, to replace regclass and choose register classes webs
instead of pseudos. This also includes splitting webs if a register
in a web really wants to be in two different classes to satisfy
constraints in two different insns. Right now, as far as I
understand, regclass just picks one and lets reload figure out how to
fix up that mistake.
- A semi-strict RTL mode. Right now there is just strict and
non-strict. On the branch there is a semi-strict mode which is the
same as strict RTL except that pseudo-registers are still allowed.
- pre-reload (which is related to web class) to make sure as many insn
constraints as possible are satisfied before the register allocator
goes to work. Basically, after pre-reload the insns stream should be
in semi-strict RTL form.
I used the webizer to unify defs and uses. I would split a web if it
needed multiple register classes (I inserted a mov, without checking
that a move existed from the source to the target register class), and
I put pseudos r1 and r2 in the same register class if there was an
insn (set (r1) (r2)) somewhere. The selection of the register classes
had a cost function, but I used rtx_cost, which is not very effective,
really. But I never took this experiment very far because for x86-64
the plan didn't work as well as I had hoped. I don't remember the
details, but the biggest problem I had with the experimental
implementation of these ideas (apart from lots of trouble with recog
for semi-strict RTL) was that there is a bit of an ordering problem
between combine on the one hand, and web-based register classes. If
you assign classes too early and don't allow things to change, then
combine fails too often. If you assign register classes after combine,
you may not get the instructions selected the way you want them to be.
This was when GCC still had the old local-alloc.c and global.c
allocators. Things may be different (better) with IRA and the upcoming
LRA stuff.
If you plan to work on this, I would suggest you discuss the plan on
the GCC mailing list also, with Jeff Law and Vladimir Makarov in CC
because they are working on a reload rewrite (LRA).
Ciao!
Steven
