- linaro-toolchain - lists.linaro.org

Linaro GCC 4.4 and 4.5 2011.02 released

by Michael Hope

The Linaro Toolchain Working Group is pleased to announce the release of both Linaro GCC 4.4 and Linaro GCC 4.5. Linaro GCC 4.5 is the seventh release in the 4.5 series. Based off the latest GCC 4.5.2, it includes many ARM-focused performance improvements and bug fixes. Interesting changes include: * Improved code generation in the __sync primitives * Better modelling of the Cortex-A9 NEON pipeline * Added a performance improvement that converts a tree of ifs into a switchs * Many bug fixes Linaro GCC 4.4 is the seventh release in the 4.4 series. Based off the latest GCC 4.4.5, it is a maintenance release that fixes one fault found with offsets on NEON loads. The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.5-2011.02-0 https://launchpad.net/gcc-linaro/+milestone/4.4-2011.02-0 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro -- Michael

14 years, 3 months

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Linaro QEMU 2011.02-0 released

by Peter Maydell

The Linaro Toolchain Working Group is pleased to announce the release of Linaro QEMU 2011.02-0. Linaro QEMU 2011.02-0 is the first official release of qemu-linaro. Based off upstream qemu, it includes a number of ARM-focused bug fixes and enhancements. - This initial qemu-linaro release includes all the ARM code generation fixes from the qemu-meego tree; these are mainly Neon related - The OMAP3 support from qemu-meego is also included - Various bugs which prevented newer Linaro snapshots from booting on the beagle model have been fixed - Bugs causing linaro-media-create to print warnings about unimplemented syscalls and ioctls have been fixed Known issues: - There is no support for USB keyboard or mouse, so only a serial console is usable (#708703) - Images built with linaro-media-create's --swap_file option will not boot (#713101) The source tarball is available at: https://launchpad.net/qemu-linaro/+milestone/2011.02 Binary builds of this qemu-linaro release are available for users of Ubuntu. Natty users can find qemu-linaro 2011.02-0 in the Ubuntu archive. Users of Ubuntu 10.04 LTS and Ubuntu 10.10 can find packages in the linaro-maintainers tools ppa: https://launchpad.net/~linaro-maintainers/+archive/tools/ More information on Linaro QEMU is available at: https://launchpad.net/qemu-linaro

14 years, 3 months

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[ACTIVITY] 31st January - 4th February

by Andrew Stubbs

== Linaro GCC 4.5 == Reviewed, tested and merged all the outstanding patches waiting to go into Linaro GCC 4.5. Michael reported that there was a build failure on i686 and amd64. I attempted to reproduce this but my builds completed successfully - very strange. Eventually I found that I had a corrupted checkout and managed to reproduce the problem - thanks bzr! The problem is in Tom's recent changes to stmt.c, so I informed him and backed out the patches, temporarily. Spun the Linaro GCC 4.4 and 4.5 release tarballs and passed them to Michael Hope for final testing. == GCC 4.6 == Tested a more recent version of GCC 4.6 and pushed it to the bazaar repository. Already out of date by the time testing finished of course, but never mind. The number of test failures is greatly reduced. Started another build/test with an even more up-to-date check-out. Begun work merging the 4.5 patches into 4.6. Pushed 1 patch upstream. Got another ready to go, once I've tested it. == Android == Tried to unpick a large patch I was sent that supposedly added Android support to Linaro GCC 4.5. The patch was suspicious from the start because it had large changes to gcc/ChangeLog that clearly backed out the 4.5.2 release. After comparing it against various sources I concluded that it was a 4.6 snapshot from last May with (at least some of) the Linaro patches forward ported, and the release numbers fudged to look like it was 4.5.2 based. This was not terribly helpful - I can't very well backport that into our 4.5 branch! == Upstream GCC == Upstream patches requiring review: * Thumb2 constants: http://gcc.gnu.org/ml/gcc-patches/2010-12/msg00652.html * Kazu's VFP testcases: http://gcc.gnu.org/ml/gcc-patches/2011-02/msg00128.html

14 years, 3 months

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[ACTIVITY] Weekly status

by Richard Sandiford

== Last week == * Backported the fixes for lp693502, lp710623 and lp710652 to linaro 4.6 and linaro 4.5. Tested and sent merge requests. * Wrote several more ifunc tests, and fixed the bugs they showed up. Found that ARM generates unnecessary dynamic relocs against GOT entries, so fixed that as a prerequisite. Improved the tracking of STB_LOCAL ifuncs, so that they're treated more like STB_GLOBAL. * Submitted a request for R_ARM_IRELATIVE to be added to the ARM EABI. == This week == * More ifunc. I'm away next week (14th-18th) Richard

14 years, 3 months

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Extension elimination pass breaks SPU (Fw: spu gcc-4.5 linaro build failure)

by Ulrich Weigand

Hello, Matthias noticed the following ICE when attempting to build the SPU compiler from the Linaro GCC 4.5 sources: ../../../../src-spu/libgcc/../gcc/libgcc2.c: In function '__fixunssfdi': ../../../../src-spu/libgcc/../gcc/libgcc2.c:1344:1: internal compiler error: in spu_expand_mov, at config/spu/spu.c:4575 It turns out that this is due to the new "extension elimination" pass that was recently added in Linaro GCC, as port from the CodeSourcery compiler. This patch has also been proposed, but not yet included upstream. The problem is that this patch seems to frequently introduce instructions that *set* a sub-word lowpart subreg of a register. Now such instructions, according to the docs, are probably valid RTL, but since the effect of the instruction onto the highpart of the register is deliberately left unspecified, they tend to be very infrequently used. Probably because of this, there seem to be parts of the compiler that simply don't handle such instructions correctly. This has been already noticed in the case of the RTL loop optimizers (see discussion here http://gcc.gnu.org/ml/gcc/2010-11/msg00552.html). The failure in the SPU back-end is another instance of the same problem. SPU needs special code to handle subregs (since a "lowpart" SImode subreg of a DImode register is not actually valid on the SPU, because SImode values live in bytes 0..3 while DImode values live in bytes 0..7 of the otherwise big-endian 16-byte SPU registers), and this code simply aborts when given an assignment to a sub-word lowpart subreg. Now, I guess there's two ways forward: either the outcome of the ongoing discussions on gcc-patches is that it is in fact not a good idea to generate such sets, and the EE pass is subsequently rewritten to avoid them; or else, if those instructions are considered valid, I'll have to extend the SPU move expander to handle them. Thoughts? Matthias, if you need a quick workaround for now, I guess you could disable the new pass for SPU by adding a line "flag_ee = 0;" to spu_override_options. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 3 months

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qemu 2011.02-rc2 test results

by Michael Hope

I've had a go with running the QEMU release candidate. Short story is that it boots to a prompt against the 11.05 alpha2 release so I'm happy. It was a messy road so I've written up my train of though here: https://wiki.linaro.org/MichaelHope/Sandbox/QEMU Note that if you follow the instructions on: https://wiki.linaro.org/Releases/GettingInstallingTesting and turn on a swap file then it halts during boot. -- Michael

14 years, 3 months

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[ACTIVITY] 2011-02-04

by David Gilbert

== String routines == * After some discussions about IT semantics managed to shave a couple of instructions out of a couple of routines * Got around to trying a suggestion that was made some months ago, that LDM is faster than LDRD on A9's; and indeed it does seem to be in some cases; those cases seem pretty hard to define though - it's no slower than LDRD, so it seems best to avoid LDRD. * Digging around eglibc's build/configure system to see how to add assembler routines to only get used on certain build conditions (i.e. v7 & up) == SPEC == * Compiled lbm -O2 and ran it on our local panda and on Michael's ursa1 - it seems happy (with a drop of swap); so I'd say that confirms the issues I previously had were local to something on canis. That's a bit of a pain since it's the only machine with enough RAM to run the rest of the suite. == Other == * Tested a headless Alpha-2 install on our Beagle C4 - mostly worked * Tested qemu-linaro release on the realview-pbx kernel/nfs setup I had * A simple smoke test for pldw on qemu * Tripped over ltrace not working while trying to profile git's use of memcpy and memcmp; it does some _very_ odd things; it's predominant size of memcpy seems to be 1 byte.

14 years, 3 months

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OpenOCD support for OMAP4/ PandaBoard

by Nicolas Pitre

I just stumbled across this: http://article.gmane.org/gmane.comp.debugging.openocd.devel/15584 And the mentioned clock issue seems to be fixed here: http://article.gmane.org/gmane.comp.debugging.openocd.devel/15619 This is excellent news, and I think we ought to support this at some point. Nicolas

14 years, 3 months

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[ACTIVITY] Jan 31 - Feb 04

by Ulrich Weigand

== GDB == * Prepared Linaro GDB 7.2-2011-02.0 release * Committed two patches to implement LP #661253 (Improve backtrace by using ARM exception tables) to mainline and Linaro GDB 7.2 * Provided two follow-on fixes to the patch for LP #616000 (Handle -fstack-protector prologue code); both applied to mainline and Linaro GDB 7.2 * Backported mainline fix for LP #685494 (gdb.xml/tdesc-regs.exp failure) to Linaro GDB 7.2 * Identified root cause of LP #711375 (gdb internal error in inline_frame_this_id trying to debug a qemu target); committed fix to mainline and Linaro GDB 7.2 * Worked on re-implementation of fix for LP #615978 (Failure to software single-step into signal handler) Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294

14 years, 3 months

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[ACTIVITY] Week 2011-2-04

by Mounir Bsaibes

=== Toolchain === * Organized the Weekly Release Meeting Status pages https://wiki.linaro.org/WorkingGroups/ToolChain/Status * Organized the collection of weekly Activity https://wiki.linaro.org/WorkingGroups/KernelConsolidation/ActivityReports * Started to track Linaro events planned and approved attendance https://wiki.linaro.org/Internal/People/MounirBsaibes/ToolchainScratchpad(f… now) * Started to monitor bug handling * Reviewed and tracked blueprints status (burdown charts) * Kernel WG various PM tasks * Power Management WG various PM tasks ==== Plan ==== * Continue investigating importing blueprint and WI's data into OpenProj using OpenProj xml file * map bleuprint/WI's fields to the OpenProj xml fields

14 years, 3 months

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[ACTIVITY] report week 05

by Peter Maydell

RAG: Red: Amber: DATE/QEMU conference still hasn't confirmed I have a place... Green: qemu-linaro RC2 prerelease uploaded Current Milestones: | Planned | Estimate | Actual | first qemu-linaro release | 2011-02-08 | 2011-02-08 | | Historical Milestones: finish virtio-system | 2010-08-27 | postponed | | finish testing PCI patches | 2010-10-01 | 2010-10-22 | 2010-10-18 | successful ARM qemu pull req | 2010-12-16 | 2010-12-16 | 2010-12-16 | finish qemu-cont-integration | 2010-01-25 | 2010-01-25 | handed off | * maintain-beagle-models: + RC1 packaging flushed out some bugs: ++ we include some binary blobs which we're better not distributing: https://bugs.launchpad.net/qemu-linaro/+bug/709965 ++ a couple of array overruns don't compile with our picky armel gcc: https://bugs.launchpad.net/qemu-linaro/+bug/709711 https://bugs.launchpad.net/qemu-linaro/+bug/711272 (both fixes sent and applied upstream) ++ we ought to include a fix for the "swp" in qemu-lock.h: http://patchwork.ozlabs.org/patch/81205/ (patch sent upstream, no comment on it yet) + ...so I have rolled an RC2 tarball with these fixed + investigated why USB keyboard model doesn't work: it turns out that the OMAP host USB model is basically just a stub + some warnings from qemu about bad width accesses are a symptom of a nasty disagreement between gcc and the kernel about getting atomic 32 bit accesses: http://www.spinics.net/lists/arm-kernel/msg113002.html + warnings from qemu about access to a nonexistent i2c register appear to be a kernel bug in the i2c driver for OMAP36xx: https://bugs.edge.launchpad.net/linux-linaro/+bug/645324 + investigated a hang running images built with linaro-media-create's --swap_file option. Still digging but I suspect the Linux driver doesn't cope with an MMC card which can erase in zero time... * merge-correctness-fixes + the usual upstream mailing list monitoring and code review + sent patch for PLI and hint space decoding fixes: http://patchwork.ozlabs.org/patch/81711/ * misc + some non-Linaro time this week; may be more next week + some advance planning of what we might want to do with QEMU in the future Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences: 17/18 March: QEMU Users Forum, Grenoble Holiday: 22 Apr - 2 May 9-13 May: UDS, Budapest (maybe) ~17-19 August: QEMU/KVM strand at LinuxCon NA, Vancouver

14 years, 3 months

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[ACTIVITY] weekly status

by Ken Werner

Hi, * I continued to setup the pandaboad but ran into #708883 - tested vaious various hwpacks and headless images - used different power supplies and several SD cards - built various test kernels from the linux-linaro-natty.git * looked into the crash utility * https://wiki.linaro.org/KenWerner/Sandbox/crash-utility#future%20areas Regards Ken

14 years, 3 months

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gcc-linaro-4.5+bzr99469 build failure

by Michael Hope

The current revision fails to bootstrap on i686: http://ex.seabright.co.nz/build/gcc-linaro-4.5+bzr99469/logs/i686-lucid-cbu… libtool: compile: /scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/build/./gcc/xgcc -shared-libgcc -B/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/build/./gcc -nostdinc++ -L/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/build/i686-pc-linux-gnu/libstdc++-v3/src -L/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/build/i686-pc-linux-gnu/libstdc++-v3/src/.libs -B/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/i686-pc-linux-gnu/bin/ -B/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/i686-pc-linux-gnu/lib/ -isystem /scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/i686-pc-linux-gnu/include -isystem /scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/i686-pc-linux-gnu/sys-include -DHAVE_CONFIG_H -I. -I../../../gcc-linaro-4.5/libjava -I./include -I./gcj -I../../../gcc-linaro-4.5/libjava -Iinclude -I../../../gcc-linaro-4.5/libjava/include -I../../../gcc-linaro-4.5/libjava/classpath/include -Iclasspath/include -I../../../gcc-linaro-4.5/libjava/classpath/native/fdlibm -I../../../gcc-linaro-4.5/libjava/../boehm-gc/include -I../boehm-gc/include -I../../../gcc-linaro-4.5/libjava/libltdl -I../../../gcc-linaro-4.5/libjava/libltdl -I../../../gcc-linaro-4.5/libjava/.././libjava/../gcc -I../../../gcc-linaro-4.5/libjava/../zlib -I../../../gcc-linaro-4.5/libjava/../libffi/include -I../libffi/include -fno-rtti -fnon-call-exceptions -fdollars-in-identifiers -Wswitch-enum -D_FILE_OFFSET_BITS=64 -ffloat-store -fomit-frame-pointer -Usun -Wextra -Wall -D_GNU_SOURCE -DPREFIX=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install\" -DTOOLEXECLIBDIR=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/lib\" -DJAVA_HOME=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install\" -DBOOT_CLASS_PATH=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/share/java/libgcj-4.5.2.jar\" -DJAVA_EXT_DIRS=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/share/java/ext\" -DGCJ_ENDORSED_DIRS=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/share/java/gcj-endorsed\" -DGCJ_VERSIONED_LIBDIR=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/lib/gcj-4.5.2-11\" -DPATH_SEPARATOR=\":\" -DECJ_JAR_FILE=\"\" -DLIBGCJ_DEFAULT_DATABASE=\"/scratch/cbuild/slave/slaves/scorpius/gcc-linaro-4.5+bzr99469/install/lib/gcj-4.5.2-11/classmap.db\" -DLIBGCJ_DEFAULT_DATABASE_PATH_TAIL=\"gcj-4.5.2-11/classmap.db\" -g -O2 -D_GNU_SOURCE -MT exception.lo -MD -MP -MF .deps/exception.Tpo -c ../../../gcc-linaro-4.5/libjava/exception.cc -o exception.o >/dev/null 2>&1 ../../../gcc-linaro-4.5/libjava/prims.cc: In function 'jboolean _Jv_isPrimitiveOrDerived(const Utf8Const*)': ../../../gcc-linaro-4.5/libjava/prims.cc:287:5: internal compiler error: in set_jump_prob, at stmt.c:2211 Please submit a full bug report, with preprocessed source if appropriate. See <http://gcc.gnu.org/bugs.html> for instructions. The log is available here: http://builds.linaro.org/toolchain/gcc-linaro-4.5+bzr99469/logs/i686-lucid-… -- Michael

14 years, 3 months

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do we consider extravagant memory usage a gcc bug?

by Peter Maydell

Trying to build qemu on a beagle board: CC sparc64-linux-user/translate.o cc1: out of memory allocating 26975704 bytes after a total of 70742016 bytes # ls -lh target-sparc/translate.c -rw-r--r-- 1 root root 191K Jan 31 12:05 target-sparc/translate.c ie gcc wants (at least) 100M of RAM trying to compile a 190K sourcefile. (and probably more overall since the board has 500MB RAM total and it hit the out-of-memory condition). This seems a bit excessive to me, but do we consider it enough of a bug to be worth looking into? (I believe this source file has caused compile failures on the buildds too, which have rather more RAM/swap than my beagle.) -- PMM

14 years, 3 months

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[ACTIVITY] January 30 - February 3

by Revital1 Eres

Hello, Profiling Denbech: * The profiling information on x86 indicate that some benchmarks might need to run longer as helper functions such as t_run_test are reported to be hot. So I've increased the time each benchmark is executed and will continue to experiment with that for the problematic benchmarks until I start to see more reasonable results. * Opened PR711819 after having an ICE running DENbench with trunk (natively built on ARM machine). - I've started to look at an old patch for SMS that was written in 2005 by colleague; Mostafa Hagog; to place the register moves in free slots. Currently, they are placed greedily before each def thats needs them. Thanks, Revital

14 years, 3 months

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[ACTIVITY] January 30 - February 3

by Ira Rosen

Hi, I continued to work on vect_interleave and vect_extract implementation on NEON: * debugged the compiler to find out what's the problem with neon_vzip/vuzp<mode>_internal * fixed it following Uli's advice * checked how neon_vzip/vuzp<mode>_internal work for intrinsics by writing tests * fixed the patch according to Uli's comments * now fully testing the patch Thanks, Ira

14 years, 3 months

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Help with define_insn

by Ira Rosen

Hi, I am trying to implement interleave_high/low and extract_even/odd using vzip and vuzp instructions. I am attaching a patch that attempts to do that. It uses already existing neon_vzip<mode>_internal. The problem with it is that it doesn't express the fact that the two outputs of vzip depend on both inputs, which causes wrong code generation in CSE: for (a,b)<- vzip (c,d) and (e,f) <- vzip (g,d) CSE decides that b==f, since on RTL level b and f depend only on d. Here is neon_vzip<mode>_internal: (define_insn "neon_vzip<mode>_internal" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] UNSPEC_VZIP1)) (set (match_operand:VDQW 2 "s_register_operand" "=w") (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] UNSPEC_VZIP2))] "TARGET_NEON" "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2" [(set (attr "neon_type") (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) (const_string "neon_bp_simple") (const_string "neon_bp_3cycle")))] ) Is there a way to properly mark the dependence? Thanks, Ira

14 years, 3 months

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qemu-linaro prerelease available

by Peter Maydell

Hi; this is a note to say that we have now produced a prerelease tarball of qemu-linaro. (The first formal qemu-linaro release will happen in sync with other toolchain group releases on 8th Feb.) This prerelease is primarily to pipeclean the release process and to allow work to start on producing Ubuntu and Linaro packages; however it does include a number of useful bugfixes which are required if you want to be able to boot a recent Linaro snapshot on the beagle model. So the enthusiastic might like to build it from source and give it a spin. Like the Linaro kernel trees, the qemu-linaro tree aims to only include patches we are confident will go upstream; at the moment this means the OMAP3 support and ARM correctness fixes from the qemu-meego tree, based on the qemu upstream trunk. You can download the source tarball from: https://launchpad.net/qemu-linaro/+milestone/2011.02 -- Peter Maydell

14 years, 3 months

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IT block semantic question

by David Gilbert

Hi, What do people understand to be the expected semantics of IT blocks in the cases below, of which there has been some confusion in relation to a recent Qt issue. The code in question had a sequence something like: comparison IT... EQ blahEQ TEQ BEQ The important bits here are that we have an IT EQ block and two special cases: 1) There is a TEQ in the IT block - are all comparisons in the block allowed and do their effects immediately take effect? As far as I can tell this is allowed and any flag changes are used straight away; 2) There is a BEQ at the end of the IT block, as far as I can tell, as long as the destination of the BEQ is close it shouldn't make any difference if the BEQ is included in the IT block or not. Does that match everyone elses understanding? Dave

14 years, 3 months

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Generating ancilliary sections with gas

by Dave Martin

Hi all, With gas, does anyone know of a way to create a section whose name is based on that of the current section? The specific requirement is to be able to define a generic macro like the example "fixup" below, whose purpose is to record ancilliary data related to some other section. To illustrate: .macro fixup 100\@ : .pushsection fixup<current section name>, "a" .long 100\@b .popsection .endm .text ... fixup .long sym1 ... .section .other, "ax" ... fixup .long sym2 The linux kernel uses a technique just like this for patching SMP kernels at bootup to work on uniprocessor platforms (when CONFIG_SMP_ON_UP is enabled), resulting in code looking something like this: void exit __attribute__ (( __section__ (".text.exit") )) { ... asm( ... FIXUP("something") ... ); } Note that the inline asm may actually come out of a generic header file rather than being explitly written for this invocation. So it may have to be truly generic. Is far as I have been able to determine, it's not possible to generate sections named based on the current section. In practice, the kernel puts all the fixups into a single section. The downside of this is that when sections are selectively discarded at link time (which in general may happen -- for example, Linux discards the "module exit" code for drivers which are built into the kernel and therefore never exit) there is no way to selectively discard the related fixup entries. Currently the only solution is to include all the module exit code in the image and discard it at run-time when the kernel boots. This is obviously wasteful. Attempting to discard that code at like time results in a link error, since fixups refer to the removed sections. Of course, the "fixup" macro could be given an extra parameter to name the containing section, but the macro can then no longer be called in a generic way: all the calls to that macro must be manually (and buggily) maintained to ensure that the referenced section name is correct, some object post-processing must be done before linking, and/or a tool must be created to implement the missing assembler functionality. Unfortunately, such solutions are likely to be too fragile or complex to make it upstream. It's interesting to note that the same problem will apply for any section containing ancilliary data for another section. In particular, it looks like either the ABI or the assembler has had to grow a special-case workaround for this in order to support exception unwind information sections generated by .fnstart ... .fnend in a sane way: the unwind information sections get called .ARM.ex{idx,tab} for .text, and .ARM.ex{idx,tab}<section> for any other section. As a consequence, link-time discarding can handle this information properly, but IMHO this is a bit of a cheat and admits the general need to create sections with names based transparently on those of other sections, without satisfying that need. .popsection is also an example of such a cheat: most other aspects of assmbler state still cannot be saved and restored. In general, it would be useful if gas supported some general reflective abilities: i.e., the ability to query the current assembler state (section, subsection, active instruction set, active macro mode, etc.) and/or the ability to wrap or hook existing pseudo-ops. For example, the above problem would almost certainly solvable using assembler macros (albeit painfully) if wrapper macros could be defined for the section manipulation directives (section, .text, .data, .bss, .pushsection, .popsection, .previous). However, supporting some magic macro parameters reflecting the assembler state would be a lot simpler. As an example of the kind of behaviour I think would be useful, the macro argument qualifier could be extended to allow macros to query the assembler state in a backwards-compatible way; something like: .macro fixup base_section:gas_current_section_name, old_altmacro:gas_macro_mode .altmacro LOCAL fixup_location fixup_location: .pushsection \base_section\().fixup .long 100\@b .popsection \old_altmacro .endm Existing assembler code will continue to work just fine with this approach. Note how this also enables a local label to be generated hygenically, by making it possible to save and restore the macro mode. Otherwise, .altmacro (and hence LOCAL) is hard to use safely, since the initial macro mode is unknown and can't be restored. Any thoughts / comments? Cheers. ---Dave

14 years, 3 months

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[GCC 5.5 - Help on ERROR] Compilation fails with mfpu=neon

by ShankarGanesh Kandasamy

Hi, Following compilation fails with -O3 -mfpu=neon,(but successful on -O2, -mfpu=neon) for Cortex-A5. Could you please help me out to resolve this error ? ubuntu@tegra:~/$ gcc-4.5 -v -c -o utility.o -DLINUX -DUNIX -DHAS_LONGLONG -DLITTLE_ENDIAN_ARCH -DSPEC_CPU2000 -O3 -mcpu=cortex-a5 -marm -mfpu=neon -mfloat-abi=softfp utility.c Using built-in specs. COLLECT_GCC=gcc-4.5 COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabi/4.5.1/lto-wrapper Target: arm-linux-gnueabi Configured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 4.5.1-7ubuntu2' --with-bugurl=file:///usr/share/doc/gcc-4.5/README.Bugs --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.5 --enable-shared --enable-multiarch --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.5 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-plugin --enable-objc-gc --disable-sjlj-exceptions --with-arch=armv7-a --with-float=softfp --with-fpu=vfpv3-d16 --with-mode=thumb --disable-werror --enable-checking=release --build=arm-linux-gnueabi --host=arm-linux-gnueabi --target=arm-linux-gnueabi Thread model: posix gcc version 4.5.1 (Ubuntu/Linaro 4.5.1-7ubuntu2) COLLECT_GCC_OPTIONS='-v' '-c' '-o' 'utility.o' '-DLINUX' '-DUNIX' '-DHAS_LONGLONG' '-DLITTLE_ENDIAN_ARCH' '-DSPEC_CPU2000' '-O3' '-mcpu=cortex-a5' '-marm' '-mfpu=neon' '-mfloat-abi=softfp' /usr/lib/gcc/arm-linux-gnueabi/4.5.1/cc1 -quiet -v -DLINUX -DUNIX -DHAS_LONGLONG -DLITTLE_ENDIAN_ARCH -DSPEC_CPU2000 utility.c -D_FORTIFY_SOURCE=2 -quiet -dumpbase utility.c -mcpu=cortex-a5 -marm -mfpu=neon -mfloat-abi=softfp -auxbase-strip utility.o -O3 -version -fstack-protector -o /tmp/ccaZnpsw.s GNU C (Ubuntu/Linaro 4.5.1-7ubuntu2) version 4.5.1 (arm-linux-gnueabi) compiled by GNU C version 4.5.1, GMP version 4.3.2, MPFR version 3.0.0-p3, MPC version 0.8.2 GGC heuristics: --param ggc-min-expand=64 --param ggc-min-heapsize=64482 ignoring nonexistent directory "/usr/local/include/arm-linux-gnueabi" ignoring nonexistent directory "/usr/lib/gcc/arm-linux-gnueabi/4.5.1/../../../../arm-linux-gnueabi/include" ignoring nonexistent directory "/usr/include/arm-linux-gnueabi" #include "..." search starts here: #include <...> search starts here: /usr/local/include /usr/lib/gcc/arm-linux-gnueabi/4.5.1/include /usr/lib/gcc/arm-linux-gnueabi/4.5.1/include-fixed /usr/include End of search list. GNU C (Ubuntu/Linaro 4.5.1-7ubuntu2) version 4.5.1 (arm-linux-gnueabi) compiled by GNU C version 4.5.1, GMP version 4.3.2, MPFR version 3.0.0-p3, MPC version 0.8.2 GGC heuristics: --param ggc-min-expand=64 --param ggc-min-heapsize=64482 Compiler executable checksum: 52c4962735600b49ca41dc70631edd04 COLLECT_GCC_OPTIONS='-v' '-c' '-o' 'utility.o' '-DLINUX' '-DUNIX' '-DHAS_LONGLONG' '-DLITTLE_ENDIAN_ARCH' '-DSPEC_CPU2000' '-O3' '-mcpu=cortex-a5' '-marm' '-mfpu=neon' '-mfloat-abi=softfp' as -mcpu=cortex-a5 -mfloat-abi=softfp -mfpu=neon -meabi=5 -o utility.o /tmp/ccaZnpsw.s /tmp/ccaZnpsw.s: Assembler messages: /tmp/ccaZnpsw.s:460: Error: VFP/Neon double precision register expected -- `vmovl.s16 q5,s20' /tmp/ccaZnpsw.s:531: Error: VFP/Neon double precision register expected -- `vmovl.s16 q9,s14' /tmp/ccaZnpsw.s:537: Error: VFP/Neon double precision register expected -- `vmovl.s16 q7,s28' /tmp/ccaZnpsw.s:542: Error: VFP/Neon double precision register expected -- `vmovl.s16 q13,s12' /tmp/ccaZnpsw.s:543: Error: VFP/Neon double precision register expected -- `vmovl.s16 q14,s10' /tmp/ccaZnpsw.s:544: Error: VFP/Neon double precision register expected -- `vmovl.s16 q3,s8' /tmp/ccaZnpsw.s:546: Error: VFP/Neon double precision register expected -- `vmovl.s16 q2,s6' /tmp/ccaZnpsw.s:549: Error: VFP/Neon double precision register expected -- `vmovl.s16 q1,s4' /tmp/ccaZnpsw.s:550: Error: VFP/Neon double precision register expected -- `vmovl.s16 q0,s0' /tmp/ccaZnpsw.s:551: Error: VFP/Neon double precision register expected -- `vmovl.s16 q4,s16' Regards, Shankar -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

14 years, 3 months

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[ACTIVITY] Jan 24--30

by Chung-Lin Tang

== Last week == * PR47246, VFP index range on Thumb-2. Submitted and committed patch upstream. * Pinged two upstream submissions on gcc-patches, one for PR44557 and the other a patch for LP:689887; still awaiting approval. == This week == * Chinese New Year Holiday, I'll be off until Feb.8th.

14 years, 3 months

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GCC 4.6 Upgrade Plan

by Andrew Stubbs

Hi All, The GCC 4.6 Upgrade plan can be found here: https://wiki.linaro.org/WorkingGroups/ToolChain/GCCUpgradePlan The plan describes how we should commit "upstream" patches while the FSF trunk is closed, and what we plan to use 4.6 for. Andrew

14 years, 3 months

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[ACTIVITY] 24th -28th January 2011

by Andrew Stubbs

Created a Google docs spreadsheet to help visualise the benchmark results. The graphs are not very informative yet - too many lines and too much noise. I'm going to have to revisit them. Continued trying to build Android. The toolchains build fine, but Android itself complains about -Werror, and there are a few other real errors too. Considering I was told it built fine with GCC 4.6 and all I needed to do was tweak 4.5 to match, I'm not terribly impressed. I'm sinking too much time into fixing up Android, and I haven't even got to looking at the compiler trouble. Alexander Sack has said he will try to get me to a more appropriate starting place (I think), so I'll see what happens there. Discussed my maddhidi4 patch with Richard E (wearing his GCC ARM maintainer hat). He's not convinced that my change won't make something else produce worse code. I can't prove that it won't either, so I'm going to have to revisit it. Wrote up the GCC 4.6 branch policy and upgrade plan.

14 years, 3 months

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New phone number for today's call

by Michael Hope

Just a reminder that the dial-in numbers for today's and all future calls has changed. See: https://wiki.linaro.org/WorkingGroups/ToolChain/Meetings for the new list. I'll hang out on IRC just before the meeting to help the lost... -- Michael

14 years, 3 months

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