Hi Will,
- It seems odd that the kernel says it doesn't support the debug
architecture, but then reports to user space that 1 watchpoint and 6 breakpoints are supported ... GDB will never use the watchpoint,
because
the maximum watchpoint size is reported as zero, but GDB will attempt
to
use the breakpoints. Setting a breakpoint will appear to succeed, but
then
the breakpoint just never triggers. The kernel should IMO be more consistent in how unsupported configurations are handled ...
Agreed. This is an artifact of how the ptrace info register is populated. I'll work on a fix tomorrow so that we don't report any resources when the architecture is unsupported.
Great, thanks!
- Why is architecture 0x4 not supported? This seems to be the variant
of
the v7 debug architecture with memory-mapped registers. Apparently the IGEP only supports this version ... Do you know what the Beagle-/Pandaboard and other clones do? What would it take to support
this
architecture variant? Given the widespread use of those boards, it
would
be really nice if we could support hardware debugging on them ...
The memory-mapped interface is hugely unreliable in real hardware because you have to calculate the address of the memory-mapped debug registers by using a base and offset, which are hardcoded in some information
registers.
Unfortunately, I've never found a board where these registers have been programmed correctly so (a) I had nothing to test my code with (b) few
people
would be able to use it and (c) there's not really a safe way to go
around
poking random areas of memory.
Huh, I see. I have no idea whether those information registers contain correct values on IGEP ..
- Which hardware *is* supported? Can you recommend a board I should be
using to verify GDB support is working?
The simple rule is Cortex-A8 is unsupported and Cortex-A9 is supported. The A5 should work (untested) and the A15 will need a bit of hacking to get it supported.
OK. I guess I can try on our Versatile Express.
Thanks for your help in getting this working!
No problem. If you find anybody with working memory-mapped debug and some spare time, I'd be happy to review patches :)
Thanks! I'll try and see if I can figure out where the MM area is on the IGEP ...
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
-- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294
On Fri, Feb 11, 2011 at 4:23 AM, Ulrich Weigand Ulrich.Weigand@de.ibm.com wrote:
The simple rule is Cortex-A8 is unsupported and Cortex-A9 is supported. The A5 should work (untested) and the A15 will need a bit of hacking to get it supported.
OK. I guess I can try on our Versatile Express.
The PandaBoards ursa1 and ursa2 are available as well. You'll need to figure out how to get a good kernel though - I ended up going with the Ubuntu 2.6.35 kernel[1] after getting stuck.
And, having said that on a public mailing list, I must be asking for it :)
-- Michael [1] http://bazaar.launchpad.net/~michaelh1/+junk/hardware/view/head:/ursa/README...
On Fri, Feb 11, 2011 at 4:23 AM, Ulrich Weigand Ulrich.Weigand@de.ibm.com wrote:
The simple rule is Cortex-A8 is unsupported and Cortex-A9 is supported. The A5 should work (untested) and the A15 will need a bit of hacking to get it supported.
OK. I guess I can try on our Versatile Express.
The PandaBoards ursa1 and ursa2 are available as well. You'll need to figure out how to get a good kernel though - I ended up going with the Ubuntu 2.6.35 kernel[1] after getting stuck.
I don't have a pandaboard, so I'd be interested to see if the code works there. I developed it using ARM boards, so the versatile express is a known good target.
Will
linaro-toolchain@lists.linaro.org
-
Michael Hope -
Ulrich Weigand -
Will Deacon