Hi All,
As i have frequently said, we are using 2011.3 4.5 linaro gcc. For the
following codes, if we compile it by -O2, it will crash with "segment
fault", if we just comment " if(unifi_debug >= level) {", all will be
ok.
If we don't compile it by -O2, all will be ok too.
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#define DEBUG_BUFFER_SIZE 80
int unifi_debug = 5;
void
unifi_trace(void* ospriv, int level, const char *fmt, ...)
{
static char s[DEBUG_BUFFER_SIZE];
va_list args;
unsigned int len;
if(unifi_debug >= level) {
va_start(args, fmt);
len = vsnprintf(&(s)[0],
(DEBUG_BUFFER_SIZE),
fmt, args);
va_end(args);
if (len >= DEBUG_BUFFER_SIZE) {
(s)[DEBUG_BUFFER_SIZE - 2] = '\n';
(s)[DEBUG_BUFFER_SIZE - 1] = 0;
}
printf("%s", s);
}
}
int main(void)
{
char *prog = "/usr/sbin/unififw";
unifi_trace(NULL, 1, "start %s\n", prog);
return 0;
}
Thanks
Barry
Hi there. A first-pass list of summit sessions is up at:
https://wiki.linaro.org/MichaelHope/Sandbox/1111Blueprints
The next step is to investigate these areas and come up with a basic
plan that can be discussed during the summit.
I've put your names against the sessions as follows:
Andrew: Broad tuning
Dave: String routines everywhere
Dave: QEMU topic #2
Doug: STM support
Ira: Vectoriser and NEON performance
Ken: 64 bit sync primitives
Ken: Good backtracing
Ken: End-developer tools bluesky
Michael: Publish benchmarking of the toolchain
Michael: Binary builds
Michael: Deeper validation
Peter: QEMU bluesky
Ramana: Thumb-2 performance brainstorm
Ramana: GCC backend rework
Ulrich: GDB as a cross-debugger
Ira and Dave, I know you won't be at the summit but we'll see about
being able to call in.
Could you all please have a read of the outline, investigate these
topics, and draft up a blueprint-style list of work items to achieve
it? Record any notes in the sandbox page[5] or in a child page if
needed. Larger topics may warrant a specification[1].
I'd like these done by the end of next week. I'd expect to spend up
to a day on the topics you already understand and more on broad
topics.
For reference, the see the draft TRs[2] and spreadsheet [3]. I've
added some GDB topics to the spreadsheet that still need to go onto
the wiki page.
The outlines should touch each of these TRs in some way so let me know
if I've missed anything.
There's more good information on the process and style at:
https://wiki.linaro.org/Process/Blueprintshttps://wiki.linaro.org/Process/WorkItemsHowtohttps://wiki.linaro.org/Resources/FAQ
Questions? Need more detail? Let me know.
-- Michael
[1] https://wiki.linaro.org/Process/SpecTemplate
[2] https://wiki.linaro.org/Cycles/1111/TechnicalTopics/Toolchain
[3] https://spreadsheets.google.com/ccc?key=0Ap7fWLePADFVdHkxYy1INTZmMEd4bkwxSG…
[4] there is no 4...
[5] https://wiki.linaro.org/MichaelHope/Sandbox/1111Blueprints
Hi,
Agenda for today's performance call . Sorry about the last minute
posting and I'll put this in the wiki soon enough.
1. Sync-up on what's been happening around the group:
a. Coremark regressions.
b. Thumb2 constants patch.
c. divmodsi4 and vfp register moves.
d. DENBench investigations.
2. Planning for the summit and turning some of the ideas into blueprints.
3. AOB.
cheers
Ramana
== Last week ==
* PR48250, rehaul arm_legitimize_reload_address(). Richard Sandiford
caught a bug of mine where I overlooked the valid index range of NEON
quad-word load/stores. Quickly whipped up a fix, soon approved and
committed upstream.
* LP #744754, ICE in NEON struct-mode auto-inc-dec MEMs. Pushed upstream
patch for a merge to Linaro 4.5.
* PR46888, bit-field insert optimization patch. Resumed investigating,
mailed Andrew Pinski for more information on that REG_EQUAL note issue
he mentioned on gcc-patches; can't quite reproduce it myself.
* CoreMark ARMv6/v7 regressions: posted a patch set to gcc-patches.
Still waiting review.
* Reported to Bernd and AndrewS on an issue (LP #748138) which seems to
be related to the shrink-wrap patch. This ICE does not seem to be
avoided by doing -fno-shrink-wrap.
* A few tasks related to Linaro-Budapest event travel.
== This week ==
* Do the merge of the new combine patches to Linaro, and test.
* LP #689887 is still in progress.
* Hope to experiment with a few more optimization ideas.
Michael mentioned that some users reported seeing better preformance from
RVCT using arm_neon.h then they did when coding directly in assembler.
He suggested we try the same thing for GCC. Here's an experiment using
the example that Jim Huang posted to the dev list recently:
https://wiki.linaro.org/RichardSandiford/Sandbox/IntrinsicsPerformance
The summary is that the C version needs to borrow a trick from the
assembly code in order to be competitive. If it does that, though,
the C code can be faster. I think this is mostly down to scheduling,
although I haven't checked in detail yet.
Richard
== String and Memory routines ==
* Profiled denbench with perf and produced a set of stats to show
which programs spent how much time in libc and how
much time was spent in each routine. While some of the
benchmarks are good (like aes) and spend almost no time in libc
some of the others (MPEG codecs especially) seem to spend
significant times in libc.
* Ran all of denbench through latrace to generate sets of library
calls; post processed them to extract the section between the clock()
calls (and hence in the timed portion) and analysed the hot library
calls. I've looked at some of the output but not all of it yet; I
get output like:
Memcpy stats (dst align/src align/length/number of occurrences/total
size copied)
memcpy: 0,0,1 , 1588520, 1588520
memcpy: 16,28,4096 , 1, 4096
memcpy: 4,20,16384 , 855, 14008320
This shows that for a bunch of tests they do an inordinate number of 1
byte memcpy's, and a few hundred larger memcpy's with an address %32
which is 4
(and destination %32 is 20) - so not aligned but at least equally misaligned.
* Started writing up a report on some of the stats
* Also started to try and extract the same stuff from SPEC2k6
== QEMU ==
* Tested Peter's QEmu release earlier in the week (On Lucid so
didn't hit his natty bug)
* Wrote up a couple of specs (one for TrustZone and the other for
Device Tree integration)
== GDB ==
* Created Linaro GDB 7.2-2011.04-0 release.
* Committed patch to fix accessing "fpscr" register to Linaro GDB.
* Failure to disable address space randomization (bug #616001) has been
fixed in the kernel; closed the Linaro GDB bug.
== GCC ==
* Ongoing analysis of bug #759409 (Profiled bootstrap fails). Identified
two independent problems, one related to a new CodeSourcery feature,
and one a mis-optimization of final-stage cc1plus which is also present
in FSF GCC 4.5 (PR 43085). Ongoing investigation to track down the
root cause of the latter problem.
== Schedule ==
* Public holidays 04/22 - 04/25.
Mit freundlichen Gruessen / Best Regards
Ulrich Weigand
--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294
RAG:
Red:
Amber:
Green: another monthly qemu-linaro release out on schedule
Current Milestones:
| Planned | Estimate | Actual |
qemu-linaro 2011-04 | 2011-04-21 | 2011-04-21 | 2011-04-21 |
Historical Milestones:
finish qemu-cont-integration | 2011-01-25 | 2011-01-25 | handed off |
first qemu-linaro release | 2011-02-08 | 2011-02-08 | 2011-02-08 |
qemu-linaro 2011-03 | 2011-03-08 | 2011-03-08 | 2011-03-08 |
== maintain-beagle-models ==
* qemu-linaro 2011.04 tested and released
* had to do another last minute -1 respin to fix a problem caught by
ubuntu package builds; we need to come up with a process that lets
us do test package builds prior to release so we can fix this sort
of issue in a less last-minute fashion
== merge-correctness-fixes ==
* sent patch: fix semihosting SYS_HEAPINFO (seems to have issues though)
* sent patch: UNDEFs in Neon load/store space
* sent patches: fix build issues on sparc
* sent patch: bump the initrd load address to work with bigger kernels
* sent patch: set Invalid flag for float-to-int conversion of NaN
* sent patch: move vld/vst multiple to helper functions
* reviewed patches from Aurelien doing some general softfloat cleanup
* sent out a version of my performance counters patch which just does
a basic dummy implementation without the cycle counter (since the
cycle counter bits were going off down a blind alley rather and this
part is the last thing needed to be able to boot Linaro vexpress
images on stock upstream QEMU)
== other ==
* trying to nail down proposed QEMU work for next cycle; work-in-progress:
https://wiki.linaro.org/PeterMaydell/Qemu1111
* meetings: toolchain, standup
Current qemu patch status is tracked here:
https://wiki.linaro.org/PeterMaydell/QemuPatchStatus
Absences:
Holiday: 22 Apr - 2 May
9-13 May: UDS, Budapest
(maybe) 15-16 August: QEMU/KVM strand at LinuxCon NA, Vancouver
[LinuxCon proper follows on 17-19th]
Hi,
libunwind:
* added initial support for resuming at a certain stack frame
* posted unw_resume support plus some some testsuite fixes on the ml
* there are still some issues left if signal handlers/frames are involved
Note: Friday is a public holiday.
Regards
Ken
== This week ==
* Iterated with upstream on some of the vectorisation patches. I think
only half a patch (the ARM implementation of array_mode_supported_p)
is still pending review; everything else has been approved.
* Backported the vldN and vstN intrinsics to Linaro 4.5.
* Finished off the microbenchmarks for libav.
* One of the problems in the original libav output was that the
vectoriser didn't realise that a group of N accesses really did form
a group. It instead generated N separate interleave operations and took
1 vector from each.
Submitted a fix for that, which is now committed upstream. Updated the
libav wiki page with the new, improved output.
(This actually allowed more libav loops to be vectorised, as well
as improving the output from some of the existing ones. I haven't
looked at the new ones. I expect this comes from interleaved stores.)
* Wrote an arm_neon.h version of Android's scanline_t32cb16_neon and
compared it with the original.
* Started (and only started) seeing how the vectorisation stuff
affects DENbench.
* Backported the dwarf2out OOM fix to Linaro 4.6.
== Next week ==
* Do something useful on DENbench.
* If all goes well, commit the vectorisation work upstream and backport
it to Linaro 4.5 and 4.6.
...but it's only a three day week.
Richard
The Linaro Toolchain Working Group is pleased to announce the release
of Linaro QEMU 2011.04-1.
Linaro QEMU 2011.04-1 is the third release of qemu-linaro. Based
off upstream (trunk) qemu, it includes a number of ARM-focused
bug fixes and enhancements.
Interesting changes include:
- Compiling for an ARM host in Thumb mode now works
- As usual, various minor correctness fixes and other upstream changes
Known issues:
- The beagle and beaglexm models do not support USB, so there is no
keyboard, mouse or networking (#708703)
The only change over the shortlived 2011.04-0 is to fix a compilation
failure with gcc 4.5.
The source tarball is available at:
https://launchpad.net/qemu-linaro/+milestone/2011.04-1
Binary builds of this qemu-linaro release are being prepared and
will be available shortly for users of Ubuntu. Packages will be in
the linaro-maintainers tools ppa:
https://launchpad.net/~linaro-maintainers/+archive/tools/
More information on Linaro QEMU is available at:
https://launchpad.net/qemu-linaro
The Linaro Toolchain Working Group is pleased to announce the release
of Linaro GDB 7.2.
Linaro GDB 7.2 2011.04 is the fifth release in the 7.2 series. Based
off the latest GDB 7.2, it includes a number of ARM-focused bug fixes.
This release fixes:
* LP: #684218 Failure to backtrace out of glibc system call stubs
* LP: #667309 failed to single step over bad thumb->arm boundary
* Fix accessing "fpscr" register
The source tarball is available at:
https://launchpad.net/gdb-linaro/+milestone/7.2-2011.04-0
More information on Linaro GDB is available at:
https://launchpad.net/gdb-linaro
-- Michael
The Linaro Toolchain Working Group is pleased to announce the release
of both Linaro GCC 4.5 and Linaro GCC 4.6.
Linaro GCC 4.5 2011.04 is the ninth release in the 4.5 series. Based
off the latest
GCC 4.5.2+svn171921, it adds new optimisations, support for Android,
and fixes for many of the issues found in the last month.
Linaro GCC 4.6 2011.04 is the second release in the 4.6 series. Based off the
latest GCC 4.6.0+svn171921, it is the first supported release of the
new series and includes a significant number of mainstreamed patches
from 4.5.
Interesting changes in 4.6 include:
* Updates to 4.6.0+r171921
* Adds conditional store sinking to the vectoriser
* Brings in a significant number of the Linaro GCC 4.5 patches that
are in mainline
Interesting changes in 4.5 include:
* Updates to 4.5.2+r172013
* Disables the shrink wrap optimisation by default
* Adds support for swing-modulo scheduling (SMS) on ARM
* Adds support for Android and the Bionic C library
* Optimises -fvar-tracking, greatly reducing memory used when
compiling large files (seen in QEMU)
Fixes:
* 'volatile' being ignored on volatile struct members
* A potential register clobber in arm_negdi2
* An error in libgcc that prevented it being built with -Os
* Multiple shrink wrap bugs (LP: #731665, 721023, 736081, 758082,
730860, 736439, 721023)
* LP: #730440 incorrect immediate for movt (seen in Firebird)
* LP: #728315 extension elimination pass mishandles subregs of
promoted variables (seen on MIPS)
* LP: #675347 volatile int causes inline assembly build failure (seen
in Qt)
SMS is an optimisation that works on innermost loops and reorders the
instructions by overlapping different locations. An example is that
the values for the next loop may be loaded during the current loop,
making the values already ready when the next loop starts.
SMS is disabled by default. To try it, add the options '-fmodulo-sched
-fmodulo-sched-allow-regmoves'.
The source tarball is available from:
https://launchpad.net/gcc-linaro/+milestone/4.5-2011.04-0https://launchpad.net/gcc-linaro/+milestone/4.6-2011.04-0
Downloads are available from the Linaro GCC page on Launchpad:
https://launchpad.net/gcc-linaro
-- Michael
Here's a script for installing TI's DVSDK 3:
https://bitbucket.org/thayne/ti-omap-tools/src
Works with
- CodeSourcery
- OpenEmbedded
- Linaro
It will download the bazillion dependencies scattered across TI's site and
makes it easier to gut the DVSDK's hard-coded paths to work for your setup.
The DVSDK 4 isn't used because it is completely different from the DVSDK 3
and is much more difficult to root the hard paths and checks out of.
AJ ONeal
Hi toolchain, kernel folks,
I'm seeing an interesting thing on .got and .bss sections of
arch/arm/boot/compressed/vmlinux, and really need your expertise to
shed some lights.
I have an uninitialized variable 'uart_base' defined in misc.c.
static unsigned long uart_base;
$ arm-linux-gnueabi-objdump -D arch/arm/boot/compressed/misc.o
Disassembly of section .bss:
00000000 <uart_base>:
0: 00000000 andeq r0, r0, r0
00000004 <__machine_arch_type>:
4: 00000000 andeq r0, r0, r0
[...]
And section layout looks like the following.
$ arm-linux-gnueabi-objdump -h arch/arm/boot/compressed/vmlinux
SECTIOINS {
...
_etext = .;
_got_start = .;
.got : { *(.got) }
_got_end = .;
.got.plt : { *(.got.plt) }
_edata = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
...
}
$ arm-linux-gnueabi-objdump -h arch/arm/boot/compressed/vmlinux
arch/arm/boot/compressed/vmlinux: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 001c474c 00000000 00000000 00008000 2**5
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .got 00000028 001c474c 001c474c 001cc74c 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .got.plt 0000000c 001c4774 001c4774 001cc774 2**2
CONTENTS, ALLOC, LOAD, DATA
3 .bss 00000020 001c4780 001c4780 001cc780 2**2
ALLOC
4 .stack 00001000 001c47a0 001c47a0 001cc780 2**0
ALLOC
5 .comment 0000002a 00000000 00000000 001cc780 2**0
CONTENTS, READONLY
6 .ARM.attributes 00000031 00000000 00000000 001cc7aa 2**0
CONTENTS, READONLY
I'm able to see uart_base in vmlinux objdump ...
$ arm-linux-gnueabi-objdump -t arch/arm/boot/compressed/vmlinux
[relevant only, and sorted]
00000000 l d .text 00000000 .text
001c474c l d .got 00000000 .got
001c4774 l d .got.plt 00000000 .got.plt
001c4780 l d .bss 00000000 .bss
003968e4 g *ABS* 00000000 _image_size
001c474c g *ABS* 00000000 _got_start
001c4774 g *ABS* 00000000 _got_end
001c4780 g *ABS* 00000000 _edata
001c4780 g *ABS* 00000000 __bss_start
001c4780 l O .bss 00000004 uart_base
001c4798 g O .bss 00000004 malloc_ptr
001c478c g O .bss 00000004 output_ptr
001c479c g O .bss 00000004 malloc_count
001c4794 g O .bss 00000004 free_mem_end_ptr
001c4788 g O .bss 00000004 output_data
001c4784 g O .bss 00000004 __machine_arch_type
001c4790 g O .bss 00000004 free_mem_ptr
001c47a0 g *ABS* 00000000 _end
... but I can not see it in the zImage (all others in .bss seem still
there).
$ xxd arch/arm/boot/zImage | tail
01c4740: 3ef1 1400 be52 9f58 e468 3900 4c47 1c00 >....R.X.h9.LG..
^_got_start (why is it?)
01c4750: 9847 1c00 1043 0000 8c47 1c00 9c47 1c00 .G...C...G...G..
^malloc_ptr ^output_ptr
01c4760: 9447 1c00 080a 0000 8847 1c00 8447 1c00 .G.......G...G..
^free_mem_end_ptr ^__machine_arch_type
01c4770: 9047 1c00 0000 0000 0000 0000 0000 0000 .G..............
^free_mem_ptr
The following is a run-time memdump at _got_start.
Before recalculation:
9056304C: 001C474C 001C4798 00004310 001C478C 001C479C 001C4794 00000A08 001C4788
^_got_start (why is it?)
9056306C: 001C4784 001C4790 00000000 00000000 00000000 EDFE0DD0 4C010000 38000000
After recalculation (for .bss entries, the delta is 9039EA50, for
others in .got, delta is 9039E900):
9056304C: 9056304C 905631E8 903A2C10 905631DC 905631EC 905631E4 9039F308 905631D8
9056306C: 905631D4 905631E0 00000000 00000000 00000000 73FBC000 4C010000 38000000
QUESTION: Where is the .bss section of uart_base?
Now, I remove the 'static' to have 'unsigned long uart_base', and
dump the same stuff to compare.
$ arm-linux-gnueabi-objdump -D arch/arm/boot/compressed/misc.o
Disassembly of section .bss:
00000000 <__machine_arch_type>:
0: 00000000 andeq r0, r0, r0
00000004 <uart_base>:
4: 00000000 andeq r0, r0, r0
I'm able to see uart_base in vmlinux objdump ...
$ arm-linux-gnueabi-objdump -t arch/arm/boot/compressed/vmlinux
[relevant only, and sorted]
00000000 l d .text 00000000 .text
001c4720 l d .got 00000000 .got
001c474c l d .got.plt 00000000 .got.plt
001c4758 l d .bss 00000000 .bss
003968e4 g *ABS* 00000000 _image_size
001c4720 g *ABS* 00000000 _got_start
001c474c g *ABS* 00000000 _got_end
001c4758 g *ABS* 00000000 _edata
001c4758 g *ABS* 00000000 __bss_start
001c475c g O .bss 00000004 uart_base
001c4770 g O .bss 00000004 malloc_ptr
001c4764 g O .bss 00000004 output_ptr
001c4774 g O .bss 00000004 malloc_count
001c476c g O .bss 00000004 free_mem_end_ptr
001c4760 g O .bss 00000004 output_data
001c4758 g O .bss 00000004 __machine_arch_type
001c4768 g O .bss 00000004 free_mem_ptr
001c4778 g *ABS* 00000000 _end
... and I can also see it in the final zImage.
$ xxd arch/arm/boot/zImage | tail
01c4710: 221f f1b3 3ef1 1400 be52 9f58 e468 3900 "...>....R.X.h9.
01c4720: 5c47 1c00 2047 1c00 7047 1c00 e442 0000 \G.. G..pG...B..
^uart_base
01c4730: 6447 1c00 7447 1c00 6c47 1c00 140a 0000 dG..tG..lG......
01c4740: 6047 1c00 5847 1c00 6847 1c00 0000 0000 `G..XG..hG......
01c4750: 0000 0000 0000 0000 ........
Surely, it's in the run-time memdump.
Before recalculation:
90563020: 001C475C 001C4720 001C4770 000042E4 001C4764 001C4774 001C476C 00000A14
^uart_base
90563040: 001C4760 001C4758 001C4768 00000000 00000000 00000000 EDFE0DD0 4C010000
After recalculation:
90563020: 905631AC 90563020 905631C0 903A2BE4 905631B4 905631C4 905631BC 9039F314
90563040: 905631B0 905631A8 905631B8 00000000 00000000 00000000 EDFE0DD0 4C010000
So it looks the non-static ('g') uninitialized variable sits in .bss
sections well, while static ('l') one is not there. Is this
expected? How the static one is being addressed? Or ask where the
offset for static one is stored?
Any info or comments are appreciated.
--
Regards,
Shawn
I've just submitted a merge request for the vldN and vstN intrinsic
improvements. There are five related patches, so I thought it might
be easier to review the merge if I posted the individual changes here.
See:
http://www.mail-archive.com/linaro-toolchain@lists.linaro.org/msg00969.html
for an example of how this helps.
Richard
I just did `git checkout` for linaro/linux-2.6.38 and tried compiling with
CROSS_COMPILE=arm-linux-gnueabi- and I get this smc #0 error.
The bug filed here is marked as fixed, but it's still broken for me:
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/669912
I ran into this error once before, but I can't find my notes for it.
I think the solution was to append something like $(sec) on a line in the
Makefile.
Any ideas?
AJ ONeal
Hi there. I'd like to change and clarify how we make changes inside
Linaro toolchain projects. The write-up is here:
https://wiki.linaro.org/WorkingGroups/ToolChain/MakingChanges
The short story is that now, just like mainline, the developers
themselves do the final commit or merge into bzr. I've volunteered
three of you on a review roster so that someone has the responsibility
for reviewing patches each week. The roster is:
* Ramana week 15, 17, 20, ... starting the 11th of April 2011
* Richard week 16, 18, 21, ... starting the 18th of April 2011
* Ulrich week 17, 19, 22, ... starting the 25th of April 2011
Anyone is welcome to review patches. The more eyes the better.
Thoughts?
-- Michael
I'm just curious as to what "__aeabi_unwind_cpp_pr0" is or means.
I can't find any explanation by googling.
I'm about to post a separate e-mail with my problem concerning it.
AJ ONeal
Reviewed and approved Revital's do-loop patch, and Ira's store sinking
patch. More precisely, I reviewed the test results from Michael's test
system, and cast my eye over the patch to look for anything obvious. I
don't pretend to know exactly what they do.
Attended Ramana's thumb2 optimization discussion.
Continued work on merging useful patches from CodeSourcery. Pushed the
new patch set to Launchpad for testing in Michael's system.
Pointed Bernd at lp:758082 - another probable shrink-wrap failure. Bernd
responded with a new patch, and asked me to test it. I've pushed it to
Launchpad and created a merge request.
Posted an old patch of Dan's upstream:
http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg03144.html
Pinged my thumb2 constants patch upstream. Richard E responded with some
issues to address. I'll need to change the names of the constraints, at
least.
At Ramana's request, tested the NEON scheduling patch with SPEC2000.
Encountered trouble with time-outs. Fixed those and retested.
Posted an updated version of my EABI half-precision patch:
http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg03210.html
Merged my backport of Julian's -fstrict-volatile-bitfields bug fix into
Linaro GCC.
The testing of the Android patches came back with a few test
differences, but they appear to be unrelated to the patch, so are
probably environmental. I've merged the changes to Linaro GCC.
[Also spent most of Friday working on internal CS tasks.]
----
Upstream patched requiring review:
* NEON scheduling patch
http://gcc.gnu.org/ml/gcc-patches/2011-02/msg01431.html
* NEON test cases
http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg03144.html
* ARM EABI half-precision functions (reposted)
http://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg03210.html
== Last week ==
* CoreMark regressions: pushed a merge of my two upstream patches to
Linaro 4.5, some current numbers are here:
http://lists.linaro.org/pipermail/linaro-toolchain/2011-April/001087.html.
* Continued working on another combine patch for improving CoreMark,
hopefully ready to submit this week.
* Committed fix for PR48325 (NEON POST_INC/PRE_DEC load/stores for
struct modes) upstream.
* Committed fix for PR48250 / Launchpad #723185 upstream.
* Launchpad #689887, ICE in get_arm_condition_code(). My prior patch was
tested to cause native bootstrap failure on Linaro 4.5, though retesting
on upstream trunk worked fine. Still investigating.
* Booked travel for Linaro-Budapest event.
== This week ==
* Current combine patch.
* Some unresolved patches, like PR46888.
* Launchpad #689887, hope to figure this out.
I've started up a page with ideas for sessions at next month's summit:
https://wiki.linaro.org/MichaelHope/Sandbox/1111Blueprints
They're a pretty direct map to the TSC technical topics so far which
is nice to see. Feel free to add other ideas to the page. Each
session is around 45 minutes, needs to be fairly well understood by
the drafter beforehand, and should have concrete actions coming out of
it. It's fine to have a few future/blue sky sessions but not too
many.
We'll discuss these at tonights meeting and assign drafters.
-- Michael
