- linaro-toolchain - lists.linaro.org

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + tracked down the UEFI crash with KVM on AArch64 to a combination of (a) host system was heterogenous and user hadn't restricted QEMU to only running on one set of cores and (b) QEMU silently throws away the error it gets from KVM in this situation, resulting in most things seeming to work except that vcpu power on/off state isn't written to KVM and so the guest starts with all vcpus running instead of just the primary. We should really improve the error handling, but I worry that that might break previously functional setups... + tidied up some patches I wrote while doing the GICv4 work that fix an odd inconsistency in our GIC emulation where we correctly implement the right number of virtual priority bits for the CPU but always provide 8 bits of physical priority regardless of what the real CPU implementation should have, and sent them out for review + usual code review and pullreq management * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] + Implemented support for FEAT_S2FWB and sent patches to the list + Next up is probably FEAT_IDST (ID space trap handling) -- PMM

3 years

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clang-aarch64-sve-vls-2stage builder is red for about a month

by Galina Kistanova

Hello Linaro Toolchain Working Group. clang-aarch64-sve-vls-2stage builder is red for about a month. Is anybody looking at the issue? Thanks Galina

3 years

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[ACTIVITY] Report for week #17

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Continued working on the testsuite regressions introduced by my code. - Realised that gdbserver uses “thread->tdesc != NULL” as a proxy of whether it has already attached to the inferior process. My change to track the target description per-thread instead of per-process invalidated this equivalence. Fixed a few places to use “proc->attached” instead, which is the direct way of testing that condition. - Now looking into an issue with gdbserver loading libthread_db.so. # Misc - Reviewed Tom Tromey's “[PATCH 00/36] C++-ify breakpoints” patch series¹. Spotted one bug. -- Thiago ¹ https://sourceware.org/pipermail/gdb-patches/2022-January/185256.html msgid:20220118194007.2853108-1-tom@tromey.com

3 years

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[ACTIVITY] week ending May. 1 2022

by Alex Bennée

Project Stratos =============== - posted [RFC PATCH] xen/arm: p2m don't fall over on FEAT_LPA enabled hw Message-Id: <20220426160548.2020794-1-alex.bennee(a)linaro.org> - posted [PATCH v2] xen/arm: p2m don't fall over on FEAT_LPA enabled hw Message-Id: <20220428103410.2723837-1-alex.bennee(a)linaro.org> vhost-device maintainer effort ([UM-196]) - adopted [PATCH 0/2] virtio: Add vhost-user-gpio device's support Message-Id: <5f560cab92d0d789b1c94295ec74b9952907d69d.1641987128.git.viresh.kumar(a)linaro.org> - posted [RFC PATCH v2] tests/qtest: attempt to enable tests for virtio-gpio (!working) Message-Id: <20220408155704.2777166-1-alex.bennee(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 00/15] testing, docs, tracepoints and cputlb hacks Message-Id: <20220408164742.2844631-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/i386: avoid copying junk to extended ZMMReg fields Message-Id: <20220411145609.3932882-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] gdb/gic: expose cpu_index via MxTxAttrs Message-Id: <20220412104519.201655-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/guest-debug: better handle gdb crashes Message-Id: <20220413121115.639610-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [5/5] ======================= [PATCH for-7.1 v2 00/39] Logging cleanup and per-thread logfiles Message-Id: <20220326132534.543738-1-richard.henderson(a)linaro.org> [PATCH 00/17] tests/docker and tests/tcg cleanup and diet Message-Id: <20220401141326.1244422-1-pbonzini(a)redhat.com> [PATCH v1] virtio/virtio.c: include virtio prefix in error message Message-Id: <20220414112902.41390-1-codeguy.moteen(a)gmail.com> [PATCH v3 00/39] Logging cleanup and per-thread logfiles Message-Id: <20220417183019.755276-1-richard.henderson(a)linaro.org> [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus Message-Id: <20220417174426.711829-1-richard.henderson(a)linaro.org> - or at least a chunk of it Absences ======== - finally got hit with COVID Current Review Queue ==================== TODO [PATCH 0/9] Record/replay refactoring and stuff Message-Id: <165062838915.526882.13230207960407998257.stgit@pasha-ThinkPad-X280> ==================================================================================================================================== TODO [RFC PATCH 0/6] virtio: Solution to restrict memory access under Xen using xen-virtio DMA ops layer Message-Id: <1649963973-22879-1-git-send-email-olekstysh(a)gmail.com> =========================================================================================================================================================================== TODO [PATCH 0/5] Vhost-user: add Virtio RSS support Message-Id: <20220408122813.1357045-1-maxime.coquelin(a)redhat.com> ==================================================================================================================== -- Alex Bennée

3 years

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[ACTIVITY] report week ending 28 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + investigating a bug report about the guest UEFI crashing on startup when using KVM on AArch64 with an SMP guest (sadly I haven't been able to repro it myself thus far) * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] + audited code to check we can enable FEAT_TTL in QEMU (ie we ignore the new TTL hint field in TLB invalidate operations) + audited code to check we can enable FEAT_BBM level 2 in QEMU (our TLB implementation never allows multiple clashing TLB entries) + audited code to check we can enable SMMUv3.2-BBML2 in our SMMUv3 (our SMMU TLB does allow multiple entries but will always select the one for the lowest level and ignore the others) + sent patches to advertise FEAT_TTL, FEAT_BBM, SMMUv3.2-BBML2 in CPU and SMMU ID registers -- PMM

3 years

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[ACTIVITY] Report for week #16

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Found and fixed problem with the gdbserver prototype: it didn't clear the registers cache when the target description changed. The prototype is working now. * Turned my attention to the testsuite regressions introduced by my changes. Fixed one where gdbserver was crashing when debugging multi-threaded programs, and now investigating one where gdbserver returns an error when handling the ‘vRun’ remote protocol packet. # Misc * Public holiday on Thursday — but I took it on Friday instead. -- Thiago

3 years

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[ACTIVITY] report week ending 22 Apr

by Peter Maydell

Progress (two half-weeks): * UM-2 [QEMU upstream maintainership] + Got the 7.0 release out of the door and handed over pullrequest processing to RTH for the 7.1 cycle \o/ + Code review backlog now pretty nearly empty (worked through several large patchsets from RTH as well as some smaller things) + two arm pullreqs for 7.1 sent out already * QEMU-420 [GICv4 emulation] + The GICv4 emulation has now made it through code review and since we've released 7.0 it is now in upstream git for 7.1 + The GICv4.1 work has been moved to a new epic QEMU-479, as we're not going to do that immediately + This epic is therefore closed! -- PMM

3 years

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[ACTIVITY] Report for week #15

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Implemented prototype of GDB and gdbserver changing the target description in sync when the vg pseudo-register changes. The GDB side seems to be working, but gdbserver still has issues which I'm currently debugging. # Misc * Public holiday on Friday. -- Thiago

3 years

1
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[ACTIVITY] week ending Apr. 17 2022

by Alex Bennée

Project Stratos =============== - syncs with Takihiro on VFIO networking vhost-device maintainer effort ([UM-196]) - adopted [PATCH 0/2] virtio: Add vhost-user-gpio device's support Message-Id: <5f560cab92d0d789b1c94295ec74b9952907d69d.1641987128.git.viresh.kumar(a)linaro.org> - posted [RFC PATCH v2] tests/qtest: attempt to enable tests for virtio-gpio (!working) Message-Id: <20220408155704.2777166-1-alex.bennee(a)linaro.org> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 00/15] testing, docs, tracepoints and cputlb hacks Message-Id: <20220408164742.2844631-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] target/i386: avoid copying junk to extended ZMMReg fields Message-Id: <20220411145609.3932882-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] gdb/gic: expose cpu_index via MxTxAttrs Message-Id: <20220412104519.201655-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/guest-debug: better handle gdb crashes Message-Id: <20220413121115.639610-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH for-7.1 v2 00/39] Logging cleanup and per-thread logfiles Message-Id: <20220326132534.543738-1-richard.henderson(a)linaro.org> [PATCH 00/17] tests/docker and tests/tcg cleanup and diet Message-Id: <20220401141326.1244422-1-pbonzini(a)redhat.com> [PATCH v1] virtio/virtio.c: include virtio prefix in error message Message-Id: <20220414112902.41390-1-codeguy.moteen(a)gmail.com> Absences ======== - finally got hit with COVID Current Review Queue ==================== TODO [RFC PATCH 0/6] virtio: Solution to restrict memory access under Xen using xen-virtio DMA ops layer Message-Id: <1649963973-22879-1-git-send-email-olekstysh(a)gmail.com> =========================================================================================================================================================================== TODO [PATCH 0/5] Vhost-user: add Virtio RSS support Message-Id: <20220408122813.1357045-1-maxime.coquelin(a)redhat.com> ==================================================================================================================== TODO [PATCH 0/3] vhost-user: Fixes for VHOST_USER_ADD/REM_MEM_REG Message-Id: <20220407133657.155281-1-kwolf(a)redhat.com> ======================================================================================================================= -- Alex Bennée

3 years

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[TCWG CI] Regression caused by gcc: tree.cc: Add tree_builtin_call_types_compatible_p [PR105150]

by ci_notify＠linaro.org

[TCWG CI] Regression caused by gcc: tree.cc: Add tree_builtin_call_types_compatible_p [PR105150]: commit 973a2ce71f8dab559fbbfc34b59e39e047df74a6 Author: Jakub Jelinek <jakub(a)redhat.com> tree.cc: Add tree_builtin_call_types_compatible_p [PR105150] Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 7205 # First few build errors in logs: # 00:11:32 make[1]: *** [scripts/Makefile.modpost:134: modules-only.symvers] Error 1 # 00:11:32 make: *** [Makefile:1749: modules] Error 2 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 8131 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_kernel/gnu-master-aarch64-mainline-defconfig First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-mainlin… Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-mainlin… Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-mainlin… Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-mainlin… Reproduce builds: <cut> mkdir investigate-gcc-973a2ce71f8dab559fbbfc34b59e39e047df74a6 cd investigate-gcc-973a2ce71f8dab559fbbfc34b59e39e047df74a6 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-mainlin… --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-mainlin… --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-aarch64-mainlin… --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach 973a2ce71f8dab559fbbfc34b59e39e047df74a6 ../artifacts/test.sh # Reproduce last_good build git checkout --detach 54ed6563d22694aa3e1935f89641a4f696a3a9f7 ../artifacts/test.sh cd .. </cut> Full commit (up to 1000 lines): <cut> commit 973a2ce71f8dab559fbbfc34b59e39e047df74a6 Author: Jakub Jelinek <jakub(a)redhat.com> Date: Thu Apr 7 09:10:58 2022 +0200 tree.cc: Add tree_builtin_call_types_compatible_p [PR105150] And here is the follow-up patch that does the argument checking on GENERIC. It ensures TYPE_MAIN_VARIANT == TYPE_MAIN_VARIANT compatibility on the arguments, except for pointer arguments where both builtin's prototype and actual arguments have to be pointers and satisfy tree_nop_conversion_p, and for promoted char/short arguments where argument need to have integral signed type tree_nop_conversion_p compatible with integer_type_node. 2022-04-07 Jakub Jelinek <jakub(a)redhat.com> PR tree-optimization/105150 * tree.cc (tree_builtin_call_types_compatible_p): New function. (get_call_combined_fn): Use it. * gcc.dg/pr105150.c: New test. --- gcc/testsuite/gcc.dg/pr105150.c | 8 ++++++ gcc/tree.cc | 57 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/pr105150.c b/gcc/testsuite/gcc.dg/pr105150.c new file mode 100644 index 00000000000..900460c1555 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr105150.c @@ -0,0 +1,8 @@ +/* PR tree-optimization/105150 */ +/* { dg-options "-w -Ofast" } */ + +#define A(name) __typeof (__builtin_##name (0)) name (); \ + float name##1 () { return !name (1); } \ + double name##2 () { return name (1.0L); } +#define B(name) A(name) A(name##l) +B (sqrt) diff --git a/gcc/tree.cc b/gcc/tree.cc index ec200e9a7eb..8f83ea1aae3 100644 --- a/gcc/tree.cc +++ b/gcc/tree.cc @@ -8406,6 +8406,59 @@ get_callee_fndecl (const_tree call) return NULL_TREE; } +/* Return true when STMTs arguments and return value match those of FNDECL, + a decl of a builtin function. */ + +static bool +tree_builtin_call_types_compatible_p (const_tree call, tree fndecl) +{ + gcc_checking_assert (DECL_BUILT_IN_CLASS (fndecl) != NOT_BUILT_IN); + + if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL) + if (tree decl = builtin_decl_explicit (DECL_FUNCTION_CODE (fndecl))) + fndecl = decl; + + if (TYPE_MAIN_VARIANT (TREE_TYPE (call)) + != TYPE_MAIN_VARIANT (TREE_TYPE (TREE_TYPE (fndecl)))) + return false; + + tree targs = TYPE_ARG_TYPES (TREE_TYPE (fndecl)); + unsigned nargs = call_expr_nargs (call); + for (unsigned i = 0; i < nargs; ++i, targs = TREE_CHAIN (targs)) + { + /* Variadic args follow. */ + if (!targs) + return true; + tree arg = CALL_EXPR_ARG (call, i); + tree type = TREE_VALUE (targs); + if (TYPE_MAIN_VARIANT (type) != TYPE_MAIN_VARIANT (TREE_TYPE (arg))) + { + /* For pointer arguments be more forgiving, e.g. due to + FILE * vs. fileptr_type_node, or say char * vs. const char * + differences etc. */ + if (POINTER_TYPE_P (type) + && POINTER_TYPE_P (TREE_TYPE (arg)) + && tree_nop_conversion_p (type, TREE_TYPE (arg))) + continue; + /* char/short integral arguments are promoted to int + by several frontends if targetm.calls.promote_prototypes + is true. Allow such promotion too. */ + if (INTEGRAL_TYPE_P (type) + && TYPE_PRECISION (type) < TYPE_PRECISION (integer_type_node) + && INTEGRAL_TYPE_P (TREE_TYPE (arg)) + && !TYPE_UNSIGNED (TREE_TYPE (arg)) + && targetm.calls.promote_prototypes (TREE_TYPE (fndecl)) + && tree_nop_conversion_p (integer_type_node, + TREE_TYPE (arg))) + continue; + return false; + } + } + if (targs && !VOID_TYPE_P (TREE_VALUE (targs))) + return false; + return true; +} + /* If CALL_EXPR CALL calls a normal built-in function or an internal function, return the associated function code, otherwise return CFN_LAST. */ @@ -8419,7 +8472,9 @@ get_call_combined_fn (const_tree call) return as_combined_fn (CALL_EXPR_IFN (call)); tree fndecl = get_callee_fndecl (call); - if (fndecl && fndecl_built_in_p (fndecl, BUILT_IN_NORMAL)) + if (fndecl + && fndecl_built_in_p (fndecl, BUILT_IN_NORMAL) + && tree_builtin_call_types_compatible_p (call, fndecl)) return as_combined_fn (DECL_FUNCTION_CODE (fndecl)); return CFN_LAST; </cut>

3 years, 1 month

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[ACTIVITY] Report for week #14

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Got prototype of variable length vectors in GDB target descriptions barely working, but fell down a rabbit hole trying to fix an issue with the vector register size being misreported by ‘sizeof()’. Decided to change tack and implement the simpler aim of updating the client and server target descriptions in sync when the vector length changes. This is Luis' idea from 2020¹, and closer to how native GDB debugging currently works in this scenario. -- Thiago ¹ https://sourceware.org/pipermail/gdb/2020-January/048341.html

3 years, 1 month

1
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[ACTIVITY] week ending Apr. 10 2022

by Alex Bennée

Project Stratos =============== vhost-device maintainer effort ([UM-196]) - maintainer review work - adopted [PATCH 0/2] virtio: Add vhost-user-gpio device's support Message-Id: <5f560cab92d0d789b1c94295ec74b9952907d69d.1641987128.git.viresh.kumar(a)linaro.org> - posted [RFC PATCH v2] tests/qtest: attempt to enable tests for virtio-gpio (!working) Message-Id: <20220408155704.2777166-1-alex.bennee(a)linaro.org> [UM-196] <https://linaro.atlassian.net/browse/UM-196> Linux RPMB Sub-system and virtio-driver ([STR-40]) - posted [PATCH v2 0/4] rpmb subsystem, uapi and virtio-rpmb driver Message-Id: <20220405093759.1126835-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] tests/qtest: properly initialise the vring used idx Message-Id: <20220406173356.1891500-1-alex.bennee(a)linaro.org> [STR-40] <https://linaro.atlassian.net/browse/STR-40> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] tests/qtest: pass stdout/stderr down to subtests Message-Id: <20220407150042.2338562-1-alex.bennee(a)linaro.org> - posted [PATCH v1 00/15] testing, docs, tracepoints and cputlb hacks Message-Id: <20220408164742.2844631-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH 00/15] tests/docker and tests/tcg cleanup and diet Message-Id: <87czi6xbzo.fsf(a)linaro.org> [PATCH] plugins: Assert mmu_idx in range before use in qemu_plugin_get_hwaddr Message-Id: <20220401190233.329360-1-richard.henderson(a)linaro.org> [PATCH v3 0/5] qtests/libqos: Allow PCI tests to be run with virt-machine Message-Id: <20220210145254.157790-1-eric.auger(a)redhat.com> Absences ======== - dodging COVID while the rest of the household has it Current Review Queue ==================== TODO [PATCH v9 00/45] CXl 2.0 emulation Support Message-Id: <20220404151445.10955-19-Jonathan.Cameron(a)huawei.com> ================================================================================================================ TODO [PATCH for-7.1 v2 00/39] Logging cleanup and per-thread logfiles Message-Id: <20220326132534.543738-1-richard.henderson(a)linaro.org> ======================================================================================================================================= TODO [PATCH 00/11] edk2: update to stable202202 Message-Id: <20220308145521.3106395-1-kraxel(a)redhat.com> ======================================================================================================= -- Alex Bennée

3 years, 1 month

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[weekly][linaro] report week ending 8 Apr

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + Finished sorting out the exynos4210 SoC interrupt wiring and sent a patchset that cleans it up and makes it stop using qemu_split_irq() + rc3 tagged this week. We will need an rc4 next week for a couple of late-breaking security fixes. * QEMU-420 [GICv4 emulation] + Finished the last bits of debugging and wiring up GICv4 support on the virt board, and sent initial patchset to the list for review: https://patchew.org/QEMU/20220408141550.1271295-1-peter.maydell@linaro.org/ -- PMM

3 years, 1 month

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[ACTIVITY] Report for week #13

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Moved tracking of this work from GNU-732 (GDB support for SME) to more specific story GNU-767. * Started writing prototype of variable length vectors in GDB target descriptions. # Basic setup / onboarding - Read a couple more Linaro processes documents. # Misc * Attended Linaro Connect Tech Day: Core Technologies. -- Thiago

3 years, 1 month

1
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[ACTIVITY] week ending Apr. 3 2022

by Alex Bennée

Project Stratos =============== - more follow-up on Re: Understanding osdep_xenforeignmemory_map mmap behaviour Message-Id: <alpine.DEB.2.22.394.2203231838130.2910984@ubuntu-linux-20-04-desktop> - various Stratos sync-ups vhost-device maintainer effort ([UM-196]) - bit of maintainer review work Linux RPMB Sub-system and virtio-driver ([STR-40]) - got [kernel] and [vhost-user] daemon passing all tests with multi-block reads/writes - will clean-up series next week for posting to the lists [STR-40] <https://linaro.atlassian.net/browse/STR-40> [kernel] <https://git.linaro.org/people/alex.bennee/linux.git/tag/?h=testing/vrpmb-re…> [vhost-user] <https://github.com/stsquad/qemu/tree/virtio/vhost-user-rpmb-v2> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH v1 0/2] some tests and plugin tweaks for SVE Message-Id: <20220328152614.2452259-1-alex.bennee(a)linaro.org> - posted [PATCH v3] tests/avocado: update aarch64_virt test to exercise -cpu max Message-Id: <20220328161357.2464572-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] docs/devel: add some notes on the binfmt-image-debian targets Message-Id: <20220329095041.2758355-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - Presented [LTD 2022 QEMU talk] - attneded some others [LTD 2022 QEMU talk] <https://resources.linaro.org/en/resource/tL9M2yyti73StqK1d9ap8f> Completed Reviews [1/1] ======================= [PATCH 00/15] tests/docker and tests/tcg cleanup and diet Message-Id: <87czi6xbzo.fsf(a)linaro.org> Absences ======== Current Review Queue ==================== TODO [PATCH 00/17] tests/docker and tests/tcg cleanup and diet Message-Id: <20220401141326.1244422-1-pbonzini(a)redhat.com> ======================================================================================================================== TODO [RFC PATCH 0/6] softfloat 128-bit integer support Message-Id: <20220328201442.175206-1-matheus.ferst(a)eldorado.org.br> ========================================================================================================================= TODO [PATCH for-7.1 v2 00/39] Logging cleanup and per-thread logfiles Message-Id: <20220326132534.543738-1-richard.henderson(a)linaro.org> ======================================================================================================================================= -- Alex Bennée

3 years, 1 month

1
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[ACTIVITY] report week ending 1 Apr

by Peter Maydell

Progress (short week, 2 days): * UM-2 [QEMU upstream maintainership] + More of the usual freeze-related work + Tracked down and fixed assertion when running with clang sanitizers + We finally got a Coverity Scan run through for the first time in a month or two, and it was full of new issues. Spent some time going through them and marking false positives or reporting the problems back to original code authors to be fixed + Looking at the tangle of interrupt lines in our exynos4210 SoC model -- this needs a refactoring and cleanup so we can get rid of its uses of an obsolete function -- PMM

3 years, 1 month

1
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Re: [TCWG CI] 456.hmmer grew in size by 9% after llvm: Extend the `uwtable` attribute with unwind table kind

by Maxim Kuvyrkov

Hi Momchil, Your patch seems to significantly increase code-size of several benchmarks — by up to 9%. Would you please investigate whether this can be avoided? Please let us know if you need assistance with reproducing the regressions. Thank you, -- Maxim Kuvyrkov https://www.linaro.org > On 25 Mar 2022, at 14:45, ci_notify(a)linaro.org wrote: > > After llvm commit 6398903ac8c141820a84f3063b7956abe1742500 > Author: Momchil Velikov <momchil.velikov(a)arm.com> > > Extend the `uwtable` attribute with unwind table kind > > the following benchmarks grew in size by more than 1%: > - 456.hmmer grew in size by 9% from 104960 to 113912 bytes > - 403.gcc grew in size by 9% from 2191632 to 2394404 bytes > - 400.perlbench grew in size by 9% from 803690 to 879478 bytes > - 458.sjeng grew in size by 5% from 102355 to 107719 bytes > - 401.bzip2 grew in size by 3% from 43428 to 44772 bytes > > Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI. > > For your convenience, we have uploaded tarballs with pre-processed source and assembly files at: > - First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > - Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > - Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > > Configuration: > - Benchmark: SPEC CPU2006 > - Toolchain: Clang + Glibc + LLVM Linker > - Version: all components were built from their tip of trunk > - Target: aarch64-linux-gnu > - Compiler flags: -Oz -flto > - Hardware: APM Mustang 8x X-Gene1 > > This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. > > THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. > > This commit has regressed these CI configurations: > - tcwg_bmk_llvm_apm/llvm-master-aarch64-spec2k6-Oz_LTO > > First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > > Reproduce builds: > <cut> > mkdir investigate-llvm-6398903ac8c141820a84f3063b7956abe1742500 > cd investigate-llvm-6398903ac8c141820a84f3063b7956abe1742500 > > # Fetch scripts > git clone https://git.linaro.org/toolchain/jenkins-scripts > > # Fetch manifests and test.sh script > mkdir -p artifacts/manifests > curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail > curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail > curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail > chmod +x artifacts/test.sh > > # Reproduce the baseline build (build all pre-requisites) > ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh > > # Save baseline build state (which is then restored in artifacts/test.sh) > mkdir -p ./bisect > rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/ > > cd llvm > > # Reproduce first_bad build > git checkout --detach 6398903ac8c141820a84f3063b7956abe1742500 > ../artifacts/test.sh > > # Reproduce last_good build > git checkout --detach 48f188433335846bba4cf3e5e9fa2150d4c0253b > ../artifacts/test.sh > > cd .. > </cut> > > Full commit (up to 1000 lines): > <cut> > commit 6398903ac8c141820a84f3063b7956abe1742500 > Author: Momchil Velikov <momchil.velikov(a)arm.com> > Date: Mon Feb 14 13:41:34 2022 +0000 > > Extend the `uwtable` attribute with unwind table kind > > We have the `clang -cc1` command-line option `-funwind-tables=1|2` and > the codegen option `VALUE_CODEGENOPT(UnwindTables, 2, 0) ///< Unwind > tables (1) or asynchronous unwind tables (2)`. However, this is > encoded in LLVM IR by the presence or the absence of the `uwtable` > attribute, i.e. we lose the information whether to generate want just > some unwind tables or asynchronous unwind tables. > > Asynchronous unwind tables take more space in the runtime image, I'd > estimate something like 80-90% more, as the difference is adding > roughly the same number of CFI directives as for prologues, only a bit > simpler (e.g. `.cfi_offset reg, off` vs. `.cfi_restore reg`). Or even > more, if you consider tail duplication of epilogue blocks. > Asynchronous unwind tables could also restrict code generation to > having only a finite number of frame pointer adjustments (an example > of *not* having a finite number of `SP` adjustments is on AArch64 when > untagging the stack (MTE) in some cases the compiler can modify `SP` > in a loop). > Having the CFI precise up to an instruction generally also means one > cannot bundle together CFI instructions once the prologue is done, > they need to be interspersed with ordinary instructions, which means > extra `DW_CFA_advance_loc` commands, further increasing the unwind > tables size. > > That is to say, async unwind tables impose a non-negligible overhead, > yet for the most common use cases (like C++ exceptions), they are not > even needed. > > This patch extends the `uwtable` attribute with an optional > value: > - `uwtable` (default to `async`) > - `uwtable(sync)`, synchronous unwind tables > - `uwtable(async)`, asynchronous (instruction precise) unwind tables > > Reviewed By: MaskRay > > Differential Revision: https://reviews.llvm.org/D114543 > --- > clang/lib/CodeGen/CGExpr.cpp | 2 +- > clang/lib/CodeGen/CodeGenModule.cpp | 4 +- > clang/test/CodeGen/asan-globals.cpp | 2 +- > clang/test/CodeGen/uwtable-attr.c | 30 +++++ > llvm/bindings/go/llvm/ir_test.go | 1 - > llvm/docs/LangRef.rst | 12 +- > llvm/include/llvm/AsmParser/LLParser.h | 1 + > llvm/include/llvm/AsmParser/LLToken.h | 2 + > llvm/include/llvm/IR/Attributes.h | 13 +++ > llvm/include/llvm/IR/Attributes.td | 2 +- > llvm/include/llvm/IR/Function.h | 12 +- > llvm/include/llvm/IR/Module.h | 4 +- > llvm/include/llvm/Support/CodeGen.h | 8 +- > llvm/lib/AsmParser/LLLexer.cpp | 2 + > llvm/lib/AsmParser/LLParser.cpp | 23 ++++ > llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 4 + > llvm/lib/CodeGen/MachineOutliner.cpp | 9 ++ > llvm/lib/IR/AttributeImpl.h | 1 + > llvm/lib/IR/Attributes.cpp | 50 ++++++++ > llvm/lib/IR/Function.cpp | 5 +- > llvm/lib/IR/Module.cpp | 11 +- > llvm/test/Assembler/uwtable-1.ll | 7 ++ > llvm/test/Assembler/uwtable-2.ll | 4 + > llvm/test/Bitcode/attributes.ll | 11 ++ > llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll | 4 +- > llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll | 5 +- > .../AddressSanitizer/module-flags.ll | 2 +- > .../Attributor/ArgumentPromotion/X86/attributes.ll | 34 +++--- > .../X86/min-legal-vector-width.ll | 128 ++++++++++----------- > llvm/test/Transforms/Attributor/align.ll | 48 ++++---- > llvm/test/Transforms/Attributor/allow_list.ll | 4 +- > .../Transforms/Attributor/cb_liveness_disabled.ll | 4 +- > .../Transforms/Attributor/cb_liveness_enabled.ll | 4 +- > .../test/Transforms/Attributor/internal-noalias.ll | 28 ++--- > llvm/test/Transforms/Attributor/liveness.ll | 12 +- > llvm/test/Transforms/Attributor/nocapture-2.ll | 48 ++++---- > llvm/test/Transforms/Attributor/nofree.ll | 38 +++--- > llvm/test/Transforms/Attributor/noreturn.ll | 12 +- > llvm/test/Transforms/Attributor/nosync.ll | 28 ++--- > llvm/test/Transforms/Attributor/returned.ll | 48 ++++---- > .../Attributor/value-simplify-pointer-info.ll | 14 +-- > llvm/test/Transforms/Attributor/willreturn.ll | 56 ++++----- > llvm/test/Transforms/FunctionAttrs/atomic.ll | 4 +- > .../Transforms/FunctionAttrs/nofree-attributor.ll | 2 +- > llvm/test/Transforms/FunctionAttrs/nofree.ll | 2 +- > llvm/test/Transforms/FunctionAttrs/nosync.ll | 16 +-- > llvm/test/Transforms/GCOVProfiling/module-flags.ll | 2 +- > .../Inputs/check_attrs.ll.funcattrs.expected | 2 +- > llvm/unittests/IR/VerifierTest.cpp | 3 +- > 49 files changed, 473 insertions(+), 295 deletions(-) > > diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp > index fa45554bb54f..e0e1dd5df586 100644 > --- a/clang/lib/CodeGen/CGExpr.cpp > +++ b/clang/lib/CodeGen/CGExpr.cpp > @@ -3188,7 +3188,7 @@ static void emitCheckHandlerCall(CodeGenFunction &CGF, > B.addAttribute(llvm::Attribute::NoReturn) > .addAttribute(llvm::Attribute::NoUnwind); > } > - B.addAttribute(llvm::Attribute::UWTable); > + B.addUWTableAttr(llvm::UWTableKind::Default); > > llvm::FunctionCallee Fn = CGF.CGM.CreateRuntimeFunction( > FnType, FnName, > diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp > index 772059a436d1..c99fd899ac93 100644 > --- a/clang/lib/CodeGen/CodeGenModule.cpp > +++ b/clang/lib/CodeGen/CodeGenModule.cpp > @@ -828,7 +828,7 @@ void CodeGenModule::Release() { > if (CodeGenOpts.NoPLT) > getModule().setRtLibUseGOT(); > if (CodeGenOpts.UnwindTables) > - getModule().setUwtable(); > + getModule().setUwtable(llvm::UWTableKind(CodeGenOpts.UnwindTables)); > > switch (CodeGenOpts.getFramePointer()) { > case CodeGenOptions::FramePointerKind::None: > @@ -1839,7 +1839,7 @@ void CodeGenModule::SetLLVMFunctionAttributesForDefinition(const Decl *D, > llvm::AttrBuilder B(F->getContext()); > > if (CodeGenOpts.UnwindTables) > - B.addAttribute(llvm::Attribute::UWTable); > + B.addUWTableAttr(llvm::UWTableKind(CodeGenOpts.UnwindTables)); > > if (CodeGenOpts.StackClashProtector) > B.addAttribute("probe-stack", "inline-asm"); > diff --git a/clang/test/CodeGen/asan-globals.cpp b/clang/test/CodeGen/asan-globals.cpp > index a77060b124e9..2cea167d0ea5 100644 > --- a/clang/test/CodeGen/asan-globals.cpp > +++ b/clang/test/CodeGen/asan-globals.cpp > @@ -48,7 +48,7 @@ void func() { > // RUN: %clang_cc1 -emit-llvm -fsanitize=address -funwind-tables=2 -o - %s | FileCheck %s --check-prefixes=UWTABLE > // UWTABLE: define internal void @asan.module_dtor() #[[#ATTR:]] { > // UWTABLE: attributes #[[#ATTR]] = { nounwind uwtable } > -// UWTABLE: ![[#]] = !{i32 7, !"uwtable", i32 1} > +// UWTABLE: ![[#]] = !{i32 7, !"uwtable", i32 2} > > // CHECK: !llvm.asan.globals = !{![[EXTRA_GLOBAL:[0-9]+]], ![[GLOBAL:[0-9]+]], ![[DYN_INIT_GLOBAL:[0-9]+]], ![[ATTR_GLOBAL:[0-9]+]], ![[IGNORELISTED_GLOBAL:[0-9]+]], ![[SECTIONED_GLOBAL:[0-9]+]], ![[SPECIAL_GLOBAL:[0-9]+]], ![[STATIC_VAR:[0-9]+]], ![[LITERAL:[0-9]+]]} > // CHECK: ![[EXTRA_GLOBAL]] = !{{{.*}} ![[EXTRA_GLOBAL_LOC:[0-9]+]], !"extra_global", i1 false, i1 false} > diff --git a/clang/test/CodeGen/uwtable-attr.c b/clang/test/CodeGen/uwtable-attr.c > new file mode 100644 > index 000000000000..7436db979b6b > --- /dev/null > +++ b/clang/test/CodeGen/uwtable-attr.c > @@ -0,0 +1,30 @@ > +// Test that function and modules attributes react on the command-line options, > +// it does not state the current behaviour makes sense in all cases (it does not). > + > +// RUN: %clang -S -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,DEFAULT > +// RUN: %clang -S -emit-llvm -o - %s -funwind-tables -fno-asynchronous-unwind-tables | FileCheck %s -check-prefixes=CHECK,TABLES > +// RUN: %clang -S -emit-llvm -o - %s -fno-unwind-tables -fno-asynchronous-unwind-tables | FileCheck %s -check-prefixes=CHECK,NO_TABLES > + > +// RUN: %clang -S -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,DEFAULT > +// RUN: %clang -S -emit-llvm -o - -x c++ %s -funwind-tables -fno-asynchronous-unwind-tables | FileCheck %s -check-prefixes=CHECK,TABLES > +// RUN: %clang -S -emit-llvm -o - -x c++ %s -fno-exceptions -fno-unwind-tables -fno-asynchronous-unwind-tables | FileCheck %s -check-prefixes=CHECK,NO_TABLES > + > +#ifdef __cplusplus > +extern "C" void g(void); > +struct S { ~S(); }; > +extern "C" int f() { S s; g(); return 0;}; > +#else > +void g(void); > +int f() { g(); return 0; }; > +#endif > + > +// CHECK: define {{.*}} @f() #[[#F:]] > +// CHECK: declare {{.*}} @g() #[[#]] > + > +// DEFAULT: attributes #[[#F]] = { {{.*}} uwtable{{ }}{{.*}} } > +// DEFAULT: ![[#]] = !{i32 7, !"uwtable", i32 2} > + > +// TABLES: attributes #[[#F]] = { {{.*}} uwtable(sync){{.*}} } > +// TABLES: ![[#]] = !{i32 7, !"uwtable", i32 1} > + > +// NO_TABLES-NOT: uwtable > diff --git a/llvm/bindings/go/llvm/ir_test.go b/llvm/bindings/go/llvm/ir_test.go > index 71c47d94a0ec..61b482f2ef9a 100644 > --- a/llvm/bindings/go/llvm/ir_test.go > +++ b/llvm/bindings/go/llvm/ir_test.go > @@ -83,7 +83,6 @@ func TestAttributes(t *testing.T) { > "sspstrong", > "sanitize_thread", > "sanitize_memory", > - "uwtable", > "zeroext", > "cold", > "nocf_check", > diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst > index 6b44b7e7355c..1a212c661597 100644 > --- a/llvm/docs/LangRef.rst > +++ b/llvm/docs/LangRef.rst > @@ -2108,12 +2108,15 @@ example: > function with a tail call. The prototype of a thunk should not be used for > optimization purposes. The caller is expected to cast the thunk prototype to > match the thunk target prototype. > -``uwtable`` > +``uwtable[(sync|async)]`` > This attribute indicates that the ABI being targeted requires that > an unwind table entry be produced for this function even if we can > show that no exceptions passes by it. This is normally the case for > the ELF x86-64 abi, but it can be disabled for some compilation > - units. > + units. The optional parameter describes what kind of unwind tables > + to generate: ``sync`` for normal unwind tables, ``async`` for asynchronous > + (instruction precise) unwind tables. Without the parameter, the attribute > + ``uwtable`` is equivalent to ``uwtable(async)``. > ``nocf_check`` > This attribute indicates that no control-flow check will be performed on > the attributed entity. It disables -fcf-protection=<> for a specific > @@ -7215,8 +7218,9 @@ functions is small. > - "frame-pointer": **Max**. The value can be 0, 1, or 2. A synthesized function > will get the "frame-pointer" function attribute, with value being "none", > "non-leaf", or "all", respectively. > -- "uwtable": **Max**. The value can be 0 or 1. If the value is 1, a synthesized > - function will get the ``uwtable`` function attribute. > +- "uwtable": **Max**. The value can be 0, 1, or 2. If the value is 1, a synthesized > + function will get the ``uwtable(sync)`` function attribute, if the value is 2, > + a synthesized function will get the ``uwtable(async)`` function attribute. > > Objective-C Garbage Collection Module Flags Metadata > ---------------------------------------------------- > diff --git a/llvm/include/llvm/AsmParser/LLParser.h b/llvm/include/llvm/AsmParser/LLParser.h > index 62af3afbc142..b2f7b9ebb721 100644 > --- a/llvm/include/llvm/AsmParser/LLParser.h > +++ b/llvm/include/llvm/AsmParser/LLParser.h > @@ -263,6 +263,7 @@ namespace llvm { > bool parseOptionalAlignment(MaybeAlign &Alignment, > bool AllowParens = false); > bool parseOptionalDerefAttrBytes(lltok::Kind AttrKind, uint64_t &Bytes); > + bool parseOptionalUWTableKind(UWTableKind &Kind); > bool parseScopeAndOrdering(bool IsAtomic, SyncScope::ID &SSID, > AtomicOrdering &Ordering); > bool parseScope(SyncScope::ID &SSID); > diff --git a/llvm/include/llvm/AsmParser/LLToken.h b/llvm/include/llvm/AsmParser/LLToken.h > index 78ebb35e0ea4..faac67ebbab9 100644 > --- a/llvm/include/llvm/AsmParser/LLToken.h > +++ b/llvm/include/llvm/AsmParser/LLToken.h > @@ -252,6 +252,8 @@ enum Kind { > kw_immarg, > kw_byref, > kw_mustprogress, > + kw_sync, > + kw_async, > > kw_type, > kw_opaque, > diff --git a/llvm/include/llvm/IR/Attributes.h b/llvm/include/llvm/IR/Attributes.h > index 74b60f1e3d05..61819b1a07fa 100644 > --- a/llvm/include/llvm/IR/Attributes.h > +++ b/llvm/include/llvm/IR/Attributes.h > @@ -22,6 +22,7 @@ > #include "llvm/ADT/StringRef.h" > #include "llvm/Config/llvm-config.h" > #include "llvm/Support/Alignment.h" > +#include "llvm/Support/CodeGen.h" > #include "llvm/Support/PointerLikeTypeTraits.h" > #include <bitset> > #include <cassert> > @@ -130,6 +131,7 @@ public: > static Attribute getWithByRefType(LLVMContext &Context, Type *Ty); > static Attribute getWithPreallocatedType(LLVMContext &Context, Type *Ty); > static Attribute getWithInAllocaType(LLVMContext &Context, Type *Ty); > + static Attribute getWithUWTableKind(LLVMContext &Context, UWTableKind Kind); > > /// For a typed attribute, return the equivalent attribute with the type > /// changed to \p ReplacementTy. > @@ -223,6 +225,9 @@ public: > /// unknown. > Optional<unsigned> getVScaleRangeMax() const; > > + // Returns the unwind table kind. > + UWTableKind getUWTableKind() const; > + > /// The Attribute is converted to a string of equivalent mnemonic. This > /// is, presumably, for writing out the mnemonics for the assembly writer. > std::string getAsString(bool InAttrGrp = false) const; > @@ -353,6 +358,7 @@ public: > std::pair<unsigned, Optional<unsigned>> getAllocSizeArgs() const; > unsigned getVScaleRangeMin() const; > Optional<unsigned> getVScaleRangeMax() const; > + UWTableKind getUWTableKind() const; > std::string getAsString(bool InAttrGrp = false) const; > > /// Return true if this attribute set belongs to the LLVMContext. > @@ -841,6 +847,9 @@ public: > /// arg. > uint64_t getParamDereferenceableOrNullBytes(unsigned ArgNo) const; > > + /// Get the unwind table kind requested for the function. > + UWTableKind getUWTableKind() const; > + > /// Return the attributes at the index as a string. > std::string getAsString(unsigned Index, bool InAttrGrp = false) const; > > @@ -1190,6 +1199,10 @@ public: > /// Attribute.getIntValue(). > AttrBuilder &addVScaleRangeAttrFromRawRepr(uint64_t RawVScaleRangeRepr); > > + /// This turns the unwind table kind into the form used internally in > + /// Attribute. > + AttrBuilder &addUWTableAttr(UWTableKind Kind); > + > ArrayRef<Attribute> attrs() const { return Attrs; } > > bool operator==(const AttrBuilder &B) const; > diff --git a/llvm/include/llvm/IR/Attributes.td b/llvm/include/llvm/IR/Attributes.td > index a03e5441827c..d7a79f90e05e 100644 > --- a/llvm/include/llvm/IR/Attributes.td > +++ b/llvm/include/llvm/IR/Attributes.td > @@ -273,7 +273,7 @@ def SwiftSelf : EnumAttr<"swiftself", [ParamAttr]>; > def SwiftAsync : EnumAttr<"swiftasync", [ParamAttr]>; > > /// Function must be in a unwind table. > -def UWTable : EnumAttr<"uwtable", [FnAttr]>; > +def UWTable : IntAttr<"uwtable", [FnAttr]>; > > /// Minimum/Maximum vscale value for function. > def VScaleRange : IntAttr<"vscale_range", [FnAttr]>; > diff --git a/llvm/include/llvm/IR/Function.h b/llvm/include/llvm/IR/Function.h > index 90095cd1bc77..1b9843e08b28 100644 > --- a/llvm/include/llvm/IR/Function.h > +++ b/llvm/include/llvm/IR/Function.h > @@ -623,15 +623,19 @@ public: > bool willReturn() const { return hasFnAttribute(Attribute::WillReturn); } > void setWillReturn() { addFnAttr(Attribute::WillReturn); } > > + /// Get what kind of unwind table entry to generate for this function. > + UWTableKind getUWTableKind() const { > + return AttributeSets.getUWTableKind(); > + } > + > /// True if the ABI mandates (or the user requested) that this > /// function be in a unwind table. > bool hasUWTable() const { > - return hasFnAttribute(Attribute::UWTable); > + return getUWTableKind() != UWTableKind::None; > } > - void setHasUWTable() { > - addFnAttr(Attribute::UWTable); > + void setUWTableKind(UWTableKind K) { > + addFnAttr(Attribute::getWithUWTableKind(getContext(), K)); > } > - > /// True if this function needs an unwind table. > bool needsUnwindTableEntry() const { > return hasUWTable() || !doesNotThrow() || hasPersonalityFn(); > diff --git a/llvm/include/llvm/IR/Module.h b/llvm/include/llvm/IR/Module.h > index 9385ecab83d2..0414adfaee4d 100644 > --- a/llvm/include/llvm/IR/Module.h > +++ b/llvm/include/llvm/IR/Module.h > @@ -888,8 +888,8 @@ public: > void setRtLibUseGOT(); > > /// Get/set whether synthesized functions should get the uwtable attribute. > - bool getUwtable() const; > - void setUwtable(); > + UWTableKind getUwtable() const; > + void setUwtable(UWTableKind Kind); > > /// Get/set whether synthesized functions should get the "frame-pointer" > /// attribute. > diff --git a/llvm/include/llvm/Support/CodeGen.h b/llvm/include/llvm/Support/CodeGen.h > index ef5cc5d19fc5..71d0ddbfe05e 100644 > --- a/llvm/include/llvm/Support/CodeGen.h > +++ b/llvm/include/llvm/Support/CodeGen.h > @@ -97,6 +97,12 @@ namespace llvm { > }; > } // namespace ZeroCallUsedRegs > > -} // end llvm namespace > + enum class UWTableKind { > + None = 0, ///< No unwind table requested > + Sync = 1, ///< "Synchronous" unwind tables > + Async = 2, ///< "Asynchronous" unwind tables (instr precise) > + Default = 2, > + }; > + } // namespace llvm > > #endif > diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp > index e3bf41c9721b..a508660edfa5 100644 > --- a/llvm/lib/AsmParser/LLLexer.cpp > +++ b/llvm/lib/AsmParser/LLLexer.cpp > @@ -708,6 +708,8 @@ lltok::Kind LLLexer::LexIdentifier() { > KEYWORD(immarg); > KEYWORD(byref); > KEYWORD(mustprogress); > + KEYWORD(sync); > + KEYWORD(async); > > KEYWORD(type); > KEYWORD(opaque); > diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp > index 4281193caf85..769601c7e633 100644 > --- a/llvm/lib/AsmParser/LLParser.cpp > +++ b/llvm/lib/AsmParser/LLParser.cpp > @@ -1333,6 +1333,13 @@ bool LLParser::parseEnumAttribute(Attribute::AttrKind Attr, AttrBuilder &B, > B.addDereferenceableOrNullAttr(Bytes); > return false; > } > + case Attribute::UWTable: { > + UWTableKind Kind; > + if (parseOptionalUWTableKind(Kind)) > + return true; > + B.addUWTableAttr(Kind); > + return false; > + } > default: > B.addAttribute(Attr); > Lex.Lex(); > @@ -1996,6 +2003,22 @@ bool LLParser::parseOptionalDerefAttrBytes(lltok::Kind AttrKind, > return false; > } > > +bool LLParser::parseOptionalUWTableKind(UWTableKind &Kind) { > + Lex.Lex(); > + Kind = UWTableKind::Default; > + if (!EatIfPresent(lltok::lparen)) > + return false; > + LocTy KindLoc = Lex.getLoc(); > + if (Lex.getKind() == lltok::kw_sync) > + Kind = UWTableKind::Sync; > + else if (Lex.getKind() == lltok::kw_async) > + Kind = UWTableKind::Async; > + else > + return error(KindLoc, "expected unwind table kind"); > + Lex.Lex(); > + return parseToken(lltok::rparen, "expected ')'"); > +} > + > /// parseOptionalCommaAlign > /// ::= > /// ::= ',' align 4 > diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp > index 3d4b1f64b11c..5f6d980708a5 100644 > --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp > +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp > @@ -1628,6 +1628,8 @@ Error BitcodeReader::parseAttributeGroupBlock() { > B.addStructRetAttr(nullptr); > else if (Kind == Attribute::InAlloca) > B.addInAllocaAttr(nullptr); > + else if (Kind == Attribute::UWTable) > + B.addUWTableAttr(UWTableKind::Default); > else if (Attribute::isEnumAttrKind(Kind)) > B.addAttribute(Kind); > else > @@ -1650,6 +1652,8 @@ Error BitcodeReader::parseAttributeGroupBlock() { > B.addAllocSizeAttrFromRawRepr(Record[++i]); > else if (Kind == Attribute::VScaleRange) > B.addVScaleRangeAttrFromRawRepr(Record[++i]); > + else if (Kind == Attribute::UWTable) > + B.addUWTableAttr(UWTableKind(Record[++i])); > } else if (Record[i] == 3 || Record[i] == 4) { // String attribute > bool HasValue = (Record[i++] == 4); > SmallString<64> KindStr; > diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp > index 7783b5e0d3cc..d7d098278d2a 100644 > --- a/llvm/lib/CodeGen/MachineOutliner.cpp > +++ b/llvm/lib/CodeGen/MachineOutliner.cpp > @@ -623,6 +623,15 @@ MachineFunction *MachineOutliner::createOutlinedFunction( > > TII.mergeOutliningCandidateAttributes(*F, OF.Candidates); > > + // Set uwtable, so we generate eh_frame. > + UWTableKind UW = std::accumulate( > + OF.Candidates.cbegin(), OF.Candidates.cend(), UWTableKind::None, > + [](UWTableKind K, const outliner::Candidate &C) { > + return std::max(K, C.getMF()->getFunction().getUWTableKind()); > + }); > + if (UW != UWTableKind::None) > + F->setUWTableKind(UW); > + > BasicBlock *EntryBB = BasicBlock::Create(C, "entry", F); > IRBuilder<> Builder(EntryBB); > Builder.CreateRetVoid(); > diff --git a/llvm/lib/IR/AttributeImpl.h b/llvm/lib/IR/AttributeImpl.h > index 1153fb827b56..adf8a4d34a0a 100644 > --- a/llvm/lib/IR/AttributeImpl.h > +++ b/llvm/lib/IR/AttributeImpl.h > @@ -255,6 +255,7 @@ public: > std::pair<unsigned, Optional<unsigned>> getAllocSizeArgs() const; > unsigned getVScaleRangeMin() const; > Optional<unsigned> getVScaleRangeMax() const; > + UWTableKind getUWTableKind() const; > std::string getAsString(bool InAttrGrp) const; > Type *getAttributeType(Attribute::AttrKind Kind) const; > > diff --git a/llvm/lib/IR/Attributes.cpp b/llvm/lib/IR/Attributes.cpp > index 43fde64c3734..5751b99a2807 100644 > --- a/llvm/lib/IR/Attributes.cpp > +++ b/llvm/lib/IR/Attributes.cpp > @@ -205,6 +205,11 @@ Attribute Attribute::getWithInAllocaType(LLVMContext &Context, Type *Ty) { > return get(Context, InAlloca, Ty); > } > > +Attribute Attribute::getWithUWTableKind(LLVMContext &Context, > + UWTableKind Kind) { > + return get(Context, UWTable, uint64_t(Kind)); > +} > + > Attribute > Attribute::getWithAllocSizeArgs(LLVMContext &Context, unsigned ElemSizeArg, > const Optional<unsigned> &NumElemsArg) { > @@ -366,6 +371,12 @@ Optional<unsigned> Attribute::getVScaleRangeMax() const { > return unpackVScaleRangeArgs(pImpl->getValueAsInt()).second; > } > > +UWTableKind Attribute::getUWTableKind() const { > + assert(hasAttribute(Attribute::UWTable) && > + "Trying to get unwind table kind from non-uwtable attribute"); > + return UWTableKind(pImpl->getValueAsInt()); > +} > + > std::string Attribute::getAsString(bool InAttrGrp) const { > if (!pImpl) return {}; > > @@ -426,6 +437,25 @@ std::string Attribute::getAsString(bool InAttrGrp) const { > .str(); > } > > + if (hasAttribute(Attribute::UWTable)) { > + UWTableKind Kind = getUWTableKind(); > + if (Kind != UWTableKind::None) { > + return Kind == UWTableKind::Default > + ? "uwtable" > + : ("uwtable(" + > + Twine(Kind == UWTableKind::Sync ? "sync" : "async") + ")") > + .str(); > + } > + > + if (Kind != UWTableKind::None) { > + if (Kind == UWTableKind::Default) > + return "uwtable"; > + return ("uwtable(" + Twine(Kind == UWTableKind::Sync ? "sync" : "async") + > + ")") > + .str(); > + } > + } > + > // Convert target-dependent attributes to strings of the form: > // > // "kind" > @@ -710,6 +740,10 @@ Optional<unsigned> AttributeSet::getVScaleRangeMax() const { > return SetNode ? SetNode->getVScaleRangeMax() : None; > } > > +UWTableKind AttributeSet::getUWTableKind() const { > + return SetNode ? SetNode->getUWTableKind() : UWTableKind::None; > +} > + > std::string AttributeSet::getAsString(bool InAttrGrp) const { > return SetNode ? SetNode->getAsString(InAttrGrp) : ""; > } > @@ -876,6 +910,12 @@ Optional<unsigned> AttributeSetNode::getVScaleRangeMax() const { > return None; > } > > +UWTableKind AttributeSetNode::getUWTableKind() const { > + if (auto A = findEnumAttribute(Attribute::UWTable)) > + return A->getUWTableKind(); > + return UWTableKind::None; > +} > + > std::string AttributeSetNode::getAsString(bool InAttrGrp) const { > std::string Str; > for (iterator I = begin(), E = end(); I != E; ++I) { > @@ -1428,6 +1468,10 @@ AttributeList::getParamDereferenceableOrNullBytes(unsigned Index) const { > return getParamAttrs(Index).getDereferenceableOrNullBytes(); > } > > +UWTableKind AttributeList::getUWTableKind() const { > + return getFnAttrs().getUWTableKind(); > +} > + > std::string AttributeList::getAsString(unsigned Index, bool InAttrGrp) const { > return getAttributes(Index).getAsString(InAttrGrp); > } > @@ -1649,6 +1693,12 @@ AttrBuilder &AttrBuilder::addVScaleRangeAttrFromRawRepr(uint64_t RawArgs) { > return addRawIntAttr(Attribute::VScaleRange, RawArgs); > } > > +AttrBuilder &AttrBuilder::addUWTableAttr(UWTableKind Kind) { > + if (Kind == UWTableKind::None) > + return *this; > + return addRawIntAttr(Attribute::UWTable, uint64_t(Kind)); > +} > + > Type *AttrBuilder::getTypeAttr(Attribute::AttrKind Kind) const { > assert(Attribute::isTypeAttrKind(Kind) && "Not a type attribute"); > Attribute A = getAttribute(Kind); > diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp > index 726ba80da41b..6ae3d0b4dcb9 100644 > --- a/llvm/lib/IR/Function.cpp > +++ b/llvm/lib/IR/Function.cpp > @@ -339,8 +339,9 @@ Function *Function::createWithDefaultAttr(FunctionType *Ty, > Module *M) { > auto *F = new Function(Ty, Linkage, AddrSpace, N, M); > AttrBuilder B(F->getContext()); > - if (M->getUwtable()) > - B.addAttribute(Attribute::UWTable); > + UWTableKind UWTable = M->getUwtable(); > + if (UWTable != UWTableKind::None) > + B.addUWTableAttr(UWTable); > switch (M->getFramePointer()) { > case FramePointerKind::None: > // 0 ("none") is the default. > diff --git a/llvm/lib/IR/Module.cpp b/llvm/lib/IR/Module.cpp > index 6156edd99790..b66a99ba17b0 100644 > --- a/llvm/lib/IR/Module.cpp > +++ b/llvm/lib/IR/Module.cpp > @@ -671,12 +671,15 @@ void Module::setRtLibUseGOT() { > addModuleFlag(ModFlagBehavior::Max, "RtLibUseGOT", 1); > } > > -bool Module::getUwtable() const { > - auto *Val = cast_or_null<ConstantAsMetadata>(getModuleFlag("uwtable")); > - return Val && (cast<ConstantInt>(Val->getValue())->getZExtValue() > 0); > +UWTableKind Module::getUwtable() const { > + if (auto *Val = cast_or_null<ConstantAsMetadata>(getModuleFlag("uwtable"))) > + return UWTableKind(cast<ConstantInt>(Val->getValue())->getZExtValue()); > + return UWTableKind::None; > } > > -void Module::setUwtable() { addModuleFlag(ModFlagBehavior::Max, "uwtable", 1); } > +void Module::setUwtable(UWTableKind Kind) { > + addModuleFlag(ModFlagBehavior::Max, "uwtable", uint32_t(Kind)); > +} > > FramePointerKind Module::getFramePointer() const { > auto *Val = cast_or_null<ConstantAsMetadata>(getModuleFlag("frame-pointer")); > diff --git a/llvm/test/Assembler/uwtable-1.ll b/llvm/test/Assembler/uwtable-1.ll > new file mode 100644 > index 000000000000..2e9e3f0cab6d > --- /dev/null > +++ b/llvm/test/Assembler/uwtable-1.ll > @@ -0,0 +1,7 @@ > +; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s > + > +declare void @f0() uwtable > +declare void @f1() uwtable(sync) > +declare void @f2() uwtable(async) > +declare void @f3() uwtable(unsync) > +; CHECK: :[[#@LINE-1]]:28: error: expected unwind table kind > diff --git a/llvm/test/Assembler/uwtable-2.ll b/llvm/test/Assembler/uwtable-2.ll > new file mode 100644 > index 000000000000..c04228dbf157 > --- /dev/null > +++ b/llvm/test/Assembler/uwtable-2.ll > @@ -0,0 +1,4 @@ > +; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s > + > +declare void @f() uwtable(sync x > +; CHECK: :[[#@LINE-1]]:32: error: expected ')' > diff --git a/llvm/test/Bitcode/attributes.ll b/llvm/test/Bitcode/attributes.ll > index b2b92bb6e12d..5d3828d2762d 100644 > --- a/llvm/test/Bitcode/attributes.ll > +++ b/llvm/test/Bitcode/attributes.ll > @@ -516,6 +516,16 @@ define void @f83(<4 x i8*> align 32 %0, <vscale x 1 x double*> align 64 %1) { > ret void > } > > +; CHECK: define void @f84() #51 > +define void @f84() uwtable(sync) { > + ret void; > +} > + > +; CHECK: define void @f85() #15 > +define void @f85() uwtable(async) { > + ret void; > +} > + > ; CHECK: attributes #0 = { noreturn } > ; CHECK: attributes #1 = { nounwind } > ; CHECK: attributes #2 = { readnone } > @@ -567,4 +577,5 @@ define void @f83(<4 x i8*> align 32 %0, <vscale x 1 x double*> align 64 %1) { > ; CHECK: attributes #48 = { nosanitize_coverage } > ; CHECK: attributes #49 = { noprofile } > ; CHECK: attributes #50 = { disable_sanitizer_instrumentation } > +; CHECK: attributes #51 = { uwtable(sync) } > ; CHECK: attributes #[[NOBUILTIN]] = { nobuiltin } > diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll > index af761a4c37ec..84983411e86c 100644 > --- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll > +++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll > @@ -137,7 +137,9 @@ attributes #0 = { minsize nofree norecurse nounwind optsize uwtable} > ; UNWIND-NEXT: 0xB0 ; finish > > ; UNWIND-LABEL: FunctionAddress: 0x40 > -; UNWIND: Model: CantUnwind > +; UNWIND: Opcodes [ > +; UNWIND-NEXT: 0xB0 ; finish > + > > ; UNWINND-LABEL: 00000041 {{.*}} OUTLINED_FUNCTION_0 > ; UNWINND-LABEL: 00000001 {{.*}} x > diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll > index 9251e1b4ddf6..edbae593ee84 100644 > --- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll > +++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll > @@ -154,8 +154,9 @@ attributes #0 = { minsize noinline norecurse nounwind optsize readnone uwtable } > ; UNWIND-NEXT: 0xAA ; pop {r4, r5, r6, lr} > > ; UNWIND-LABEL: FunctionAddress: 0x5C > -; UNWIND: Model: CantUnwind > - > +; UNWIND: 0xB4 ; pop ra_auth_code > +; UNWIND: 0x84 0x00 ; pop {lr} > + > ; UNWIND-LABEL: 0000005d {{.*}} OUTLINED_FUNCTION_0 > ; UNWIND-LABEL: 00000005 {{.*}} f > ; UNWIND-LABEL: 00000031 {{.*}} g > diff --git a/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll b/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll > index ca3c6f3051f1..c046592890b4 100644 > --- a/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll > +++ b/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll > @@ -13,7 +13,7 @@ entry: > !llvm.module.flags = !{!0, !1} > > ;; Due to -fasynchronous-unwind-tables. > -!0 = !{i32 7, !"uwtable", i32 1} > +!0 = !{i32 7, !"uwtable", i32 2} > > ;; Due to -fno-omit-frame-pointer. > !1 = !{i32 7, !"frame-pointer", i32 2} > diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll > index b077dd388780..90437f5876d7 100644 > --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll > +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll > @@ -9,7 +9,7 @@ > target triple = "x86_64-unknown-linux-gnu" > > define internal fastcc void @no_promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly %arg1) #0 { > -; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS________OPM-LABEL: define {{[^@]+}}@no_promote_avx2 > ; IS________OPM-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] { > ; IS________OPM-NEXT: bb: > @@ -17,7 +17,7 @@ define internal fastcc void @no_promote_avx2(<4 x i64>* %arg, <4 x i64>* readonl > ; IS________OPM-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32 > ; IS________OPM-NEXT: ret void > ; > -; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS________NPM-LABEL: define {{[^@]+}}@no_promote_avx2 > ; IS________NPM-SAME: (<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] { > ; IS________NPM-NEXT: bb: > @@ -32,7 +32,7 @@ bb: > } > > define void @no_promote(<4 x i64>* %arg) #1 { > -; IS__TUNIT_OPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn > +; IS__TUNIT_OPM: Function Attrs: argmemonly nofree nosync nounwind willreturn uwtable > ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@no_promote > ; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { > ; IS__TUNIT_OPM-NEXT: bb: > @@ -45,7 +45,7 @@ define void @no_promote(<4 x i64>* %arg) #1 { > ; IS__TUNIT_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 > ; IS__TUNIT_OPM-NEXT: ret void > ; > -; IS__TUNIT_NPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn > +; IS__TUNIT_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn uwtable > ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@no_promote > ; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { > ; IS__TUNIT_NPM-NEXT: bb: > @@ -58,7 +58,7 @@ define void @no_promote(<4 x i64>* %arg) #1 { > ; IS__TUNIT_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 > ; IS__TUNIT_NPM-NEXT: ret void > ; > -; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn > +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind willreturn uwtable > ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@no_promote > ; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { > ; IS__CGSCC_OPM-NEXT: bb: > @@ -71,7 +71,7 @@ define void @no_promote(<4 x i64>* %arg) #1 { > ; IS__CGSCC_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 > ; IS__CGSCC_OPM-NEXT: ret void > ; > -; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn > +; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn uwtable > ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@no_promote > ; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { > ; IS__CGSCC_NPM-NEXT: bb: > @@ -96,7 +96,7 @@ bb: > } > > define internal fastcc void @promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly %arg1) #0 { > -; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS________OPM-LABEL: define {{[^@]+}}@promote_avx2 > ; IS________OPM-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[ARG1:%.*]]) #[[ATTR0]] { > ; IS________OPM-NEXT: bb: > @@ -104,7 +104,7 @@ define internal fastcc void @promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly % > ; IS________OPM-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32 > ; IS________OPM-NEXT: ret void > ; > -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@promote_avx2 > ; IS__TUNIT_NPM-SAME: (<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64> [[TMP0:%.*]]) #[[ATTR0]] { > ; IS__TUNIT_NPM-NEXT: bb: > @@ -114,7 +114,7 @@ define internal fastcc void @promote_avx2(<4 x i64>* %arg, <4 x i64>* readonly % > ; IS__TUNIT_NPM-NEXT: store <4 x i64> [[TMP]], <4 x i64>* [[ARG]], align 32 > ; IS__TUNIT_NPM-NEXT: ret void > ; > -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@promote_avx2 > ; IS__CGSCC_NPM-SAME: (<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[ARG:%.*]], <4 x i64> [[TMP0:%.*]]) #[[ATTR0]] { > ; IS__CGSCC_NPM-NEXT: bb: > @@ -131,7 +131,7 @@ bb: > } > > define void @promote(<4 x i64>* %arg) #0 { > -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@promote > ; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] { > ; IS__TUNIT_OPM-NEXT: bb: > @@ -144,7 +144,7 @@ define void @promote(<4 x i64>* %arg) #0 { > ; IS__TUNIT_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 > ; IS__TUNIT_OPM-NEXT: ret void > ; > -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@promote > ; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] { > ; IS__TUNIT_NPM-NEXT: bb: > @@ -158,7 +158,7 @@ define void @promote(<4 x i64>* %arg) #0 { > ; IS__TUNIT_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 > ; IS__TUNIT_NPM-NEXT: ret void > ; > -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@promote > ; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR0]] { > ; IS__CGSCC_OPM-NEXT: bb: > @@ -171,7 +171,7 @@ define void @promote(<4 x i64>* %arg) #0 { > ; IS__CGSCC_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 > ; IS__CGSCC_OPM-NEXT: ret void > ; > -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@promote > ; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR0]] { > ; IS__CGSCC_NPM-NEXT: bb: > @@ -203,14 +203,14 @@ attributes #0 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2 > attributes #1 = { nounwind uwtable } > attributes #2 = { argmemonly nounwind } > ;. > -; IS__TUNIT____: attributes #[[ATTR0:[0-9]+]] = { argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn "target-features"="+avx2" } > -; IS__TUNIT____: attributes #[[ATTR1:[0-9]+]] = { argmemonly nofree nosync nounwind uwtable willreturn } > +; IS__TUNIT____: attributes #[[ATTR0:[0-9]+]] = { argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable "target-features"="+avx2" } > +; IS__TUNIT____: attributes #[[ATTR1:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn uwtable } > ; IS__TUNIT____: attributes #[[ATTR2:[0-9]+]] = { argmemonly nofree nounwind willreturn writeonly } > ; IS__TUNIT____: attributes #[[ATTR3:[0-9]+]] = { willreturn writeonly } > ; IS__TUNIT____: attributes #[[ATTR4:[0-9]+]] = { nofree nosync nounwind willreturn } > ;. > -; IS__CGSCC____: attributes #[[ATTR0:[0-9]+]] = { argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn "target-features"="+avx2" } > -; IS__CGSCC____: attributes #[[ATTR1:[0-9]+]] = { argmemonly nofree nosync nounwind uwtable willreturn } > +; IS__CGSCC____: attributes #[[ATTR0:[0-9]+]] = { argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable "target-features"="+avx2" } > +; IS__CGSCC____: attributes #[[ATTR1:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn uwtable } > ; IS__CGSCC____: attributes #[[ATTR2:[0-9]+]] = { argmemonly nofree nounwind willreturn writeonly } > ; IS__CGSCC____: attributes #[[ATTR3:[0-9]+]] = { willreturn writeonly } > ; IS__CGSCC____: attributes #[[ATTR4:[0-9]+]] = { nosync nounwind willreturn } > diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll > index a7bcf1e42252..7a2b796cb321 100644 > --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll > +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll > @@ -11,7 +11,7 @@ target triple = "x86_64-unknown-linux-gnu" > ; This should promote > define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #0 { > ; > -; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512 > ; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] { > ; IS________OPM-NEXT: bb: > @@ -19,7 +19,7 @@ define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal5 > ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 > ; IS________OPM-NEXT: ret void > ; > -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512 > ; IS__TUNIT_NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { > ; IS__TUNIT_NPM-NEXT: bb: > @@ -29,7 +29,7 @@ define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal5 > ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 > ; IS__TUNIT_NPM-NEXT: ret void > ; > -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512 > ; IS__CGSCC_NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { > ; IS__CGSCC_NPM-NEXT: bb: > @@ -47,7 +47,7 @@ bb: > > define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* %arg) #0 { > ; > -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 > ; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] { > ; IS__TUNIT_OPM-NEXT: bb: > @@ -60,7 +60,7 @@ define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* > ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 > ; IS__TUNIT_OPM-NEXT: ret void > ; > -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 > ; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] { > ; IS__TUNIT_NPM-NEXT: bb: > @@ -74,7 +74,7 @@ define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* > ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 > ; IS__TUNIT_NPM-NEXT: ret void > ; > -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 > ; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR0]] { > ; IS__CGSCC_OPM-NEXT: bb: > @@ -87,7 +87,7 @@ define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* > ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 > ; IS__CGSCC_OPM-NEXT: ret void > ; > -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 > ; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR0]] { > ; IS__CGSCC_NPM-NEXT: bb: > @@ -115,7 +115,7 @@ bb: > ; This should promote > define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #1 { > ; > -; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256 > ; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) #[[ATTR1:[0-9]+]] { > ; IS________OPM-NEXT: bb: > @@ -123,7 +123,7 @@ define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal5 > ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 > ; IS________OPM-NEXT: ret void > ; > -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256 > ; IS__TUNIT_NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] { > ; IS__TUNIT_NPM-NEXT: bb: > @@ -133,7 +133,7 @@ define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal5 > ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 > ; IS__TUNIT_NPM-NEXT: ret void > ; > -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256 > ; IS__CGSCC_NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] { > ; IS__CGSCC_NPM-NEXT: bb: > @@ -151,7 +151,7 @@ bb: > > define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg) #1 { > ; > -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 > ; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1]] { > ; IS__TUNIT_OPM-NEXT: bb: > @@ -164,7 +164,7 @@ define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* > ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 > ; IS__TUNIT_OPM-NEXT: ret void > ; > -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 > ; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1]] { > ; IS__TUNIT_NPM-NEXT: bb: > @@ -178,7 +178,7 @@ define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* > ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 > ; IS__TUNIT_NPM-NEXT: ret void > ; > -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 > ; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR1]] { > ; IS__CGSCC_OPM-NEXT: bb: > @@ -191,7 +191,7 @@ define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* > ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 > ; IS__CGSCC_OPM-NEXT: ret void > ; > -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn > +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind willreturn uwtable > ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 > ; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR1]] { > ; IS__CGSCC_NPM-NEXT: bb: > @@ -219,7 +219,7 @@ bb: > ; This should promote > define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* %arg, <8 x i64>* readonly %arg1) #1 { > </cut>

3 years, 1 month

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Re: [TCWG CI] 401.bzip2 grew in size by 11% after llvm: [MachineSink] Disable if there are any irreducible cycles

by Maxim Kuvyrkov

Hi Nikita, Your patch seems to increase code-size of 401.bzip2 by 11% at -Oz. This is due to BZ2_decompress() function growing by 56%. Would you please investigate and see if this regression can be avoided? Please let us know if you need help reproducing or analyzing the problem. Regards, -- Maxim Kuvyrkov https://www.linaro.org > On Mar 27, 2022, at 11:26 AM, ci_notify(a)linaro.org wrote: > > After llvm commit 6fde0439512580df793f3f48f95757b47de40d2b > Author: Nikita Popov <npopov(a)redhat.com> > > [MachineSink] Disable if there are any irreducible cycles > > the following benchmarks grew in size by more than 1%: > - 401.bzip2 grew in size by 11% from 36213 to 40325 bytes > - 401.bzip2:[.] BZ2_decompress grew in size by 56% from 7400 to 11560 bytes > > Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI. > > For your convenience, we have uploaded tarballs with pre-processed source and assembly files at: > - First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > - Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > - Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > > Configuration: > - Benchmark: SPEC CPU2006 > - Toolchain: Clang + Glibc + LLVM Linker > - Version: all components were built from their tip of trunk > - Target: arm-linux-gnueabihf > - Compiler flags: -Oz -mthumb > - Hardware: APM Mustang 8x X-Gene1 > > This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports. > > THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. > > This commit has regressed these CI configurations: > - tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz > - tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz_LTO > > First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… > > Reproduce builds: > <cut> > mkdir investigate-llvm-6fde0439512580df793f3f48f95757b47de40d2b > cd investigate-llvm-6fde0439512580df793f3f48f95757b47de40d2b > > # Fetch scripts > git clone https://git.linaro.org/toolchain/jenkins-scripts > > # Fetch manifests and test.sh script > mkdir -p artifacts/manifests > curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail > curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail > curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail > chmod +x artifacts/test.sh > > # Reproduce the baseline build (build all pre-requisites) > ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh > > # Save baseline build state (which is then restored in artifacts/test.sh) > mkdir -p ./bisect > rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/ > > cd llvm > > # Reproduce first_bad build > git checkout --detach 6fde0439512580df793f3f48f95757b47de40d2b > ../artifacts/test.sh > > # Reproduce last_good build > git checkout --detach eb27da7dec67f1a36505b589b786ba1a499c274a > ../artifacts/test.sh > > cd .. > </cut> > > Full commit (up to 1000 lines): > <cut> > commit 6fde0439512580df793f3f48f95757b47de40d2b > Author: Nikita Popov <npopov(a)redhat.com> > Date: Thu Feb 24 10:09:49 2022 +0100 > > [MachineSink] Disable if there are any irreducible cycles > > This is an alternative to D120330, which disables MachineSink for > functions with irreducible cycles entirely. This avoids both the > correctness problem, and ensures we don't perform non-profitable > sinks into cycles. At the same time, it may also disable > profitable sinks in the same function. This can be made more > precise by using MachineCycleInfo in the future. > > Fixes https://github.com/llvm/llvm-project/issues/53990. > > Differential Revision: https://reviews.llvm.org/D120800 > --- > llvm/lib/CodeGen/MachineSink.cpp | 12 +++ > llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll | 22 +++-- > llvm/test/CodeGen/X86/pr38795.ll | 93 +++++++++++----------- > .../CodeGen/X86/pr53990-incorrect-machine-sink.ll | 9 +-- > llvm/test/CodeGen/X86/x86-shrink-wrapping.ll | 36 ++++----- > 5 files changed, 87 insertions(+), 85 deletions(-) > > diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp > index 7ed33f9fdeac..301cc73a0530 100644 > --- a/llvm/lib/CodeGen/MachineSink.cpp > +++ b/llvm/lib/CodeGen/MachineSink.cpp > @@ -18,12 +18,14 @@ > #include "llvm/ADT/DenseSet.h" > #include "llvm/ADT/MapVector.h" > #include "llvm/ADT/PointerIntPair.h" > +#include "llvm/ADT/PostOrderIterator.h" > #include "llvm/ADT/SetVector.h" > #include "llvm/ADT/SmallSet.h" > #include "llvm/ADT/SmallVector.h" > #include "llvm/ADT/SparseBitVector.h" > #include "llvm/ADT/Statistic.h" > #include "llvm/Analysis/AliasAnalysis.h" > +#include "llvm/Analysis/CFG.h" > #include "llvm/CodeGen/MachineBasicBlock.h" > #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" > #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" > @@ -429,6 +431,16 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { > AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); > RegClassInfo.runOnMachineFunction(MF); > > + // MachineSink currently uses MachineLoopInfo, which only recognizes natural > + // loops. As such, we could sink instructions into irreducible cycles, which > + // would be non-profitable. > + // WARNING: The current implementation of hasStoreBetween() is incorrect for > + // sinking into irreducible cycles (PR53990), this bailout is currently > + // necessary for correctness, not just profitability. > + ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin()); > + if (containsIrreducibleCFG<MachineBasicBlock *>(RPOT, *LI)) > + return false; > + > bool EverMadeChange = false; > > while (true) { > diff --git a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll > index 024b6c608aba..f93e181d157c 100644 > --- a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll > +++ b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll > @@ -24,7 +24,7 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind { > ; CHECK-NEXT: movq %r15, %rdi > ; CHECK-NEXT: callq l > ; CHECK-NEXT: testl %eax, %eax > -; CHECK-NEXT: jne .LBB0_10 > +; CHECK-NEXT: jne .LBB0_9 > ; CHECK-NEXT: # %bb.1: # %if.end > ; CHECK-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill > ; CHECK-NEXT: cmpl $0, e(%rip) > @@ -44,21 +44,19 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind { > ; CHECK-NEXT: callq i > ; CHECK-NEXT: movl %eax, %ebp > ; CHECK-NEXT: orl %r14d, %ebp > -; CHECK-NEXT: testl %r13d, %r13d > -; CHECK-NEXT: je .LBB0_6 > -; CHECK-NEXT: # %bb.5: > ; CHECK-NEXT: andl $4, %ebx > -; CHECK-NEXT: jmp .LBB0_3 > -; CHECK-NEXT: .LBB0_6: # %if.end12 > +; CHECK-NEXT: testl %r13d, %r13d > +; CHECK-NEXT: jne .LBB0_3 > +; CHECK-NEXT: # %bb.5: # %if.end12 > ; CHECK-NEXT: testl %ebp, %ebp > -; CHECK-NEXT: je .LBB0_9 > -; CHECK-NEXT: # %bb.7: # %if.then14 > +; CHECK-NEXT: je .LBB0_8 > +; CHECK-NEXT: # %bb.6: # %if.then14 > ; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload > ; CHECK-NEXT: #APP > ; CHECK-NEXT: #NO_APP > -; CHECK-NEXT: jmp .LBB0_10 > +; CHECK-NEXT: jmp .LBB0_9 > ; CHECK-NEXT: .Ltmp0: # Block address taken > -; CHECK-NEXT: # %bb.8: # %if.then20.critedge > +; CHECK-NEXT: # %bb.7: # %if.then20.critedge > ; CHECK-NEXT: movl j(%rip), %edi > ; CHECK-NEXT: movslq %eax, %rcx > ; CHECK-NEXT: movl $1, %esi > @@ -71,9 +69,9 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind { > ; CHECK-NEXT: popq %r15 > ; CHECK-NEXT: popq %rbp > ; CHECK-NEXT: jmp k # TAILCALL > -; CHECK-NEXT: .LBB0_9: # %if.else > +; CHECK-NEXT: .LBB0_8: # %if.else > ; CHECK-NEXT: incq 0 > -; CHECK-NEXT: .LBB0_10: # %cleanup > +; CHECK-NEXT: .LBB0_9: # %cleanup > ; CHECK-NEXT: addq $8, %rsp > ; CHECK-NEXT: popq %rbx > ; CHECK-NEXT: popq %r12 > diff --git a/llvm/test/CodeGen/X86/pr38795.ll b/llvm/test/CodeGen/X86/pr38795.ll > index d805dcad8b6e..b526e4f471b1 100644 > --- a/llvm/test/CodeGen/X86/pr38795.ll > +++ b/llvm/test/CodeGen/X86/pr38795.ll > @@ -32,13 +32,14 @@ define dso_local void @fn() { > ; CHECK-NEXT: # implicit-def: $ebp > ; CHECK-NEXT: jmp .LBB0_1 > ; CHECK-NEXT: .p2align 4, 0x90 > -; CHECK-NEXT: .LBB0_16: # %for.inc > +; CHECK-NEXT: .LBB0_15: # %for.inc > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > +; CHECK-NEXT: movl %esi, %ecx > ; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill > ; CHECK-NEXT: movb %dh, %dl > ; CHECK-NEXT: .LBB0_1: # %for.cond > ; CHECK-NEXT: # =>This Loop Header: Depth=1 > -; CHECK-NEXT: # Child Loop BB0_20 Depth 2 > +; CHECK-NEXT: # Child Loop BB0_19 Depth 2 > ; CHECK-NEXT: cmpb $8, %dl > ; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill > ; CHECK-NEXT: ja .LBB0_3 > @@ -55,7 +56,7 @@ define dso_local void @fn() { > ; CHECK-NEXT: movb %cl, %dh > ; CHECK-NEXT: movl $0, h > ; CHECK-NEXT: cmpb $8, %dl > -; CHECK-NEXT: jg .LBB0_8 > +; CHECK-NEXT: jg .LBB0_9 > ; CHECK-NEXT: # %bb.5: # %if.then13 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > ; CHECK-NEXT: movl %eax, %esi > @@ -64,12 +65,10 @@ define dso_local void @fn() { > ; CHECK-NEXT: calll printf > ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload > ; CHECK-NEXT: testb %bl, %bl > -; CHECK-NEXT: movl %esi, %ecx > ; CHECK-NEXT: # implicit-def: $eax > -; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload > -; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill > +; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload > ; CHECK-NEXT: movb %dh, %dl > -; CHECK-NEXT: jne .LBB0_16 > +; CHECK-NEXT: jne .LBB0_15 > ; CHECK-NEXT: jmp .LBB0_6 > ; CHECK-NEXT: .p2align 4, 0x90 > ; CHECK-NEXT: .LBB0_3: # %if.then > @@ -78,82 +77,82 @@ define dso_local void @fn() { > ; CHECK-NEXT: calll printf > ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload > ; CHECK-NEXT: # implicit-def: $eax > +; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload > +; CHECK-NEXT: jmp .LBB0_6 > +; CHECK-NEXT: .p2align 4, 0x90 > +; CHECK-NEXT: .LBB0_9: # %if.end21 > +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > +; CHECK-NEXT: # implicit-def: $ebp > +; CHECK-NEXT: jmp .LBB0_10 > +; CHECK-NEXT: .p2align 4, 0x90 > ; CHECK-NEXT: .LBB0_6: # %for.cond35 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > +; CHECK-NEXT: movb %dl, %dh > ; CHECK-NEXT: testl %edi, %edi > -; CHECK-NEXT: je .LBB0_7 > -; CHECK-NEXT: .LBB0_11: # %af > +; CHECK-NEXT: movl %edi, %esi > +; CHECK-NEXT: movl $0, %edi > +; CHECK-NEXT: movb %cl, %dl > +; CHECK-NEXT: je .LBB0_19 > +; CHECK-NEXT: # %bb.7: # %af > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > ; CHECK-NEXT: testb %bl, %bl > -; CHECK-NEXT: jne .LBB0_12 > -; CHECK-NEXT: .LBB0_17: # %if.end39 > +; CHECK-NEXT: jne .LBB0_8 > +; CHECK-NEXT: .LBB0_16: # %if.end39 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > ; CHECK-NEXT: testl %eax, %eax > -; CHECK-NEXT: je .LBB0_19 > -; CHECK-NEXT: # %bb.18: # %if.then41 > +; CHECK-NEXT: je .LBB0_18 > +; CHECK-NEXT: # %bb.17: # %if.then41 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) > ; CHECK-NEXT: movl $fn, {{[0-9]+}}(%esp) > ; CHECK-NEXT: movl $.str, (%esp) > ; CHECK-NEXT: calll printf > -; CHECK-NEXT: .LBB0_19: # %for.end46 > +; CHECK-NEXT: .LBB0_18: # %for.end46 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > +; CHECK-NEXT: movl %esi, %edi > ; CHECK-NEXT: # implicit-def: $dl > ; CHECK-NEXT: # implicit-def: $dh > ; CHECK-NEXT: # implicit-def: $ebp > -; CHECK-NEXT: jmp .LBB0_20 > -; CHECK-NEXT: .p2align 4, 0x90 > -; CHECK-NEXT: .LBB0_8: # %if.end21 > -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > -; CHECK-NEXT: # implicit-def: $ebp > -; CHECK-NEXT: jmp .LBB0_9 > ; CHECK-NEXT: .p2align 4, 0x90 > -; CHECK-NEXT: .LBB0_7: # in Loop: Header=BB0_1 Depth=1 > -; CHECK-NEXT: xorl %edi, %edi > -; CHECK-NEXT: movb %dl, %dh > -; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload > -; CHECK-NEXT: .p2align 4, 0x90 > -; CHECK-NEXT: .LBB0_20: # %for.cond47 > +; CHECK-NEXT: .LBB0_19: # %for.cond47 > ; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 > ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 > ; CHECK-NEXT: testb %bl, %bl > -; CHECK-NEXT: jne .LBB0_20 > -; CHECK-NEXT: # %bb.21: # %for.cond47 > -; CHECK-NEXT: # in Loop: Header=BB0_20 Depth=2 > +; CHECK-NEXT: jne .LBB0_19 > +; CHECK-NEXT: # %bb.20: # %for.cond47 > +; CHECK-NEXT: # in Loop: Header=BB0_19 Depth=2 > ; CHECK-NEXT: testb %bl, %bl > -; CHECK-NEXT: jne .LBB0_20 > -; CHECK-NEXT: .LBB0_9: # %ae > +; CHECK-NEXT: jne .LBB0_19 > +; CHECK-NEXT: .LBB0_10: # %ae > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > ; CHECK-NEXT: testb %bl, %bl > -; CHECK-NEXT: jne .LBB0_10 > -; CHECK-NEXT: # %bb.13: # %if.end26 > +; CHECK-NEXT: jne .LBB0_11 > +; CHECK-NEXT: # %bb.12: # %if.end26 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > -; CHECK-NEXT: xorl %ecx, %ecx > +; CHECK-NEXT: xorl %esi, %esi > ; CHECK-NEXT: testb %dl, %dl > -; CHECK-NEXT: je .LBB0_16 > -; CHECK-NEXT: # %bb.14: # %if.end26 > +; CHECK-NEXT: je .LBB0_15 > +; CHECK-NEXT: # %bb.13: # %if.end26 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > ; CHECK-NEXT: testl %ebp, %ebp > -; CHECK-NEXT: jne .LBB0_16 > -; CHECK-NEXT: # %bb.15: # %if.then31 > +; CHECK-NEXT: jne .LBB0_15 > +; CHECK-NEXT: # %bb.14: # %if.then31 > ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 > -; CHECK-NEXT: xorl %ecx, %ecx > +; CHECK-NEXT: xorl %esi, %esi > ; CHECK-NEXT: xorl %ebp, %ebp > -; CHECK-NEXT: jmp .LBB0_16 > +; CHECK-NEXT: jmp .LBB0_15 > ; CHECK-NEXT: .p2align 4, 0x90 > -; CHECK-NEXT: .LBB0_10: # in Loop: Header=BB0_1 Depth=1 > +; CHECK-NEXT: .LBB0_11: # in Loop: Header=BB0_1 Depth=1 > +; CHECK-NEXT: movl %edi, %esi > ; CHECK-NEXT: # implicit-def: $eax > ; CHECK-NEXT: testb %bl, %bl > -; CHECK-NEXT: je .LBB0_17 > -; CHECK-NEXT: .LBB0_12: # in Loop: Header=BB0_1 Depth=1 > +; CHECK-NEXT: je .LBB0_16 > +; CHECK-NEXT: .LBB0_8: # in Loop: Header=BB0_1 Depth=1 > ; CHECK-NEXT: # implicit-def: $edi > ; CHECK-NEXT: # implicit-def: $cl > -; CHECK-NEXT: # kill: killed $cl > ; CHECK-NEXT: # implicit-def: $dl > ; CHECK-NEXT: # implicit-def: $ebp > -; CHECK-NEXT: testl %edi, %edi > -; CHECK-NEXT: jne .LBB0_11 > -; CHECK-NEXT: jmp .LBB0_7 > +; CHECK-NEXT: jmp .LBB0_6 > entry: > br label %for.cond > > diff --git a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll > index 3d7ff6cbe676..4f56d7b16a87 100644 > --- a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll > +++ b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll > @@ -7,18 +7,15 @@ define void @test(i1 %c, i64* %p, i64* noalias %p2) nounwind { > ; CHECK-LABEL: test: > ; CHECK: # %bb.0: # %entry > ; CHECK-NEXT: pushq %rbp > -; CHECK-NEXT: pushq %r15 > ; CHECK-NEXT: pushq %r14 > ; CHECK-NEXT: pushq %rbx > -; CHECK-NEXT: pushq %rax > ; CHECK-NEXT: movq %rdx, %rbx > -; CHECK-NEXT: movq %rsi, %r14 > -; CHECK-NEXT: movl %edi, %r15d > +; CHECK-NEXT: movl %edi, %r14d > +; CHECK-NEXT: movq (%rsi), %rbp > ; CHECK-NEXT: xorl %eax, %eax > ; CHECK-NEXT: jmpq *.LJTI0_0(,%rax,8) > ; CHECK-NEXT: .LBB0_1: # %split.3 > -; CHECK-NEXT: movq (%r14), %rbp > -; CHECK-NEXT: testb $1, %r15b > +; CHECK-NEXT: testb $1, %r14b > ; CHECK-NEXT: je .LBB0_3 > ; CHECK-NEXT: # %bb.2: # %clobber > ; CHECK-NEXT: callq clobber@PLT > diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll > index 0f8bb837f82a..b44895293b41 100644 > --- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll > +++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll > @@ -1377,6 +1377,8 @@ define i32 @irreducibleCFG() #4 { > ; ENABLE-NEXT: pushq %rbx > ; ENABLE-NEXT: pushq %rax > ; ENABLE-NEXT: .cfi_offset %rbx, -24 > +; ENABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax > +; ENABLE-NEXT: movl (%rax), %edi > ; ENABLE-NEXT: movq _irreducibleCFGf@GOTPCREL(%rip), %rax > ; ENABLE-NEXT: cmpb $0, (%rax) > ; ENABLE-NEXT: je LBB16_2 > @@ -1386,24 +1388,20 @@ define i32 @irreducibleCFG() #4 { > ; ENABLE-NEXT: jmp LBB16_1 > ; ENABLE-NEXT: LBB16_2: ## %split > ; ENABLE-NEXT: movq _irreducibleCFGb@GOTPCREL(%rip), %rax > +; ENABLE-NEXT: xorl %ebx, %ebx > ; ENABLE-NEXT: cmpl $0, (%rax) > -; ENABLE-NEXT: je LBB16_3 > -; ENABLE-NEXT: ## %bb.4: ## %for.body4.i > -; ENABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax > -; ENABLE-NEXT: movl (%rax), %edi > +; ENABLE-NEXT: je LBB16_4 > +; ENABLE-NEXT: ## %bb.3: ## %for.body4.i > ; ENABLE-NEXT: xorl %ebx, %ebx > ; ENABLE-NEXT: xorl %eax, %eax > ; ENABLE-NEXT: callq _something > -; ENABLE-NEXT: jmp LBB16_5 > -; ENABLE-NEXT: LBB16_3: > -; ENABLE-NEXT: xorl %ebx, %ebx > ; ENABLE-NEXT: .p2align 4, 0x90 > -; ENABLE-NEXT: LBB16_5: ## %for.inc > +; ENABLE-NEXT: LBB16_4: ## %for.inc > ; ENABLE-NEXT: ## =>This Inner Loop Header: Depth=1 > ; ENABLE-NEXT: incl %ebx > ; ENABLE-NEXT: cmpl $7, %ebx > -; ENABLE-NEXT: jl LBB16_5 > -; ENABLE-NEXT: ## %bb.6: ## %fn1.exit > +; ENABLE-NEXT: jl LBB16_4 > +; ENABLE-NEXT: ## %bb.5: ## %fn1.exit > ; ENABLE-NEXT: xorl %eax, %eax > ; ENABLE-NEXT: addq $8, %rsp > ; ENABLE-NEXT: popq %rbx > @@ -1420,6 +1418,8 @@ define i32 @irreducibleCFG() #4 { > ; DISABLE-NEXT: pushq %rbx > ; DISABLE-NEXT: pushq %rax > ; DISABLE-NEXT: .cfi_offset %rbx, -24 > +; DISABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax > +; DISABLE-NEXT: movl (%rax), %edi > ; DISABLE-NEXT: movq _irreducibleCFGf@GOTPCREL(%rip), %rax > ; DISABLE-NEXT: cmpb $0, (%rax) > ; DISABLE-NEXT: je LBB16_2 > @@ -1429,24 +1429,20 @@ define i32 @irreducibleCFG() #4 { > ; DISABLE-NEXT: jmp LBB16_1 > ; DISABLE-NEXT: LBB16_2: ## %split > ; DISABLE-NEXT: movq _irreducibleCFGb@GOTPCREL(%rip), %rax > +; DISABLE-NEXT: xorl %ebx, %ebx > ; DISABLE-NEXT: cmpl $0, (%rax) > -; DISABLE-NEXT: je LBB16_3 > -; DISABLE-NEXT: ## %bb.4: ## %for.body4.i > -; DISABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax > -; DISABLE-NEXT: movl (%rax), %edi > +; DISABLE-NEXT: je LBB16_4 > +; DISABLE-NEXT: ## %bb.3: ## %for.body4.i > ; DISABLE-NEXT: xorl %ebx, %ebx > ; DISABLE-NEXT: xorl %eax, %eax > ; DISABLE-NEXT: callq _something > -; DISABLE-NEXT: jmp LBB16_5 > -; DISABLE-NEXT: LBB16_3: > -; DISABLE-NEXT: xorl %ebx, %ebx > ; DISABLE-NEXT: .p2align 4, 0x90 > -; DISABLE-NEXT: LBB16_5: ## %for.inc > +; DISABLE-NEXT: LBB16_4: ## %for.inc > ; DISABLE-NEXT: ## =>This Inner Loop Header: Depth=1 > ; DISABLE-NEXT: incl %ebx > ; DISABLE-NEXT: cmpl $7, %ebx > -; DISABLE-NEXT: jl LBB16_5 > -; DISABLE-NEXT: ## %bb.6: ## %fn1.exit > +; DISABLE-NEXT: jl LBB16_4 > +; DISABLE-NEXT: ## %bb.5: ## %fn1.exit > ; DISABLE-NEXT: xorl %eax, %eax > ; DISABLE-NEXT: addq $8, %rsp > ; DISABLE-NEXT: popq %rbx > </cut>

3 years, 1 month

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[ACTIVITY] Report for week #12

by Thiago Jung Bauermann

Hello, # [GNU-732] GDB support for ARMv9 Scalable Matrix Extension (SME) * Continued working on gdbserver and remote protocol support for programs that change the SVE vector length during execution: - Studied the 2020 discussion around Luis' proposal to support changed VL size in the Remote Serial Protocol / gdbserver, as well as relevant parts of the RSP itself. - Started studying GDB's type system and how it handles dynamic types, and also the target description code to assess the feasibility of making the vector registers use a dynamically sized type. - Luis made a second proposal in that mailing list discussion where the target description wouldn't be transferred via the remote protocol, just the vector length. Then both GDB and gdbserver could locally update their own descriptions based on that. Starting to think about this alternative. It would probably be simpler than changing the target description to use a dynamically sized type for the Z registers. # Basic setup / onboarding * Work laptop arrived. Set it up. -- Thiago

3 years, 1 month

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[ACTIVITY] week ending Mar. 27 2022

by Alex Bennée

Project Stratos =============== - spent some time talking through design approaches for xen vhost-master with Viresh - posted Re: Understanding osdep_xenforeignmemory_map mmap behaviour Message-Id: <alpine.DEB.2.22.394.2203231838130.2910984@ubuntu-linux-20-04-desktop> Linux RPMB Sub-system and virtio-driver ([STR-40]) - continued working on [Linux driver] - discovered a bug in vhost-user config handling in QEMU as well - posted [PATCH v1 00/13] various virtio docs, fixes and tweaks Message-Id: <20220321153037.3622127-1-alex.bennee(a)linaro.org> [STR-40] <https://linaro.atlassian.net/browse/STR-40> [Linux driver] <http://git.linaro.org/people/alex.bennee/linux.git/shortlog/refs/heads/rpmb…> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/18] testing and semihosting updates Message-Id: <20220301094715.550871-1-alex.bennee(a)linaro.org> - posted [PULL for 7.0 0/8] i386, docs, gitlab fixes Message-Id: <20220323112711.440376-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Other ===== - Finished work on presentation for LTD Completed Reviews [11/11] ========================= [PATCH] gdbstub.c: add support for info proc mappings Message-Id: <20220221030910.3203063-1-dominik.b.czarnota(a)gmail.com> [PATCH] tests/Makefile.include: Let "make clean" remove the TCG tests, too Message-Id: <20220301085900.1443232-1-thuth(a)redhat.com> [PATCH 0/3] gdbstub: add support for switchable endianness Message-Id: <20210823142004.17935-1-changbin.du(a)gmail.com> [PATCH 0/6] More record/replay acceptance tests Message-Id: <162332427732.194926.7555369160312506539.stgit@pasha-ThinkPad-X280> [PATCH v6 00/43] CXl 2.0 emulation Support Message-Id: <20220211120747.3074-1-Jonathan.Cameron(a)huawei.com> [PATCH 00/11] edk2: update to stable202202 Message-Id: <20220308145521.3106395-1-kraxel(a)redhat.com> [PATCH 0/3] Use g_new() & friends where that makes obvious Message-Id: <20220314160108.1440470-3-armbru(a)redhat.com> [PATCH 2/2] target/arm: Log fault address for M-profile faults Message-Id: <20220315204306.2797684-3-peter.maydell(a)linaro.org> [RFC PATCH 0/6] Port PPC64/PowerNV MMU tests to QEMU Message-Id: <20220324190854.156898-1-leandro.lupori(a)eldorado.org.br> [PULL for-7.1 00/36] Logging cleanup and per-thread logfiles Message-Id: <20220320171135.2704502-1-richard.henderson(a)linaro.org> [PATCH 1/2] gdbstub: Set current_cpu for memory read write Message-Id: <20220322154213.86475-1-bmeng.cn(a)gmail.com> Absences ======== Current Review Queue ==================== TODO [PULL for-7.1 00/36] Logging cleanup and per-thread logfiles Message-Id: <20220320171135.2704502-1-richard.henderson(a)linaro.org> ==================================================================================================================================== TODO [PATCH 00/11] edk2: update to stable202202 Message-Id: <20220308145521.3106395-1-kraxel(a)redhat.com> ======================================================================================================= TODO [RFC PATCH 00/27] Virtio sound card implementation Message-Id: <20210429120445.694420-1-chouhan.shreyansh2702(a)gmail.com> ============================================================================================================================ -- Alex Bennée

3 years, 1 month

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[ACTIVITY] report week ending 25 Mar

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] + More of the usual freeze-related work * QEMU-420 [GICv4 emulation] + I think the code is more or less bug-free now; still need to figure out the best way for a board to request a GICv4 (eg do we want a 'revision' property specifying 3, 3.1, 4, 4.1, or just 3 vs 4 with some optional booleans for extra features?) -- PMM

3 years, 1 month

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[ACTIVITY] Report for week #11

by Thiago Jung Bauermann

Hello, # [GNU-732] GDB support for ARMv9 Scalable Matrix Extension (SME) * Continued reading patches from Mark Brown's v12 patch set adding SME support to the Linux kernel. Sent a few trivial review comments. * After conversation with Luis, decided to work on gdbserver and remote protocol support for programs which change the SVE vector length during execution (native GDB already supports it). This issue will most likely be relevant for SME as well. Started by studying Luis' proposal from 2020 and background information provided by him. # Basic setup / onboarding * Bought a work laptop. * Set up access to the team's machines. -- Thiago

3 years, 1 month

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[ACTIVITY] report week ending 18 Mar

by Peter Maydell

Progress (for a week-and-a-half) * UM-2 [QEMU upstream maintainership] + Lots of freeze-related work (softfreeze was last week and we tagged rc0 this week) + Code review of other peoples's stuff to go into the release + Assembling arm pullreqs + Investigating an intermittent failure in one of our test cases on s390 host, which seems like it may be a bug in the s390 h/w-accelerated zlib * QEMU-420 [GICv4 emulation] + Still debugging... -- PMM

3 years, 1 month

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Interest in reproducing gcc-linaro-4.9-2016.02 arm-linux-gnueabihf target under darwin and linux aarch64 host

by jhgorse＠gmail.com

Hello, I see this release gcc-linaro-4.9-2016.02 for 86_64_arm-linux-gnueabihf: https://releases.linaro.org/components/toolchain/binaries/4.9-2016.02/arm-l… and would like to reproduce the toolchain for aarch64 hosts. I see that it was built with ABE, though I have generally been unsuccessful in getting ABE to work on aarch64 for this. I was looking for some build or ci breadcrumbs or documentation. What can you recommend? The motivation here is to support legacy development/testing from modern aarch64 hardware. Cheers, Joe Gorse

3 years, 1 month

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[Activity] Week #10

by Thiago Jung Bauermann

Hello, # GDB support for ARMv9 Scalable Matrix Extension (SME) - Synced with Luis Machado to learn what the current status is. Read discussions in the linux-arm-kernel mailing list which he pointed to. - Read Arm architecture documentation about Neon, SVE, SVE2 and SME to familiarise myself with these features. - Basic setup / onboarding - Joined some internal and external mailing lists, IRC and Slack channels. - Read some company policy documents. - Researched models and got a quote for a work laptop. - Set up aarch64 cross-compilation environment on my laptop. - Set up emulated aarch64 machine with Fedora on my laptop. - Attempted setting up emulated aarch64 machine with Ubuntu on my laptop, but ran into problems with the Ubuntu Server installer. -- Thiago

3 years, 2 months

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