Progress:
* UM-2 [QEMU upstream maintainership]
- sent out patch which adds a retry-on-EINTR loop to KVM_CREATE_VM ioctls
- wrote up the draft of the minutes for the QEMU Summit for review
- more code review and pullrequest collation (notably the Arm v8R support
patchset)
* QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG]
- read up on the remaining unimplemented features under this epic;
closed out one we'd already implemented, and wrote up enough detail
on the others to be happy with putting them all into the current
sprint (they're all small features)
- started looking at FEAT_GTG
thanks
-- PMM
Project Stratos
===============
- held poll for next meeting
- started planning for virtio-camera/sensor
QEMU Upstream Work ([UM-2])
===========================
- posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id:
<CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com>
- sadly one patch had to be reverted as it exposed another race
- posted [PATCH v1 00/10] plugins/next (disas, monitor, docs, execlog)
Message-Id: <20220921160801.1490125-6-alex.bennee(a)linaro.org>
- posted [PULL 00/30] testing updates (docker, avocado, deprecate
32bit BE MIPS) Message-Id:
<20220920171533.1098094-4-alex.bennee(a)linaro.org>
[UM-2] <https://linaro.atlassian.net/browse/UM-2>
Update docs
- mention -d plugin
- document features of tests/plugin plugins
- clean up command lines to drop builddir
KVM Forum
=========
- Attended KVM forum, gave a talk, helper with another
Completed Reviews [3/3]
=======================
[PATCH 00/62] target/arm: Implement FEAT_HAFDBS
Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org>
[RFC PATCH v2] gdbstub: only send stop-reply packets when allowed to
Message-Id: <ba99db564c3aeb1812bdfbc9116849092334482f.1661362557.git.quic_mathbern(a)quicinc.com>
[RFC 0/4] Support interactions between TCG plugins
Message-Id: <20220901182734.2987337-1-fasano(a)mit.edu>
Absences
========
Current Review Queue
====================
TODO [PATCH v4 0/7] tcg: pc-relative translation blocks
Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org>
=========================================================================================================================
TODO [PATCH 00/51] tests/qtest: Enable running qtest on Windows
Message-Id: <20220824094029.1634519-1-bmeng.cn(a)gmail.com>
========================================================================================================================
TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation
Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org>
=======================================================================================================================================
--
Alex Bennée
Progress:
* UM-2 [QEMU upstream maintainership]
- attended KVM Forum
- catching up with code review, email, etc...
- sent out an Arm pullreq now 7.2 has opened up for development
* QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG]
- diagnosed a regression caused by the recent FEAT_PMUv3p5 changes
and sent out a fix
KVM Forum trip highlights:
* it was good to be able to meet people face-to-face again after
several years
* Cloud use of Arm hardware has now got to the point where big cloud
companies are working through performance issues and then coming to
present about it; e.g. Google did a talk about perf issues during
migration on an Ampere Altra setup. The solutions seem to be a mix
of "apply the lessons and fixes we already went through with x86"
and "architecture fixes coming down the pipe" (in this case
FEAT_TLBIRANGE and FEAT_BBM).
* lots of Google talks about pKVM (using hypervisor hardware on
Android to improve security). In fact lots of Google all over --
apparently they've made a big push to do more upstream kernel work
and as a result a large chunk of the kernel KVM commits come from
them...
* talk from Xilinx (now with AMD) about doing co-simulation of QEMU
and RTL -- basically (with the aid of a lot of non-upstream stuff)
having QEMU talk to a SystemC environment so you can have eg an
emulated ethernet card in FPGA that plugs into a QEMU VM. This kind
of thing is a use-case which historically upstream have not really
been interested in addressing.
* Which brings me to the BoF session on emulation, perhaps the most
interesting bit of the conference for me. There was a lot of
discussion about whether QEMU might move closer to what I call the
"bag of lego bricks" paradigm, where it provides device models and
users might be able to configure it at runtime to stitch them
together, perhaps adding out-of-tree devices of their own. There is
clearly interest in this (eg from attendees from Xilinx and
Qualcomm); the sticking point is that from upstream's perspective
this seems like "you should do this thing that will benefit us and
not you". My take is that whether this goes anywhere will depend on
whether those who would like this are prepared to coordinate
together to present themselves as a group who are willing to dig in
to the necessary upstream refactoring and cleanup that would be a
precondition for having something like this be anywhere near
supportable, i.e. that they're a group who will come and help
rather than merely consume...
* There was also a shorter discussion in the BoF about the idea of
"heterogenous CPU emulation", eg one QEMU model with both Arm and
Microblaze CPUs. This is not conceptually controversial, it's just
a lot of work. It seemed like maybe a few folk now care enough to
have a go at it.
-- PMM
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Made a few last-minute adjustments to the code and fixed a couple of
regressions on x86_64-linux. Re-ran regression tests on x86_64-linux and
aarch64-linux. Wrote cover letter and descriptions for all the patches.
- Finally posted the patch series upstream¹.
# [GNU-796] Stabilize GDB testsuite results in the Linaro CI
- Started working on this issue. Currently adding a new CI job to run the
same small subset of GDB testcases that Sourceware's buildbot runs. This
subset runs quickly and has stable results so the job will be a good
canary to check that the CI infrastructure is working correctly.
--
Thiago
¹https://inbox.sourceware.org/gdb-patches/20220908064151.3959930-1-thiago.b…
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Cleaned up code for upstream submission, and divided it into patches.
A couple of the patches affect other architectures and OSes, so made
sure the code builds on as many combinations I can test, and now doing
final regression testing on some of them. I'm hoping to finally send
the patches upstream early next week.
--
Thiago
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Finished fixing regressions in my changes to gdbserver for debugging an
inferior which changes the SVE length.
- Started cleaning up code for upstream submission and dividing it into
patches.
# Community participation
- Reviewed mailing list patches:
- [PATCH,v3] [aarch64] Fix removal of non-address bits for PAuth
- [PATCH 1/2] gdb: Fix deleted thread when issuing next command
- [PATCH 2/2] gdb: Improve the resuming of the stepped thread
--
Thiago
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- pretty much just tying up loose ends and doing other
miscellaneous bits and pieces
* QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG]
- respin, resend of PMUv3p5 series
-- PMM
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- v2 of the patches fixing a small SVE bug when debugging in native mode
an inferior which changes the SVE length was committed upstream.
- Continued working on fixing regressions in my changes to gdbserver for
debugging an inferior which changes the SVE length.
--
Thiago
Project Stratos
===============
- continued working on [adding vhost-user-rng to crosvm]
- this is to demo Stratos on Gunyah
- re-built guest kernel with known working backend
- it works :-)
- initial review of Viresh's slides for KVM Forum talk
[adding vhost-user-rng to crosvm]
<https://github.com/stsquad/crosvm/tree/add-vhost-user-rng>
vhost-device maintainer effort ([UM-196])
- prepared a clean-up [branch for new queue interface]
- spent time testing and realised it had broken things
[branch for new queue interface]
<https://github.com/stsquad/vhost-device/tree/update-queue-interface>
QEMU Upstream Work ([UM-2])
===========================
- posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id:
<CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com>
- sadly one patch had to be reverted as it exposed another race
[UM-2] <https://linaro.atlassian.net/browse/UM-2>
Completed Reviews [1/1]
=======================
[PATCH 00/62] target/arm: Implement FEAT_HAFDBS
Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org>
Absences
========
- will take a long w/e for August BH
Current Review Queue
====================
TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation
Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org>
=======================================================================================================================================
TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes
Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org>
===========================================================================================================================================================================
--
Alex Bennée
Progress:
* UM-2 [QEMU upstream maintainership]
- respin and resend for a few patchsets after code review
* QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG]
- identified what the old ARMv8.5-CMODX feature is now
("prefetch speculation protection") and confirmed that
QEMU is already compliant with the instruction fetch ordering
requirements so there's no coding work required here
- Checked that we implement FEAT_ETS already and sent patches
to advertise it in the ID registers
- Checked that we already conform to the ordering rules required
by "prefetch speculation protection"
- Discovered that we accidentally fail to RAZ for a big chunk
of the reserved-for-new-AArch32-ID-registers space for v8 CPUs;
sent patches fixing that
thanks
-- PMM
Hello Linaro Toolchain Working Group,
clang-arm64-windows-msvc is red for 12 days. The host is missing a correct
version of msvc.
Is somebody looking at this?
Thanks
Galina
Progress:
* UM-2 [QEMU upstream maintainership]
- usual release cycle work: rounded up a couple of last-minute
fixes for "whoops, this crashes" bugs and some safe changes like
docs typo fixes.
* QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG]
- Finished implementing the FEAT_PMUv3p5 work. In the process of
testing it I found a handful of bugs in our existing PMU
emulation code. Sent out the patchset which fixes those bugs and
adds FEAT_PMUv3p5.
- Cleaned up the epic to remove subtasks we aren't going to
implement (FEAT_SPE, FEAT_TRF), and added one for "actually
define the new CPU model"
- FEAT_LSE2 is the only remaining real work here, and it is
probably going to be seriously tricky...(i.e. I hope to leave
it to RTH ;-))
-- PMM
Project Stratos
===============
- continued working on [adding vhost-user-rng to crosvm]
- this is to demo Stratos on Gunyah
- backend comes up and device is detected but queues are not
consumed
- had some initial discussions with Viresh about talk structure for
KVM Forum
[adding vhost-user-rng to crosvm]
<https://github.com/stsquad/crosvm/tree/add-vhost-user-rng>
vhost-device maintainer effort ([UM-196])
- prepared a clean-up [branch for new queue interface]
[UM-196] <https://linaro.atlassian.net/browse/UM-196>
[branch for new queue interface]
<https://github.com/stsquad/vhost-device/tree/update-queue-interface>
QEMU Upstream Work ([UM-2])
===========================
- posted [PATCH for 7.1 v1 0/8] memory leaks and speed tweaks
Message-Id: <20220811151413.3350684-8-alex.bennee(a)linaro.org>
- will drop most of the speed tweaks until 7.2 opens
[UM-2] <https://linaro.atlassian.net/browse/UM-2>
Completed Reviews [1/1]
=======================
[PATCH 00/62] target/arm: Implement FEAT_HAFDBS
Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org>
Absences
========
- 2 day week next week
- will take a long w/e for August BH
--
Alex Bennée
Hello,
I noticed that I didn't send a report for week #30. Sorry about that. For
that reason, this report covers two weeks.
# [GNU-767] Support changing SVE vector length in remote debugging
- Prepared and submitted upstream a fix and a testcase for a small SVE bug
when debugging in native mode an inferior which changes the SVE length.
Luis reviewed it and I submitted v2 addressing his comments.
# Misc
- Was out for 2 days.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- more investigation, triage and fixing of minor bugs in run-up to release
* QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG]
- starting working on the PMUv8p5 enhancements. These consist of a couple
of new cycle-counter-disable bits (easy) and extension of the event
counters to 64 bits (more tricky). So far I have code for the easy part
and have made a start on the hard part...
-- PMM
Progress:
* UM-2 [QEMU upstream maintainership]
- debugged and sent patch to fix a bug in timer_create
syscall support in linux-user on certain host libcs
- tried and failed to repro a bug where semihosting SYS_HEAPINFO
was returning addresses in the flash rom
- more Coverity issue triage -- now have finished triage of
everything that isn't either in the test suite or an
"insecure data handling" issue. Sent patches for a few
issues, prodded other people about some more...
-- PMM
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
* Fixed last bug which prevented the sve-ioctls QEMU testcase to be
correctly stepped through in gdbserver. The next step is checking
whether any regression was introduced by my changes, and clean up the
code.
* In the process, spotted small bug in GDB when stepping through the
sve-ioctls QEMU testcase using the existing native support. Started
preparing a patch to submit upstream.
# [LLVM-769] Linaro CI
* Increased tcwg-fx-02 ccache max size to 40 GB.
* Learned a bit about Zorg and started adding “depends_on_projects”
field to builders running on Linaro workers.
--
Thiago
Hi,
I noticed that bots like flang-aarch64-latest-gcc are quite slow and could
benefit from enabling ccache. Could you make it available on the system so
it could be turned on for all these builds?
Thanks,
--
Mehdi
Progress:
* UM-2 [QEMU upstream maintainership]
- softfreeze this week; lots of pullrequest merging
- spent some time going through our backlog of Coverity Scan issues, triaging
them and sending patches for some of them
- sent a patchset fixing portability issues in our configure script which
had crept in recently and were causing problems on OpenBSD and NetBSD
- sent out the invite emails for QEMU Summit
-- PMM
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
* Rebased the actual SVE vector length changes on top of the stabilised
per-thread target descriptions changes. Now stabilising the result. Fixed
a couple of problems found when remote-debugging QEMU's sve-ioctls test
binary, currently looking into a third one.
# Linaro CI's GDB testsuite results
* Updated and expanded the LLVM Docker Buildbot Maintenance wiki page with
the information about ccache setup I gathered in the past few days. Also
added a link to it to the Buildkite Bot Maintenance wiki page since
libstdc++ buildkites uses the same configuration.
* Increased ccache max size in GNU build jobs on tcwg-jade-02.
* Updated ABE repo's tested branch with my commits from last week to
improve the GDB testsuite results. Confirmed that the GDB testsuite went
from 538 unexpected failures to 307. There's still room for improvement
though.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- took over pullreq handling from RTH for the next couple of weeks
- wrote and sent patches that fix a mishandling of Secure stage 2
translation caused by QEMU not noticing that some config bits are
in VTCR_EL2 and some in VSTCR_EL2. Removed an ancient microoptimization
that was getting in the way of fixing that.
- sent patch fixing incorrect syndrome value for data abort on some
post-indexed load/store insns
- RTH's SME patchset is now upstream, so now would be a good time to
test it if anybody has compiler test cases or similar they were
thinking of running under QEMU
- softfreeze next Tuesday: started reviewing and collecting up
minor patches for a pre-freeze pullreq
-- PMM
Hello,
I went through the LLVM build bots (and also the libc++ buildkites) and
increased their ccache max size. There was a big impact on the flang
builds on tcwg-jade-01 (which went from 1h–2h to 10min–30min), but not
on other builds. One reason is probably that since I made this change
earlier today, there wasn't time yet to finish enough several-hours-long
builds to warm up the caches.
Since different machines have different disk sizes and free space I
chose different ccache max sizes for them, as follows:
* tcwg-fx-02 hosts the following build bots:
- clang-aarch64-sve-vls-2stage
- clang-aarch64-sve-vls
- clang-aarch64-sve-vla-2stage
- clang-aarch64-sve-vla
All share the same ccache. I changed its max size to 20 GB. It's not a
lot, but this machine is also used as a dev box so I though it would
be good to preserve a fair amount of space.
* tcwg-jade-01 hosts the following build bots:
- clang-armv8-lld-2stage
- clang-armv7-vfpv3-2stage
- clang-armv7-global-isel
- clang-armv7-quick
- clang-armv7-2stage
- clang-armv7-lnt
- flang-aarch64-latest-gcc
- flang-aarch64-rel-assert
- flang-aarch64-release
- flang-aarch64-latest-clang
- flang-aarch64-debug
- flang-aarch64-out-of-tree
- flang-aarch64-sharedlibs
- flang-aarch64-dylib
- clang-aarch64-full-2stage
- clang-aarch64-global-isel
- clang-aarch64-lld-2stage
- clang-aarch64-quick
All armv7 and armv8 bots share one ccache, and all aarch64 bots share
another. I changed the max size of each one to 100 GB.
* tcwg-jade-04 hosts the following build bots:
- lldb-aarch64-ubuntu
- lldb-arm-ubuntu
- buildkite-linaro-armv8-libcxx-01
- buildkite-linaro-armv8-libcxx-02
- buildkite-linaro-armv8-libcxx-03
- buildkite-linaro-armv8-libcxx-04
The buildkite bots share a 50 GB ccache, while lldb-arm-ubuntu uses
another 50 GB ccache due to being based on a different distro version.
And lldb-aarch64-ubuntu also uses its own 50 GB ccache.
* tcwg-llvmbot_tk1-01.tcwglab hosts the following build bot:
- silent-linaro-tk1-01
I changed the max cache size to 10 GB. There's not a lot of free space
on the machine.
* tcwg-llvmbot_tk1-03.tcwglab hosts the following build bot:
- normal-linaro-tk1-02
I changed the max cache size to 20 GB.
* tcwg-llvmbot_tk1-05.tcwglab hosts the following build bot:
- silent-linaro-tk1-08
I changed the max cache size to 10 GB.
* The following tcwg-llvmbot_tk1-* machines are currently unreachable so
I couldn't examine them:
- tcwg-llvmbot_tk1-02.tcwglab
- tcwg-llvmbot_tk1-04.tcwglab
* The following tcwg-llvmbot_tk1-* machines are running an llvmbot
container but no builder container, so I didn't change their ccache
configuration:
- tcwg-llvmbot_tk1-06.tcwglab
- tcwg-llvmbot_tk1-07.tcwglab
- tcwg-llvmbot_tk1-08.tcwglab
- tcwg-llvmbot_tk1-09.tcwglab
* tcwg-jade-02 is a GNU builder, and from peeking into a few containers
running build jobs I have the impression that it doesn't use ccache.
Should I look into it?
* Going through our ssh config file I didn't find these build bots that
are listed at http://llvm.validation.linaro.org/ so I didn't check
their ccache usage:
- clang-arm64-windows-msvc-2stage
- clang-arm64-windows-msvc
- clang-arm64-windows-msvc-2stage
- clang-arm64-windows-msvc
- clang-native-arm-lnt-perf
- clang-armv7-vfpv3-full-2stage
- clang-thumbv7-full-2stage
- libcxx aarch64
- libcxx aarch64 -fno-exceptions
--
Thiago
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
* Analysed and fixed a couple more regressions in my branch. The change to
per-thread target descriptions in gdbserver (which was the more
challenging part) is now free of regressions. Now cleaning up the part
that actually deals with the SVE vector length change.
# Linaro CI's GDB testsuite results
* Increased ccache's max size on most build bots. Sent email to the
linaro-toolchain list summarising the current status of their ccache
setup.
* Started looking more closely into how ccache configuration is put
together in our container scripts to document it on the wiki (together
with the steps I took to change the ccache max size).
--
Thiago
