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[TCWG CI] Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses

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Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: Results changed to -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 624 # First few build errors in logs: # 00:01:42 mm/slub.c:4428:5: error: virtual use of statement not up to date # 00:01:42 mm/slub.c:4428:5: internal compiler error: verify_ssa failed # 00:01:43 make[2]: *** [scripts/Makefile.build:250: mm/slub.o] Error 1 # 00:01:44 make[1]: *** [scripts/Makefile.build:500: mm] Error 2 # 00:01:56 make: *** [Makefile:1990: .] Error 2 from -10 # build_abe binutils: -9 # build_abe stage1: -5 # build_abe qemu: -2 # linux_n_obj: 629 # linux build successful: all # linux boot successful: boot THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-680 . Status of basepoints/gcc-13-3219-g25413fdb2ac commit for tcwg_kernel: commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. * gnu-master-aarch64-next-allnoconfig ** Failure after basepoints/gcc-13-3219-g25413fdb2ac: vect: Teach vectorizer how to handle bitfield accesses: ** https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Good build: https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… Reproduce current build: <cut> mkdir -p investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 cd investigate-gcc-25413fdb2ac24933214123e24ba165026452a6f2 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests for bad and good builds mkdir -p bad/artifacts good/artifacts curl -o bad/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail curl -o good/artifacts/manifest.sh https://ci.linaro.org/job/tcwg_kernel-gnu-build-gnu-master-aarch64-next-all… --fail # Reproduce bad build (cd bad; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) # Reproduce good build (cd good; ../jenkins-scripts/tcwg_kernel-build.sh ^^ true %%rr[top_artifacts] artifacts) </cut> Full commit (up to 1000 lines): <cut> commit 25413fdb2ac24933214123e24ba165026452a6f2 Author: Andre Vieira <andre.simoesdiasvieira(a)arm.com> Date: Tue Oct 11 10:49:27 2022 +0100 vect: Teach vectorizer how to handle bitfield accesses gcc/ChangeLog: * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from here... (tree_if_conversion): ... to here. Also call bitfield lowering when appropriate. (version_loop_for_if_conversion): Adapt to enable loop versioning when we only need to lower bitfields. (ifcvt_split_critical_edges): Relax condition of expected loop form as this is checked earlier. (get_bitfield_rep): New function. (lower_bitfield): Likewise. (bitfields_to_lower_p): Likewise. (need_to_lower_bitfields): New global boolean. (need_to_ifcvt): Likewise. * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic message. * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last parameter. (vect_recog_bitfield_ref_pattern): New. (vect_recog_bit_insert_pattern): New. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-bitfield-read-1.c: New test. * gcc.dg/vect/vect-bitfield-read-2.c: New test. * gcc.dg/vect/vect-bitfield-read-3.c: New test. * gcc.dg/vect/vect-bitfield-read-4.c: New test. * gcc.dg/vect/vect-bitfield-read-5.c: New test. * gcc.dg/vect/vect-bitfield-read-6.c: New test. * gcc.dg/vect/vect-bitfield-write-1.c: New test. * gcc.dg/vect/vect-bitfield-write-2.c: New test. * gcc.dg/vect/vect-bitfield-write-3.c: New test. * gcc.dg/vect/vect-bitfield-write-4.c: New test. * gcc.dg/vect/vect-bitfield-write-5.c: New test. --- gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c | 40 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c | 44 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c | 45 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c | 39 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c | 43 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c | 42 +++ gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c | 42 +++ gcc/tree-if-conv.cc | 313 ++++++++++++++++++-- gcc/tree-vect-data-refs.cc | 3 +- gcc/tree-vect-patterns.cc | 330 +++++++++++++++++++++- 14 files changed, 1079 insertions(+), 31 deletions(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c new file mode 100644 index 00000000000..01cf34fb444 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-1.c @@ -0,0 +1,40 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define ELT0 {0} +#define ELT1 {1} +#define ELT2 {2} +#define ELT3 {3} +#define N 32 +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].i; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c new file mode 100644 index 00000000000..1a4a1579c14 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-2.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 0} +#define ELT1 {0x7FFFFFFFUL, 1} +#define ELT2 {0x7FFFFFFFUL, 2} +#define ELT3 {0x7FFFFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c new file mode 100644 index 00000000000..849f4a017e1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-3.c @@ -0,0 +1,44 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" +#include <stdbool.h> + +extern void abort(void); + +typedef struct { + int c; + int b; + bool a : 1; + int d : 31; +} struct_t; + +#define N 16 +#define ELT_F { 0xFFFFFFFF, 0xFFFFFFFF, 0, 0x7FFFFFFF } +#define ELT_T { 0xFFFFFFFF, 0xFFFFFFFF, 1, 0x7FFFFFFF } + +struct_t vect_false[N] = { ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +struct_t vect_true[N] = { ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F, + ELT_F, ELT_F, ELT_T, ELT_F, ELT_F, ELT_F, ELT_F, ELT_F }; +int main (void) +{ + unsigned ret = 0; + for (unsigned i = 0; i < N; i++) + { + ret |= vect_false[i].a; + } + if (ret) + abort (); + + for (unsigned i = 0; i < N; i++) + { + ret |= vect_true[i].a; + } + if (!ret) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c new file mode 100644 index 00000000000..5bc9c412e96 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-4.c @@ -0,0 +1,45 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define ELT0 {0x7FFFFFFFUL, 3, 0} +#define ELT1 {0x7FFFFFFFUL, 3, 1} +#define ELT2 {0x7FFFFFFFUL, 3, 2} +#define ELT3 {0x7FFFFFFFUL, 3, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].a; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c new file mode 100644 index 00000000000..1dc24d3eded --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 9; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c new file mode 100644 index 00000000000..7d24c299758 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-read-6.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned a : 23; unsigned b : 8; +}; + +#define N 32 +#define ELT0 {0x7FFFFFUL, 0} +#define ELT1 {0x7FFFFFUL, 1} +#define ELT2 {0x7FFFFFUL, 2} +#define ELT3 {0x7FFFFFUL, 3} +#define RES 48 +struct s A[N] + = { ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3, + ELT0, ELT1, ELT2, ELT3, ELT0, ELT1, ELT2, ELT3}; + +int __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + int res = 0; + for (int i = 0; i < n; ++i) + res += ptr[i].b; + return res; +} + +int main (void) +{ + check_vect (); + + if (f(&A[0], N) != RES) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c new file mode 100644 index 00000000000..19683d277b1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-1.c @@ -0,0 +1,39 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { int i : 31; }; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].i = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].i != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c new file mode 100644 index 00000000000..d550dd35ab7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-2.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c new file mode 100644 index 00000000000..3303d2610ff --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-3.c @@ -0,0 +1,43 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned i : 31; + char x : 2; + char a : 4; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c new file mode 100644 index 00000000000..fae6ea3557d --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-4.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 9; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c new file mode 100644 index 00000000000..99360c2967b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-bitfield-write-5.c @@ -0,0 +1,42 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +extern void abort(void); + +struct s { + unsigned b : 23; + unsigned a : 8; +}; + +#define N 32 +#define V 5 +struct s A[N]; + +void __attribute__ ((noipa)) +f(struct s *ptr, unsigned n) { + for (int i = 0; i < n; ++i) + ptr[i].a = V; +} + +void __attribute__ ((noipa)) +check_f(struct s *ptr) { + for (unsigned i = 0; i < N; ++i) + if (ptr[i].a != V) + abort (); +} + +int main (void) +{ + check_vect (); + __builtin_memset (&A[0], 0, sizeof(struct s) * N); + + f(&A[0], N); + check_f (&A[0]); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ + diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc index bac29fb5574..e468a4659fa 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -91,6 +91,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-pass.h" #include "ssa.h" #include "expmed.h" +#include "expr.h" #include "optabs-query.h" #include "gimple-pretty-print.h" #include "alias.h" @@ -123,6 +124,9 @@ along with GCC; see the file COPYING3. If not see #include "tree-vectorizer.h" #include "tree-eh.h" +/* For lang_hooks.types.type_for_mode. */ +#include "langhooks.h" + /* Only handle PHIs with no more arguments unless we are asked to by simd pragma. */ #define MAX_PHI_ARG_NUM \ @@ -145,6 +149,12 @@ static bool need_to_rewrite_undefined; before phi_convertible_by_degenerating_args. */ static bool any_complicated_phi; +/* True if we have bitfield accesses we can lower. */ +static bool need_to_lower_bitfields; + +/* True if there is any ifcvting to be done. */ +static bool need_to_ifcvt; + /* Hash for struct innermost_loop_behavior. It depends on the user to free the memory. */ @@ -1411,15 +1421,6 @@ if_convertible_loop_p_1 (class loop *loop, vec<data_reference_p> *refs) calculate_dominance_info (CDI_DOMINATORS); - /* Allow statements that can be handled during if-conversion. */ - ifc_bbs = get_loop_body_in_if_conv_order (loop); - if (!ifc_bbs) - { - if (dump_file && (dump_flags & TDF_DETAILS)) - fprintf (dump_file, "Irreducible loop\n"); - return false; - } - for (i = 0; i < loop->num_nodes; i++) { basic_block bb = ifc_bbs[i]; @@ -2899,18 +2900,22 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) class loop *new_loop; gimple *g; gimple_stmt_iterator gsi; - unsigned int save_length; + unsigned int save_length = 0; g = gimple_build_call_internal (IFN_LOOP_VECTORIZED, 2, build_int_cst (integer_type_node, loop->num), integer_zero_node); gimple_call_set_lhs (g, cond); - /* Save BB->aux around loop_version as that uses the same field. */ - save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; - void **saved_preds = XALLOCAVEC (void *, save_length); - for (unsigned i = 0; i < save_length; i++) - saved_preds[i] = ifc_bbs[i]->aux; + void **saved_preds = NULL; + if (any_complicated_phi || need_to_predicate) + { + /* Save BB->aux around loop_version as that uses the same field. */ + save_length = loop->inner ? loop->inner->num_nodes : loop->num_nodes; + saved_preds = XALLOCAVEC (void *, save_length); + for (unsigned i = 0; i < save_length; i++) + saved_preds[i] = ifc_bbs[i]->aux; + } initialize_original_copy_tables (); /* At this point we invalidate porfile confistency until IFN_LOOP_VECTORIZED @@ -2922,8 +2927,9 @@ version_loop_for_if_conversion (class loop *loop, vec<gimple *> *preds) profile_probability::always (), true); free_original_copy_tables (); - for (unsigned i = 0; i < save_length; i++) - ifc_bbs[i]->aux = saved_preds[i]; + if (any_complicated_phi || need_to_predicate) + for (unsigned i = 0; i < save_length; i++) + ifc_bbs[i]->aux = saved_preds[i]; if (new_loop == NULL) return NULL; @@ -2999,7 +3005,7 @@ ifcvt_split_critical_edges (class loop *loop, bool aggressive_if_conv) auto_vec<edge> critical_edges; /* Loop is not well formed. */ - if (num <= 2 || loop->inner || !single_exit (loop)) + if (loop->inner) return false; body = get_loop_body (loop); @@ -3260,6 +3266,201 @@ ifcvt_hoist_invariants (class loop *loop, edge pe) free (body); } +/* Returns the DECL_FIELD_BIT_OFFSET of the bitfield accesse in stmt iff its + type mode is not BLKmode. If BITPOS is not NULL it will hold the poly_int64 + value of the DECL_FIELD_BIT_OFFSET of the bitfield access and STRUCT_EXPR, + if not NULL, will hold the tree representing the base struct of this + bitfield. */ + +static tree +get_bitfield_rep (gassign *stmt, bool write, tree *bitpos, + tree *struct_expr) +{ + tree comp_ref = write ? gimple_assign_lhs (stmt) + : gimple_assign_rhs1 (stmt); + + tree field_decl = TREE_OPERAND (comp_ref, 1); + tree rep_decl = DECL_BIT_FIELD_REPRESENTATIVE (field_decl); + + /* Bail out if the representative is BLKmode as we will not be able to + vectorize this. */ + if (TYPE_MODE (TREE_TYPE (rep_decl)) == E_BLKmode) + return NULL_TREE; + + /* Bail out if the DECL_SIZE of the field_decl isn't the same as the BF's + precision. */ + unsigned HOST_WIDE_INT bf_prec + = TYPE_PRECISION (TREE_TYPE (gimple_assign_lhs (stmt))); + if (compare_tree_int (DECL_SIZE (field_decl), bf_prec) != 0) + return NULL_TREE; + + if (struct_expr) + *struct_expr = TREE_OPERAND (comp_ref, 0); + + if (bitpos) + *bitpos + = fold_build2 (MINUS_EXPR, bitsizetype, + DECL_FIELD_BIT_OFFSET (field_decl), + DECL_FIELD_BIT_OFFSET (rep_decl)); + + return rep_decl; + +} + +/* Lowers the bitfield described by DATA. + For a write like: + + struct.bf = _1; + + lower to: + + __ifc_1 = struct.<representative>; + __ifc_2 = BIT_INSERT_EXPR (__ifc_1, _1, bitpos); + struct.<representative> = __ifc_2; + + For a read: + + _1 = struct.bf; + + lower to: + + __ifc_1 = struct.<representative>; + _1 = BIT_FIELD_REF (__ifc_1, bitsize, bitpos); + + where representative is a legal load that contains the bitfield value, + bitsize is the size of the bitfield and bitpos the offset to the start of + the bitfield within the representative. */ + +static void +lower_bitfield (gassign *stmt, bool write) +{ + tree struct_expr; + tree bitpos; + tree rep_decl = get_bitfield_rep (stmt, write, &bitpos, &struct_expr); + tree rep_type = TREE_TYPE (rep_decl); + tree bf_type = TREE_TYPE (gimple_assign_lhs (stmt)); + + gimple_stmt_iterator gsi = gsi_for_stmt (stmt); + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Lowering:\n"); + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + fprintf (dump_file, "to:\n"); + } + + /* REP_COMP_REF is a COMPONENT_REF for the representative. NEW_VAL is it's + defining SSA_NAME. */ + tree rep_comp_ref = build3 (COMPONENT_REF, rep_type, struct_expr, rep_decl, + NULL_TREE); + tree new_val = ifc_temp_var (rep_type, rep_comp_ref, &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + if (write) + { + new_val = ifc_temp_var (rep_type, + build3 (BIT_INSERT_EXPR, rep_type, new_val, + unshare_expr (gimple_assign_rhs1 (stmt)), + bitpos), &gsi); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, SSA_NAME_DEF_STMT (new_val), 0, TDF_SLIM); + + gimple *new_stmt = gimple_build_assign (unshare_expr (rep_comp_ref), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + else + { + tree bfr = build3 (BIT_FIELD_REF, bf_type, new_val, + build_int_cst (bitsizetype, TYPE_PRECISION (bf_type)), + bitpos); + new_val = ifc_temp_var (bf_type, bfr, &gsi); + + gimple *new_stmt = gimple_build_assign (gimple_assign_lhs (stmt), + new_val); + gimple_move_vops (new_stmt, stmt); + gsi_insert_before (&gsi, new_stmt, GSI_SAME_STMT); + + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, new_stmt, 0, TDF_SLIM); + } + + gsi_remove (&gsi, true); +} + +/* Return TRUE if there are bitfields to lower in this LOOP. Fill TO_LOWER + with data structures representing these bitfields. */ + +static bool +bitfields_to_lower_p (class loop *loop, + vec <gassign *> &reads_to_lower, + vec <gassign *> &writes_to_lower) +{ + gimple_stmt_iterator gsi; + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Analyzing loop %d for bitfields:\n", loop->num); + } + + for (unsigned i = 0; i < loop->num_nodes; ++i) + { + basic_block bb = ifc_bbs[i]; + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) + { + gassign *stmt = dyn_cast<gassign*> (gsi_stmt (gsi)); + if (!stmt) + continue; + + tree op = gimple_assign_lhs (stmt); + bool write = TREE_CODE (op) == COMPONENT_REF; + + if (!write) + op = gimple_assign_rhs1 (stmt); + + if (TREE_CODE (op) != COMPONENT_REF) + continue; + + if (DECL_BIT_FIELD_TYPE (TREE_OPERAND (op, 1))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + + if (!INTEGRAL_TYPE_P (TREE_TYPE (op))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NO OK to lower," + " field type is not Integral.\n"); + return false; + } + + if (!get_bitfield_rep (stmt, write, NULL, NULL)) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NOT OK to lower," + " representative is BLKmode.\n"); + return false; + } + + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\tBitfield OK to lower.\n"); + if (write) + writes_to_lower.safe_push (stmt); + else + reads_to_lower.safe_push (stmt); + } + } + } + return !reads_to_lower.is_empty () || !writes_to_lower.is_empty (); +} + + /* If-convert LOOP when it is legal. For the moment this pass has no profitability analysis. Returns non-zero todo flags when something changed. */ @@ -3270,12 +3471,16 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) unsigned int todo = 0; bool aggressive_if_conv; class loop *rloop; + auto_vec <gassign *, 4> reads_to_lower; + auto_vec <gassign *, 4> writes_to_lower; bitmap exit_bbs; edge pe; again: rloop = NULL; ifc_bbs = NULL; + need_to_lower_bitfields = false; + need_to_ifcvt = false; need_to_predicate = false; need_to_rewrite_undefined = false; any_complicated_phi = false; @@ -3291,16 +3496,42 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) aggressive_if_conv = true; } - if (!ifcvt_split_critical_edges (loop, aggressive_if_conv)) + if (!single_exit (loop)) goto cleanup; - if (!if_convertible_loop_p (loop) - || !dbg_cnt (if_conversion_tree)) + /* If there are more than two BBs in the loop then there is at least one if + to convert. */ + if (loop->num_nodes > 2 + && !ifcvt_split_critical_edges (loop, aggressive_if_conv)) goto cleanup; - if ((need_to_predicate || any_complicated_phi) - && ((!flag_tree_loop_vectorize && !loop->force_vectorize) - || loop->dont_vectorize)) + ifc_bbs = get_loop_body_in_if_conv_order (loop); + if (!ifc_bbs) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "Irreducible loop\n"); + goto cleanup; + } + + if (loop->num_nodes > 2) + { + need_to_ifcvt = true; + + if (!if_convertible_loop_p (loop) || !dbg_cnt (if_conversion_tree)) + goto cleanup; + + if ((need_to_predicate || any_complicated_phi) + && ((!flag_tree_loop_vectorize && !loop->force_vectorize) + || loop->dont_vectorize)) + goto cleanup; + } + + if ((flag_tree_loop_vectorize || loop->force_vectorize) + && !loop->dont_vectorize) + need_to_lower_bitfields = bitfields_to_lower_p (loop, reads_to_lower, + writes_to_lower); + + if (!need_to_ifcvt && !need_to_lower_bitfields) goto cleanup; /* The edge to insert invariant stmts on. */ @@ -3311,7 +3542,8 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) Either version this loop, or if the pattern is right for outer-loop vectorization, version the outer loop. In the latter case we will still if-convert the original inner loop. */ - if (need_to_predicate + if (need_to_lower_bitfields + || need_to_predicate || any_complicated_phi || flag_tree_loop_if_convert != 1) { @@ -3351,10 +3583,31 @@ tree_if_conversion (class loop *loop, vec<gimple *> *preds) pe = single_pred_edge (gimple_bb (preds->last ())); } - /* Now all statements are if-convertible. Combine all the basic - blocks into one huge basic block doing the if-conversion - on-the-fly. */ - combine_blocks (loop); + if (need_to_lower_bitfields) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "-------------------------\n"); + fprintf (dump_file, "Start lowering bitfields\n"); + } + while (!reads_to_lower.is_empty ()) + lower_bitfield (reads_to_lower.pop (), false); + while (!writes_to_lower.is_empty ()) + lower_bitfield (writes_to_lower.pop (), true); + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf (dump_file, "Done lowering bitfields\n"); + fprintf (dump_file, "-------------------------\n"); + } + } + if (need_to_ifcvt) + { + /* Now all statements are if-convertible. Combine all the basic + blocks into one huge basic block doing the if-conversion + on-the-fly. */ + combine_blocks (loop); + } </cut>

2 years, 11 months

1
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[ACTIVITY] Report for weeks #37, #39 and #40

by Thiago Jung Bauermann

Hello, I haven't sent a report since week #36. For that reason, this report covers three weeks. # [GNU-796] Stabilise GDB testsuite results in the CI - Implemented CI job to run fast GDB tests based on the list from Sourceware's builder. Submitted Gerrit change requests for jenkins-scripts and ci/job/configs. - Posted Gerrit change request for jenkins-scripts with an improvement to tcwg_gnu-build.sh to use a default path for the artifacts file if one isn't given on the command line. # [GNU-767] Support changing SVE vector length in remote debugging - Started incorporating suggestions from Luis' review of the patches. # Community participation - Reviewed mailing list patch “[PATCH v3] gdb/arm: Handle lazy FPU register stacking” - Attended GNU Tools Cauldron 2022. -- Thiago

2 years, 11 months

1
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0 0

[ACTIVITY] week ending Oct. 9 2022

by Alex Bennée

Project Stratos =============== [UM-196] <https://linaro.atlassian.net/browse/UM-196> vhost-device maintainer effort ([UM-196]) - [review of vhost-sock for vhost-device] [review of vhost-sock for vhost-device] <https://github.com/rust-vmm/vhost-device/pull/216> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL 00/54] testing, gdbstub, plugin and gitdm updates Message-Id: <20221004130138.2299307-1-alex.bennee(a)linaro.org> - took 3 attempts [PULL v3 00/52] testing, gdbstub, plugin and gitdm updates Message-Id: <20221006105556.3319342-1-alex.bennee(a)linaro.org> - leadership committee work - member engagement on CCA/RME [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [3/3] ======================= [PATCH 00/20] Cross compilation changes for 7.2 Message-Id: <20220825222745.38779-13-pbonzini(a)redhat.com> [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Message-Id: <20221004141051.110653-4-richard.henderson(a)linaro.org> [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> Other ===== - reviews and appraisals Absences ======== Current Review Queue ==================== TODO [PATCH 00/24] accel/tcg: Rewrite user-only vma tracking Message-Id: <20221006031113.1139454-2-richard.henderson(a)linaro.org> =============================================================================================================================== TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org> =========================================================================================================================================================================== -- Alex Bennée

2 years, 11 months

1
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[ACTIVITY] report week ending Oct 7

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - miscellaneous upstream patch review * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - sent out patchset implementing FEAT_GTG - sent out patch implementing FEAT_E0PD - code review of RTH's FEAT_HAFDBS patchset -- PMM

2 years, 11 months

1
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0 0

[ACTIVITY] report week ending 30 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent out patch which adds a retry-on-EINTR loop to KVM_CREATE_VM ioctls - wrote up the draft of the minutes for the QEMU Summit for review - more code review and pullrequest collation (notably the Arm v8R support patchset) * QEMU-471 [QEMU ARM v9.0 Baseline CPU for TCG] - read up on the remaining unimplemented features under this epic; closed out one we'd already implemented, and wrote up enough detail on the others to be happy with putting them all into the current sprint (they're all small features) - started looking at FEAT_GTG thanks -- PMM

2 years, 11 months

1
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[ACTIVITY] week ending Sep. 25 2022

by Alex Bennée

Project Stratos =============== - held poll for next meeting - started planning for virtio-camera/sensor QEMU Upstream Work ([UM-2]) =========================== - posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id: <CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com> - sadly one patch had to be reverted as it exposed another race - posted [PATCH v1 00/10] plugins/next (disas, monitor, docs, execlog) Message-Id: <20220921160801.1490125-6-alex.bennee(a)linaro.org> - posted [PULL 00/30] testing updates (docker, avocado, deprecate 32bit BE MIPS) Message-Id: <20220920171533.1098094-4-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Update docs - mention -d plugin - document features of tests/plugin plugins - clean up command lines to drop builddir KVM Forum ========= - Attended KVM forum, gave a talk, helper with another Completed Reviews [3/3] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> [RFC PATCH v2] gdbstub: only send stop-reply packets when allowed to Message-Id: <ba99db564c3aeb1812bdfbc9116849092334482f.1661362557.git.quic_mathbern(a)quicinc.com> [RFC 0/4] Support interactions between TCG plugins Message-Id: <20220901182734.2987337-1-fasano(a)mit.edu> Absences ======== Current Review Queue ==================== TODO [PATCH v4 0/7] tcg: pc-relative translation blocks Message-Id: <20220906091126.298041-1-richard.henderson(a)linaro.org> ========================================================================================================================= TODO [PATCH 00/51] tests/qtest: Enable running qtest on Windows Message-Id: <20220824094029.1634519-1-bmeng.cn(a)gmail.com> ======================================================================================================================== TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org> ======================================================================================================================================= -- Alex Bennée

2 years, 12 months

1
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0 0

[ACTIVITY] report week ending 23 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - attended KVM Forum - catching up with code review, email, etc... - sent out an Arm pullreq now 7.2 has opened up for development * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - diagnosed a regression caused by the recent FEAT_PMUv3p5 changes and sent out a fix KVM Forum trip highlights: * it was good to be able to meet people face-to-face again after several years * Cloud use of Arm hardware has now got to the point where big cloud companies are working through performance issues and then coming to present about it; e.g. Google did a talk about perf issues during migration on an Ampere Altra setup. The solutions seem to be a mix of "apply the lessons and fixes we already went through with x86" and "architecture fixes coming down the pipe" (in this case FEAT_TLBIRANGE and FEAT_BBM). * lots of Google talks about pKVM (using hypervisor hardware on Android to improve security). In fact lots of Google all over -- apparently they've made a big push to do more upstream kernel work and as a result a large chunk of the kernel KVM commits come from them... * talk from Xilinx (now with AMD) about doing co-simulation of QEMU and RTL -- basically (with the aid of a lot of non-upstream stuff) having QEMU talk to a SystemC environment so you can have eg an emulated ethernet card in FPGA that plugs into a QEMU VM. This kind of thing is a use-case which historically upstream have not really been interested in addressing. * Which brings me to the BoF session on emulation, perhaps the most interesting bit of the conference for me. There was a lot of discussion about whether QEMU might move closer to what I call the "bag of lego bricks" paradigm, where it provides device models and users might be able to configure it at runtime to stitch them together, perhaps adding out-of-tree devices of their own. There is clearly interest in this (eg from attendees from Xilinx and Qualcomm); the sticking point is that from upstream's perspective this seems like "you should do this thing that will benefit us and not you". My take is that whether this goes anywhere will depend on whether those who would like this are prepared to coordinate together to present themselves as a group who are willing to dig in to the necessary upstream refactoring and cleanup that would be a precondition for having something like this be anywhere near supportable, i.e. that they're a group who will come and help rather than merely consume... * There was also a shorter discussion in the BoF about the idea of "heterogenous CPU emulation", eg one QEMU model with both Arm and Microblaze CPUs. This is not conceptually controversial, it's just a lot of work. It seemed like maybe a few folk now care enough to have a go at it. -- PMM

2 years, 12 months

1
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[ACTIVITY] Report for week #36

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Made a few last-minute adjustments to the code and fixed a couple of regressions on x86_64-linux. Re-ran regression tests on x86_64-linux and aarch64-linux. Wrote cover letter and descriptions for all the patches. - Finally posted the patch series upstream¹. # [GNU-796] Stabilize GDB testsuite results in the Linaro CI - Started working on this issue. Currently adding a new CI job to run the same small subset of GDB testcases that Sourceware's buildbot runs. This subset runs quickly and has stable results so the job will be a good canary to check that the CI infrastructure is working correctly. -- Thiago ¹https://inbox.sourceware.org/gdb-patches/20220908064151.3959930-1-thiago.b…

3 years

1
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0 0

[ACTIVITY] Report for week #35

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Cleaned up code for upstream submission, and divided it into patches. A couple of the patches affect other architectures and OSes, so made sure the code builds on as many combinations I can test, and now doing final regression testing on some of them. I'm hoping to finally send the patches upstream early next week. -- Thiago

3 years

1
0
0 0

[ACTIVITY] Report for week #34

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Finished fixing regressions in my changes to gdbserver for debugging an inferior which changes the SVE length. - Started cleaning up code for upstream submission and dividing it into patches. # Community participation - Reviewed mailing list patches: - [PATCH,v3] [aarch64] Fix removal of non-address bits for PAuth - [PATCH 1/2] gdb: Fix deleted thread when issuing next command - [PATCH 2/2] gdb: Improve the resuming of the stepped thread -- Thiago

3 years

1
0
0 0

[ACTIVITY] report week ending 25 Aug

by Peter Maydell

Progress (short week, 3 days): * UM-2 [QEMU upstream maintainership] - pretty much just tying up loose ends and doing other miscellaneous bits and pieces * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - respin, resend of PMUv3p5 series -- PMM

3 years

1
0
0 0

[ACTIVITY] Report for week #33

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - v2 of the patches fixing a small SVE bug when debugging in native mode an inferior which changes the SVE length was committed upstream. - Continued working on fixing regressions in my changes to gdbserver for debugging an inferior which changes the SVE length. -- Thiago

3 years, 1 month

1
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0 0

[ACTIVITY] week ending Aug. 21 2022

by Alex Bennée

Project Stratos =============== - continued working on [adding vhost-user-rng to crosvm] - this is to demo Stratos on Gunyah - re-built guest kernel with known working backend - it works :-) - initial review of Viresh's slides for KVM Forum talk [adding vhost-user-rng to crosvm] <https://github.com/stsquad/crosvm/tree/add-vhost-user-rng> vhost-device maintainer effort ([UM-196]) - prepared a clean-up [branch for new queue interface] - spent time testing and realised it had broken things [branch for new queue interface] <https://github.com/stsquad/vhost-device/tree/update-queue-interface> QEMU Upstream Work ([UM-2]) =========================== - posted [PULL for 7.1 0/3] memory leak and testing tweaks Message-Id: <CAFEAcA8oPjTq9quHxOCSczckwmmBSP0fY6dtCzwrNs59pMrNCw(a)mail.gmail.com> - sadly one patch had to be reverted as it exposed another race [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [1/1] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> Absences ======== - will take a long w/e for August BH Current Review Queue ==================== TODO [PATCH v2 00/33] accel/tcg + target/arm: pc-relative translation Message-Id: <20220816203400.161187-1-richard.henderson(a)linaro.org> ======================================================================================================================================= TODO [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Message-Id: <20220812180806.2128593-22-richard.henderson(a)linaro.org> =========================================================================================================================================================================== -- Alex Bennée

3 years, 1 month

1
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[ACTIVITY] report week ending 19 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - respin and resend for a few patchsets after code review * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - identified what the old ARMv8.5-CMODX feature is now ("prefetch speculation protection") and confirmed that QEMU is already compliant with the instruction fetch ordering requirements so there's no coding work required here - Checked that we implement FEAT_ETS already and sent patches to advertise it in the ID registers - Checked that we already conform to the ordering rules required by "prefetch speculation protection" - Discovered that we accidentally fail to RAZ for a big chunk of the reserved-for-new-AArch32-ID-registers space for v8 CPUs; sent patches fixing that thanks -- PMM

3 years, 1 month

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clang-arm64-windows-msvc is red for 12 days

by Galina Kistanova

Hello Linaro Toolchain Working Group, clang-arm64-windows-msvc is red for 12 days. The host is missing a correct version of msvc. Is somebody looking at this? Thanks Galina

3 years, 1 month

2
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[ACTIVITY] report week ending 12 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - usual release cycle work: rounded up a couple of last-minute fixes for "whoops, this crashes" bugs and some safe changes like docs typo fixes. * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - Finished implementing the FEAT_PMUv3p5 work. In the process of testing it I found a handful of bugs in our existing PMU emulation code. Sent out the patchset which fixes those bugs and adds FEAT_PMUv3p5. - Cleaned up the epic to remove subtasks we aren't going to implement (FEAT_SPE, FEAT_TRF), and added one for "actually define the new CPU model" - FEAT_LSE2 is the only remaining real work here, and it is probably going to be seriously tricky...(i.e. I hope to leave it to RTH ;-)) -- PMM

3 years, 1 month

1
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[ACTIVITY] week ending Aug. 14 2022

by Alex Bennée

Project Stratos =============== - continued working on [adding vhost-user-rng to crosvm] - this is to demo Stratos on Gunyah - backend comes up and device is detected but queues are not consumed - had some initial discussions with Viresh about talk structure for KVM Forum [adding vhost-user-rng to crosvm] <https://github.com/stsquad/crosvm/tree/add-vhost-user-rng> vhost-device maintainer effort ([UM-196]) - prepared a clean-up [branch for new queue interface] [UM-196] <https://linaro.atlassian.net/browse/UM-196> [branch for new queue interface] <https://github.com/stsquad/vhost-device/tree/update-queue-interface> QEMU Upstream Work ([UM-2]) =========================== - posted [PATCH for 7.1 v1 0/8] memory leaks and speed tweaks Message-Id: <20220811151413.3350684-8-alex.bennee(a)linaro.org> - will drop most of the speed tweaks until 7.2 opens [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [1/1] ======================= [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Message-Id: <20220703082419.770989-1-richard.henderson(a)linaro.org> Absences ======== - 2 day week next week - will take a long w/e for August BH -- Alex Bennée

3 years, 1 month

1
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[ACTIVITY] week ending Aug. 7 2022

by Alex Bennée

Project Stratos =============== - worked on [adding vhost-user-rng to crosvm] - this is to demo Stratos on Gunyah [adding vhost-user-rng to crosvm] <https://github.com/stsquad/crosvm/tree/add-vhost-user-rng> vhost-device maintainer effort ([UM-196]) - posted [error message cleanup series] [UM-196] <https://linaro.atlassian.net/browse/UM-196> [error message cleanup series] <https://github.com/rust-vmm/vhost/pull/113> Linux RPMB Sub-system and virtio-driver ([STR-40]) - posted [PATCH v4 for 7.2 00/22] virtio-gpio and various virtio cleanups Message-Id: <20220802095010.3330793-1-alex.bennee(a)linaro.org> [STR-40] <https://linaro.atlassian.net/browse/STR-40> QEMU Upstream Work ([UM-2]) =========================== - posted [RFC PATCH] util: add a qemu_backtrace utility function Message-Id: <20220801141209.2184305-1-alex.bennee(a)linaro.org> - posted [PATCH v2] linux-user: un-parent OBJECT(cpu) when closing thread Message-Id: <20220803130537.763666-1-alex.bennee(a)linaro.org> - posted [RFC PATCH] cputlb and ssi: cache class to avoid expensive object_dynamic_cast_assert (HACK!!!) Message-Id: <20220804092044.2101093-1-alex.bennee(a)linaro.org> [UM-2] <https://linaro.atlassian.net/browse/UM-2> Completed Reviews [4/4] ======================= [PATCH] tests/tcg/i386: Use explicit suffix on fist insns Message-Id: <20220527171143.168276-1-richard.henderson(a)linaro.org> [PATCH 00/43] semihosting cleanup Message-Id: <20220430132932.324018-1-richard.henderson(a)linaro.org> [PATCH 0/2] gdbstub: don't crash if no gdb attached and gdb syscall attempted Message-Id: <20220526190053.521505-1-peter.maydell(a)linaro.org> [PATCH 0/2] Floating-point OE/UE exception bug Message-Id: <87pmhemzh9.fsf(a)linaro.org> Absences ======== Current Review Queue ==================== TODO [PATCH RFC v2 0/2] arm: enable MTE for QEMU + kvm Message-Id: <20220707161656.41664-1-cohuck(a)redhat.com> ============================================================================================================ TODO [PATCH v4 0/9] Record/replay refactoring and stuff Message-Id: <165364836050.688121.11980415709895333098.stgit@pasha-ThinkPad-X280> ======================================================================================================================================= TODO [PATCH v11 0/2] hw/arm/virt: CXL 2.0 emulation support Message-Id: <20220520163732.27545-3-Jonathan.Cameron(a)huawei.com> =========================================================================================================================== -- Alex Bennée

3 years, 1 month

1
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[ACTIVITY] Report for weeks #30 and #31

by Thiago Jung Bauermann

Hello, I noticed that I didn't send a report for week #30. Sorry about that. For that reason, this report covers two weeks. # [GNU-767] Support changing SVE vector length in remote debugging - Prepared and submitted upstream a fix and a testcase for a small SVE bug when debugging in native mode an inferior which changes the SVE length. Luis reviewed it and I submitted v2 addressing his comments. # Misc - Was out for 2 days. -- Thiago

3 years, 1 month

1
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[ACTIVITY] report week ending 5 Aug

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - more investigation, triage and fixing of minor bugs in run-up to release * QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG] - starting working on the PMUv8p5 enhancements. These consist of a couple of new cycle-counter-disable bits (easy) and extension of the event counters to 64 bits (more tricky). So far I have code for the easy part and have made a start on the hard part... -- PMM

3 years, 1 month

1
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[ACTIVITY] report week ending 29 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - debugged and sent patch to fix a bug in timer_create syscall support in linux-user on certain host libcs - tried and failed to repro a bug where semihosting SYS_HEAPINFO was returning addresses in the flash rom - more Coverity issue triage -- now have finished triage of everything that isn't either in the test suite or an "insecure data handling" issue. Sent patches for a few issues, prodded other people about some more... -- PMM

3 years, 1 month

1
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[ACTIVITY] Report for week #29

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Fixed last bug which prevented the sve-ioctls QEMU testcase to be correctly stepped through in gdbserver. The next step is checking whether any regression was introduced by my changes, and clean up the code. * In the process, spotted small bug in GDB when stepping through the sve-ioctls QEMU testcase using the existing native support. Started preparing a patch to submit upstream. # [LLVM-769] Linaro CI * Increased tcwg-fx-02 ccache max size to 40 GB. * Learned a bit about Zorg and started adding “depends_on_projects” field to builders running on Linaro workers. -- Thiago

3 years, 1 month

1
0
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Enabling CCache on LLVM bots

by Mehdi AMINI

Hi, I noticed that bots like flang-aarch64-latest-gcc are quite slow and could benefit from enabling ccache. Could you make it available on the system so it could be turned on for all these builds? Thanks, -- Mehdi

3 years, 1 month

4
14
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[ACTIVITY] report week ending 21 Jul

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - softfreeze this week; lots of pullrequest merging - spent some time going through our backlog of Coverity Scan issues, triaging them and sending patches for some of them - sent a patchset fixing portability issues in our configure script which had crept in recently and were causing problems on OpenBSD and NetBSD - sent out the invite emails for QEMU Summit -- PMM

3 years, 1 month

1
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[ACTIVITY] Report for week #28

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging * Rebased the actual SVE vector length changes on top of the stabilised per-thread target descriptions changes. Now stabilising the result. Fixed a couple of problems found when remote-debugging QEMU's sve-ioctls test binary, currently looking into a third one. # Linaro CI's GDB testsuite results * Updated and expanded the LLVM Docker Buildbot Maintenance wiki page with the information about ccache setup I gathered in the past few days. Also added a link to it to the Buildkite Bot Maintenance wiki page since libstdc++ buildkites uses the same configuration. * Increased ccache max size in GNU build jobs on tcwg-jade-02. * Updated ABE repo's tested branch with my commits from last week to improve the GDB testsuite results. Confirmed that the GDB testsuite went from 538 unexpected failures to 307. There's still room for improvement though. -- Thiago

3 years, 2 months

1
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0 0

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