[TCWG CI] 453.povray failed to build after llvm: [SLP]Fix reused extracts cost.
by ci_notify＠linaro.org
After llvm commit ba74bb3a226e1b4660537f274627285b1bf41ee1
Author: Alexey Bataev <a.bataev(a)outlook.com>
[SLP]Fix reused extracts cost.
the following benchmarks slowed down by more than 2%:
- 453.povray failed to build
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-ba74bb3a226e1b4660537f274627285b1bf41ee1
cd investigate-llvm-ba74bb3a226e1b4660537f274627285b1bf41ee1
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach ba74bb3a226e1b4660537f274627285b1bf41ee1
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 78cc133c63173a4b5b7a43750cc507d4cff683cf
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit ba74bb3a226e1b4660537f274627285b1bf41ee1
Author: Alexey Bataev <a.bataev(a)outlook.com>
Date: Thu Dec 2 04:22:55 2021 -0800
[SLP]Fix reused extracts cost.
If the extractelement instruction is used multiple times in the
different tree entries (either vectorized, or gathered), need to
compensate the scalar cost of such instructions. They are completely
removed if all users are part of the tree but we need to compensate the
cost only once for each instruction.
Differential Revision: https://reviews.llvm.org/D114958
---
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 29 +++++++++++++---------
.../X86/extractelement-multiple-uses.ll | 23 +++++++++--------
2 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 95061e9053fa..335ad6c85387 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -4287,8 +4287,8 @@ bool BoUpSLP::canReuseExtract(ArrayRef<Value *> VL, Value *OpValue,
bool BoUpSLP::areAllUsersVectorized(Instruction *I,
ArrayRef<Value *> VectorizedVals) const {
return (I->hasOneUse() && is_contained(VectorizedVals, I)) ||
- llvm::all_of(I->users(), [this](User *U) {
- return ScalarToTreeEntry.count(U) > 0;
+ all_of(I->users(), [this](User *U) {
+ return ScalarToTreeEntry.count(U) > 0 || MustGather.contains(U);
});
}
@@ -4442,9 +4442,9 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
// FIXME: it tries to fix a problem with MSVC buildbots.
TargetTransformInfo &TTIRef = *TTI;
auto &&AdjustExtractsCost = [this, &TTIRef, CostKind, VL, VecTy,
- VectorizedVals](InstructionCost &Cost,
- bool IsGather) {
+ VectorizedVals, E](InstructionCost &Cost) {
DenseMap<Value *, int> ExtractVectorsTys;
+ SmallPtrSet<Value *, 4> CheckedExtracts;
for (auto *V : VL) {
if (isa<UndefValue>(V))
continue;
@@ -4452,7 +4452,12 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
// instruction itself is not going to be vectorized, consider this
// instruction as dead and remove its cost from the final cost of the
// vectorized tree.
- if (!areAllUsersVectorized(cast<Instruction>(V), VectorizedVals))
+ // Also, avoid adjusting the cost for extractelements with multiple uses
+ // in different graph entries.
+ const TreeEntry *VE = getTreeEntry(V);
+ if (!CheckedExtracts.insert(V).second ||
+ !areAllUsersVectorized(cast<Instruction>(V), VectorizedVals) ||
+ (VE && VE != E))
continue;
auto *EE = cast<ExtractElementInst>(V);
Optional<unsigned> EEIdx = getExtractIndex(EE);
@@ -4549,11 +4554,6 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
}
return GatherCost;
}
- if (isSplat(VL)) {
- // Found the broadcasting of the single scalar, calculate the cost as the
- // broadcast.
- return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy);
- }
if ((E->getOpcode() == Instruction::ExtractElement ||
all_of(E->Scalars,
[](Value *V) {
@@ -4571,13 +4571,18 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
// single input vector or of 2 input vectors.
InstructionCost Cost =
computeExtractCost(VL, VecTy, *ShuffleKind, Mask, *TTI);
- AdjustExtractsCost(Cost, /*IsGather=*/true);
+ AdjustExtractsCost(Cost);
if (NeedToShuffleReuses)
Cost += TTI->getShuffleCost(TargetTransformInfo::SK_PermuteSingleSrc,
FinalVecTy, E->ReuseShuffleIndices);
return Cost;
}
}
+ if (isSplat(VL)) {
+ // Found the broadcasting of the single scalar, calculate the cost as the
+ // broadcast.
+ return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy);
+ }
InstructionCost ReuseShuffleCost = 0;
if (NeedToShuffleReuses)
ReuseShuffleCost = TTI->getShuffleCost(
@@ -4755,7 +4760,7 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
TTI->getVectorInstrCost(Instruction::ExtractElement, VecTy, I);
}
} else {
- AdjustExtractsCost(CommonCost, /*IsGather=*/false);
+ AdjustExtractsCost(CommonCost);
}
return CommonCost;
}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
index c47f255f0bfe..31696752bbb3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
@@ -2,24 +2,25 @@
; RUN: opt < %s -slp-vectorizer -S -mtriple=x86_64-unknown-linux -march=core-avx2 -pass-remarks-output=%t | FileCheck %s
; RUN: FileCheck %s --input-file=%t --check-prefix=YAML
-; YAML: --- !Missed
+; YAML: --- !Passed
; YAML: Pass: slp-vectorizer
-; YAML: Name: NotBeneficial
+; YAML: Name: VectorizedList
; YAML: Function: multi_uses
; YAML: Args:
-; YAML: - String: 'List vectorization was possible but not beneficial with cost '
-; YAML: - Cost: '0'
-; YAML: - String: ' >= '
-; YAML: - Treshold: '0'
+; YAML: - String: 'SLP vectorized with cost '
+; YAML: - Cost: '-1'
+; YAML: - String: ' and with tree size '
+; YAML: - TreeSize: '3'
define float @multi_uses(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: @multi_uses(
-; CHECK-NEXT: [[X0:%.*]] = extractelement <2 x float> [[X:%.*]], i32 0
-; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x float> [[X]], i32 1
; CHECK-NEXT: [[Y1:%.*]] = extractelement <2 x float> [[Y:%.*]], i32 1
-; CHECK-NEXT: [[X0X0:%.*]] = fmul float [[X0]], [[Y1]]
-; CHECK-NEXT: [[X1X1:%.*]] = fmul float [[X1]], [[Y1]]
-; CHECK-NEXT: [[ADD:%.*]] = fadd float [[X0X0]], [[X1X1]]
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[Y1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[Y1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[X:%.*]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP4]], [[TMP5]]
; CHECK-NEXT: ret float [[ADD]]
;
%x0 = extractelement <2 x float> %x, i32 0
</cut>
3 years, 6 months
- 3
- 3
[TCWG CI] 464.h264ref slowed down by 3% after llvm: [SLP]Improve isFixedVectorShuffle and its use.
by ci_notify＠linaro.org
After llvm commit dce6c434ead3ccbaa67b8db2301b2a9fb4319123
Author: Alexey Bataev <a.bataev(a)outlook.com>
[SLP]Improve isFixedVectorShuffle and its use.
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 3% from 10824 to 11101 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O2 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-dce6c434ead3ccbaa67b8db2301b2a9fb4319123
cd investigate-llvm-dce6c434ead3ccbaa67b8db2301b2a9fb4319123
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach dce6c434ead3ccbaa67b8db2301b2a9fb4319123
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 7a7c059d867554e116244ad5639d05d75ed1a7cd
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit dce6c434ead3ccbaa67b8db2301b2a9fb4319123
Author: Alexey Bataev <a.bataev(a)outlook.com>
Date: Wed Nov 17 11:14:38 2021 -0800
[SLP]Improve isFixedVectorShuffle and its use.
Extended support for undefined source vector/extract indices/non-fixed
vector types, also no need to check for the parent of the extractelement
instructions with the constant indicies.
Differential Revision: https://reviews.llvm.org/D114121
---
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 67 +++++++++++++++-------
.../X86/alternate-int-inseltpoison.ll | 24 ++++----
.../Transforms/SLPVectorizer/X86/alternate-int.ll | 24 ++++----
3 files changed, 66 insertions(+), 49 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index e3d3d8992c23..4db630fbd063 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -327,7 +327,11 @@ static bool isCommutative(Instruction *I) {
/// TargetTransformInfo::getInstructionThroughput?
static Optional<TargetTransformInfo::ShuffleKind>
isFixedVectorShuffle(ArrayRef<Value *> VL, SmallVectorImpl<int> &Mask) {
- auto *EI0 = cast<ExtractElementInst>(VL[0]);
+ const auto *It =
+ find_if(VL, [](Value *V) { return isa<ExtractElementInst>(V); });
+ if (It == VL.end())
+ return None;
+ auto *EI0 = cast<ExtractElementInst>(*It);
if (isa<ScalableVectorType>(EI0->getVectorOperandType()))
return None;
unsigned Size =
@@ -336,33 +340,41 @@ isFixedVectorShuffle(ArrayRef<Value *> VL, SmallVectorImpl<int> &Mask) {
Value *Vec2 = nullptr;
enum ShuffleMode { Unknown, Select, Permute };
ShuffleMode CommonShuffleMode = Unknown;
+ Mask.assign(VL.size(), UndefMaskElem);
for (unsigned I = 0, E = VL.size(); I < E; ++I) {
+ // Undef can be represented as an undef element in a vector.
+ if (isa<UndefValue>(VL[I]))
+ continue;
auto *EI = cast<ExtractElementInst>(VL[I]);
+ if (isa<ScalableVectorType>(EI->getVectorOperandType()))
+ return None;
auto *Vec = EI->getVectorOperand();
+ // We can extractelement from undef or poison vector.
+ if (isa<UndefValue>(Vec))
+ continue;
// All vector operands must have the same number of vector elements.
if (cast<FixedVectorType>(Vec->getType())->getNumElements() != Size)
return None;
+ if (isa<UndefValue>(EI->getIndexOperand()))
+ continue;
auto *Idx = dyn_cast<ConstantInt>(EI->getIndexOperand());
if (!Idx)
return None;
// Undefined behavior if Idx is negative or >= Size.
- if (Idx->getValue().uge(Size)) {
- Mask.push_back(UndefMaskElem);
+ if (Idx->getValue().uge(Size))
continue;
- }
unsigned IntIdx = Idx->getValue().getZExtValue();
- Mask.push_back(IntIdx);
- // We can extractelement from undef or poison vector.
- if (isa<UndefValue>(Vec))
- continue;
+ Mask[I] = IntIdx;
// For correct shuffling we have to have at most 2 different vector operands
// in all extractelement instructions.
- if (!Vec1 || Vec1 == Vec)
+ if (!Vec1 || Vec1 == Vec) {
Vec1 = Vec;
- else if (!Vec2 || Vec2 == Vec)
+ } else if (!Vec2 || Vec2 == Vec) {
Vec2 = Vec;
- else
+ Mask[I] += Size;
+ } else {
return None;
+ }
if (CommonShuffleMode == Permute)
continue;
// If the extract index is not the same as the operation number, it is a
@@ -4414,15 +4426,19 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
bool IsGather) {
DenseMap<Value *, int> ExtractVectorsTys;
for (auto *V : VL) {
+ if (isa<UndefValue>(V))
+ continue;
// If all users of instruction are going to be vectorized and this
// instruction itself is not going to be vectorized, consider this
// instruction as dead and remove its cost from the final cost of the
// vectorized tree.
- if (!areAllUsersVectorized(cast<Instruction>(V), VectorizedVals) ||
- (IsGather && ScalarToTreeEntry.count(V)))
+ if (!areAllUsersVectorized(cast<Instruction>(V), VectorizedVals))
continue;
auto *EE = cast<ExtractElementInst>(V);
- unsigned Idx = *getExtractIndex(EE);
+ Optional<unsigned> EEIdx = getExtractIndex(EE);
+ if (!EEIdx)
+ continue;
+ unsigned Idx = *EEIdx;
if (TTIRef.getNumberOfParts(VecTy) !=
TTIRef.getNumberOfParts(EE->getVectorOperandType())) {
auto It =
@@ -4454,6 +4470,8 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
for (const auto &Data : ExtractVectorsTys) {
auto *EEVTy = cast<FixedVectorType>(Data.first->getType());
unsigned NumElts = VecTy->getNumElements();
+ if (Data.second % NumElts == 0)
+ continue;
if (TTIRef.getNumberOfParts(EEVTy) > TTIRef.getNumberOfParts(VecTy)) {
unsigned Idx = (Data.second / NumElts) * NumElts;
unsigned EENumElts = EEVTy->getNumElements();
@@ -4516,10 +4534,12 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E,
// broadcast.
return TTI->getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy);
}
- if (E->getOpcode() == Instruction::ExtractElement && allSameType(VL) &&
- allSameBlock(VL) &&
- !isa<ScalableVectorType>(
- cast<ExtractElementInst>(E->getMainOp())->getVectorOperandType())) {
+ if ((E->getOpcode() == Instruction::ExtractElement ||
+ all_of(E->Scalars,
+ [](Value *V) {
+ return isa<ExtractElementInst, UndefValue>(V);
+ })) &&
+ allSameType(VL)) {
// Check that gather of extractelements can be represented as just a
// shuffle of a single/two vectors the scalars are extracted from.
SmallVector<int> Mask;
@@ -5111,7 +5131,11 @@ bool BoUpSLP::isFullyVectorizableTinyTree(bool ForReduction) const {
[this](Value *V) { return EphValues.contains(V); }) &&
(allConstant(TE->Scalars) || isSplat(TE->Scalars) ||
TE->Scalars.size() < Limit ||
- (TE->getOpcode() == Instruction::ExtractElement &&
+ ((TE->getOpcode() == Instruction::ExtractElement ||
+ all_of(TE->Scalars,
+ [](Value *V) {
+ return isa<ExtractElementInst, UndefValue>(V);
+ })) &&
isFixedVectorShuffle(TE->Scalars, Mask)) ||
(TE->State == TreeEntry::NeedToGather &&
TE->getOpcode() == Instruction::Load && !TE->isAltShuffle()));
@@ -9183,8 +9207,9 @@ bool SLPVectorizerPass::vectorizeInsertElementInst(InsertElementInst *IEI,
SmallVector<Value *, 16> BuildVectorOpds;
SmallVector<int> Mask;
if (!findBuildAggregate(IEI, TTI, BuildVectorOpds, BuildVectorInsts) ||
- (llvm::all_of(BuildVectorOpds,
- [](Value *V) { return isa<ExtractElementInst>(V); }) &&
+ (llvm::all_of(
+ BuildVectorOpds,
+ [](Value *V) { return isa<ExtractElementInst, UndefValue>(V); }) &&
isFixedVectorShuffle(BuildVectorOpds, Mask)))
return false;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
index 8ab137cc2d7d..9c19a32b2f41 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
@@ -230,25 +230,21 @@ define <8 x i32> @ashr_shl_v8i32_const(<8 x i32> %a) {
define <8 x i32> @ashr_lshr_shl_v8i32(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: @ashr_lshr_shl_v8i32(
-; SSE-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 6
-; SSE-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
-; SSE-NEXT: [[B6:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 6
-; SSE-NEXT: [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
-; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; SSE-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[B:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; SSE-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], [[TMP2]]
; SSE-NEXT: [[TMP4:%.*]] = lshr <4 x i32> [[TMP1]], [[TMP2]]
; SSE-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; SSE-NEXT: [[TMP6:%.*]] = lshr <8 x i32> [[A]], [[B]]
; SSE-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
-; SSE-NEXT: [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
-; SSE-NEXT: [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
-; SSE-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
-; SSE-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
-; SSE-NEXT: [[R51:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 undef, i32 undef>
-; SSE-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R51]], i32 [[AB6]], i32 6
-; SSE-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
-; SSE-NEXT: ret <8 x i32> [[R7]]
+; SSE-NEXT: [[TMP8:%.*]] = shl <8 x i32> [[A]], [[B]]
+; SSE-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
+; SSE-NEXT: [[TMP10:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+; SSE-NEXT: [[TMP11:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; SSE-NEXT: [[R52:%.*]] = shufflevector <8 x i32> [[TMP10]], <8 x i32> [[TMP11]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 undef, i32 undef>
+; SSE-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; SSE-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R52]], <8 x i32> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
+; SSE-NEXT: ret <8 x i32> [[R71]]
;
; SLM-LABEL: @ashr_lshr_shl_v8i32(
; SLM-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
index 3af16bf404a3..783b50ae4b17 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
@@ -230,25 +230,21 @@ define <8 x i32> @ashr_shl_v8i32_const(<8 x i32> %a) {
define <8 x i32> @ashr_lshr_shl_v8i32(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: @ashr_lshr_shl_v8i32(
-; SSE-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 6
-; SSE-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
-; SSE-NEXT: [[B6:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 6
-; SSE-NEXT: [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
-; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; SSE-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[B:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; SSE-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], [[TMP2]]
; SSE-NEXT: [[TMP4:%.*]] = lshr <4 x i32> [[TMP1]], [[TMP2]]
; SSE-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; SSE-NEXT: [[TMP6:%.*]] = lshr <8 x i32> [[A]], [[B]]
; SSE-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
-; SSE-NEXT: [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
-; SSE-NEXT: [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
-; SSE-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
-; SSE-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
-; SSE-NEXT: [[R51:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 undef, i32 undef>
-; SSE-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R51]], i32 [[AB6]], i32 6
-; SSE-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
-; SSE-NEXT: ret <8 x i32> [[R7]]
+; SSE-NEXT: [[TMP8:%.*]] = shl <8 x i32> [[A]], [[B]]
+; SSE-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
+; SSE-NEXT: [[TMP10:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+; SSE-NEXT: [[TMP11:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; SSE-NEXT: [[R52:%.*]] = shufflevector <8 x i32> [[TMP10]], <8 x i32> [[TMP11]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 undef, i32 undef>
+; SSE-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; SSE-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R52]], <8 x i32> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
+; SSE-NEXT: ret <8 x i32> [[R71]]
;
; SLM-LABEL: @ashr_lshr_shl_v8i32(
; SLM-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
</cut>
3 years, 6 months
- 1
- 0
[TCWG CI] 453.povray slowed down by 3% after llvm: [llvm] Use range-based for loops (NFC)
by ci_notify＠linaro.org
After llvm commit f240e528cea25fd2a9ae01b1e1fe77f507ed7a2c
Author: Kazu Hirata <kazu(a)google.com>
[llvm] Use range-based for loops (NFC)
the following benchmarks slowed down by more than 2%:
- 453.povray slowed down by 3% from 4906 to 5047 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O2 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-f240e528cea25fd2a9ae01b1e1fe77f507ed7a2c
cd investigate-llvm-f240e528cea25fd2a9ae01b1e1fe77f507ed7a2c
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach f240e528cea25fd2a9ae01b1e1fe77f507ed7a2c
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach c572eb1ad9d8a528bcaff0160888aff31b1f4b5f
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit f240e528cea25fd2a9ae01b1e1fe77f507ed7a2c
Author: Kazu Hirata <kazu(a)google.com>
Date: Mon Nov 29 09:04:44 2021 -0800
[llvm] Use range-based for loops (NFC)
---
llvm/lib/CodeGen/MachinePipeliner.cpp | 7 ++---
.../CodeGen/SelectionDAG/ResourcePriorityQueue.cpp | 4 +--
llvm/lib/Object/ELFObjectFile.cpp | 4 +--
llvm/lib/ObjectYAML/COFFEmitter.cpp | 32 ++++++++++------------
llvm/lib/Passes/StandardInstrumentations.cpp | 4 +--
llvm/lib/ProfileData/InstrProf.cpp | 11 ++++----
llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp | 18 ++++++------
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 32 ++++++++++------------
8 files changed, 50 insertions(+), 62 deletions(-)
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 21be6718b7d9..8d6459a627fa 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1519,9 +1519,8 @@ static bool pred_L(SetVector<SUnit *> &NodeOrder,
SmallSetVector<SUnit *, 8> &Preds,
const NodeSet *S = nullptr) {
Preds.clear();
- for (SetVector<SUnit *>::iterator I = NodeOrder.begin(), E = NodeOrder.end();
- I != E; ++I) {
- for (const SDep &Pred : (*I)->Preds) {
+ for (const SUnit *SU : NodeOrder) {
+ for (const SDep &Pred : SU->Preds) {
if (S && S->count(Pred.getSUnit()) == 0)
continue;
if (ignoreDependence(Pred, true))
@@ -1530,7 +1529,7 @@ static bool pred_L(SetVector<SUnit *> &NodeOrder,
Preds.insert(Pred.getSUnit());
}
// Back-edges are predecessors with an anti-dependence.
- for (const SDep &Succ : (*I)->Succs) {
+ for (const SDep &Succ : SU->Succs) {
if (Succ.getKind() != SDep::Anti)
continue;
if (S && S->count(Succ.getSUnit()) == 0)
diff --git a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
index 55fe26eb64cd..2695ed36991c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
@@ -268,8 +268,8 @@ bool ResourcePriorityQueue::isResourceAvailable(SUnit *SU) {
// Now see if there are no other dependencies
// to instructions already in the packet.
- for (unsigned i = 0, e = Packet.size(); i != e; ++i)
- for (const SDep &Succ : Packet[i]->Succs) {
+ for (const SUnit *S : Packet)
+ for (const SDep &Succ : S->Succs) {
// Since we do not add pseudos to packets, might as well
// ignore order deps.
if (Succ.isCtrl())
diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
index 50035d6c7523..cf1f12d9a9a7 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -682,7 +682,7 @@ readDynsymVersionsImpl(const ELFFile<ELFT> &EF,
std::vector<VersionEntry> Ret;
size_t I = 0;
- for (auto It = Symbols.begin(), E = Symbols.end(); It != E; ++It) {
+ for (const ELFSymbolRef &Sym : Symbols) {
++I;
Expected<const typename ELFT::Versym *> VerEntryOrErr =
EF.template getEntry<typename ELFT::Versym>(*VerSec, I);
@@ -691,7 +691,7 @@ readDynsymVersionsImpl(const ELFFile<ELFT> &EF,
" from " + describe(EF, *VerSec) + ": " +
toString(VerEntryOrErr.takeError()));
- Expected<uint32_t> FlagsOrErr = It->getFlags();
+ Expected<uint32_t> FlagsOrErr = Sym.getFlags();
if (!FlagsOrErr)
return createError("unable to read flags for symbol with index " +
Twine(I) + ": " + toString(FlagsOrErr.takeError()));
diff --git a/llvm/lib/ObjectYAML/COFFEmitter.cpp b/llvm/lib/ObjectYAML/COFFEmitter.cpp
index 5f38ca13cfc2..66ad16db1ba4 100644
--- a/llvm/lib/ObjectYAML/COFFEmitter.cpp
+++ b/llvm/lib/ObjectYAML/COFFEmitter.cpp
@@ -476,29 +476,25 @@ static bool writeCOFF(COFFParser &CP, raw_ostream &OS) {
assert(OS.tell() == CP.SectionTableStart);
// Output section table.
- for (std::vector<COFFYAML::Section>::iterator i = CP.Obj.Sections.begin(),
- e = CP.Obj.Sections.end();
- i != e; ++i) {
- OS.write(i->Header.Name, COFF::NameSize);
- OS << binary_le(i->Header.VirtualSize)
- << binary_le(i->Header.VirtualAddress)
- << binary_le(i->Header.SizeOfRawData)
- << binary_le(i->Header.PointerToRawData)
- << binary_le(i->Header.PointerToRelocations)
- << binary_le(i->Header.PointerToLineNumbers)
- << binary_le(i->Header.NumberOfRelocations)
- << binary_le(i->Header.NumberOfLineNumbers)
- << binary_le(i->Header.Characteristics);
+ for (const COFFYAML::Section &S : CP.Obj.Sections) {
+ OS.write(S.Header.Name, COFF::NameSize);
+ OS << binary_le(S.Header.VirtualSize)
+ << binary_le(S.Header.VirtualAddress)
+ << binary_le(S.Header.SizeOfRawData)
+ << binary_le(S.Header.PointerToRawData)
+ << binary_le(S.Header.PointerToRelocations)
+ << binary_le(S.Header.PointerToLineNumbers)
+ << binary_le(S.Header.NumberOfRelocations)
+ << binary_le(S.Header.NumberOfLineNumbers)
+ << binary_le(S.Header.Characteristics);
}
assert(OS.tell() == CP.SectionTableStart + CP.SectionTableSize);
unsigned CurSymbol = 0;
StringMap<unsigned> SymbolTableIndexMap;
- for (std::vector<COFFYAML::Symbol>::iterator I = CP.Obj.Symbols.begin(),
- E = CP.Obj.Symbols.end();
- I != E; ++I) {
- SymbolTableIndexMap[I->Name] = CurSymbol;
- CurSymbol += 1 + I->Header.NumberOfAuxSymbols;
+ for (const COFFYAML::Symbol &Sym : CP.Obj.Symbols) {
+ SymbolTableIndexMap[Sym.Name] = CurSymbol;
+ CurSymbol += 1 + Sym.Header.NumberOfAuxSymbols;
}
// Output section data.
diff --git a/llvm/lib/Passes/StandardInstrumentations.cpp b/llvm/lib/Passes/StandardInstrumentations.cpp
index 8e6be6730ea4..27a6c519ff82 100644
--- a/llvm/lib/Passes/StandardInstrumentations.cpp
+++ b/llvm/lib/Passes/StandardInstrumentations.cpp
@@ -225,8 +225,8 @@ std::string doSystemDiff(StringRef Before, StringRef After,
return "Unable to read result.";
// Clean up.
- for (unsigned I = 0; I < NumFiles; ++I) {
- std::error_code EC = sys::fs::remove(FileName[I]);
+ for (const std::string &I : FileName) {
+ std::error_code EC = sys::fs::remove(I);
if (EC)
return "Unable to remove temporary file.";
}
diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp
index 1168ad27fe52..ab3487ecffe8 100644
--- a/llvm/lib/ProfileData/InstrProf.cpp
+++ b/llvm/lib/ProfileData/InstrProf.cpp
@@ -657,19 +657,18 @@ void InstrProfValueSiteRecord::merge(InstrProfValueSiteRecord &Input,
Input.sortByTargetValues();
auto I = ValueData.begin();
auto IE = ValueData.end();
- for (auto J = Input.ValueData.begin(), JE = Input.ValueData.end(); J != JE;
- ++J) {
- while (I != IE && I->Value < J->Value)
+ for (const InstrProfValueData &J : Input.ValueData) {
+ while (I != IE && I->Value < J.Value)
++I;
- if (I != IE && I->Value == J->Value) {
+ if (I != IE && I->Value == J.Value) {
bool Overflowed;
- I->Count = SaturatingMultiplyAdd(J->Count, Weight, I->Count, &Overflowed);
+ I->Count = SaturatingMultiplyAdd(J.Count, Weight, I->Count, &Overflowed);
if (Overflowed)
Warn(instrprof_error::counter_overflow);
++I;
continue;
}
- ValueData.insert(I, *J);
+ ValueData.insert(I, J);
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
index 43f0758f6598..8c3b9572201e 100644
--- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
@@ -476,10 +476,10 @@ namespace {
} // end anonymous namespace
static const NodeSet *node_class(GepNode *N, NodeSymRel &Rel) {
- for (NodeSymRel::iterator I = Rel.begin(), E = Rel.end(); I != E; ++I)
- if (I->count(N))
- return &*I;
- return nullptr;
+ for (const NodeSet &S : Rel)
+ if (S.count(N))
+ return &S;
+ return nullptr;
}
// Create an ordered pair of GepNode pointers. The pair will be used in
@@ -589,9 +589,8 @@ void HexagonCommonGEP::common() {
dbgs() << "{ " << I->first << ", " << I->second << " }\n";
dbgs() << "Gep equivalence classes:\n";
- for (NodeSymRel::iterator I = EqRel.begin(), E = EqRel.end(); I != E; ++I) {
+ for (const NodeSet &S : EqRel) {
dbgs() << '{';
- const NodeSet &S = *I;
for (NodeSet::const_iterator J = S.begin(), F = S.end(); J != F; ++J) {
if (J != S.begin())
dbgs() << ',';
@@ -604,8 +603,7 @@ void HexagonCommonGEP::common() {
// Create a projection from a NodeSet to the minimal element in it.
using ProjMap = std::map<const NodeSet *, GepNode *>;
ProjMap PM;
- for (NodeSymRel::iterator I = EqRel.begin(), E = EqRel.end(); I != E; ++I) {
- const NodeSet &S = *I;
+ for (const NodeSet &S : EqRel) {
GepNode *Min = *std::min_element(S.begin(), S.end(), NodeOrder);
std::pair<ProjMap::iterator,bool> Ins = PM.insert(std::make_pair(&S, Min));
(void)Ins;
@@ -1280,8 +1278,8 @@ bool HexagonCommonGEP::runOnFunction(Function &F) {
return false;
// For now bail out on C++ exception handling.
- for (Function::iterator A = F.begin(), Z = F.end(); A != Z; ++A)
- for (BasicBlock::iterator I = A->begin(), E = A->end(); I != E; ++I)
+ for (const BasicBlock &BB : F)
+ for (const Instruction &I : BB)
if (isa<InvokeInst>(I) || isa<LandingPadInst>(I))
return false;
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index c2ddfd6164f4..c35e67d6726f 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -130,10 +130,8 @@ VisitGlobalVariableForEmission(const GlobalVariable *GV,
for (unsigned i = 0, e = GV->getNumOperands(); i != e; ++i)
DiscoverDependentGlobals(GV->getOperand(i), Others);
- for (DenseSet<const GlobalVariable *>::iterator I = Others.begin(),
- E = Others.end();
- I != E; ++I)
- VisitGlobalVariableForEmission(*I, Order, Visited, Visiting);
+ for (const GlobalVariable *GV : Others)
+ VisitGlobalVariableForEmission(GV, Order, Visited, Visiting);
// Now we can visit ourself
Order.push_back(GV);
@@ -699,35 +697,33 @@ static bool useFuncSeen(const Constant *C,
void NVPTXAsmPrinter::emitDeclarations(const Module &M, raw_ostream &O) {
DenseMap<const Function *, bool> seenMap;
- for (Module::const_iterator FI = M.begin(), FE = M.end(); FI != FE; ++FI) {
- const Function *F = &*FI;
-
- if (F->getAttributes().hasFnAttr("nvptx-libcall-callee")) {
- emitDeclaration(F, O);
+ for (const Function &F : M) {
+ if (F.getAttributes().hasFnAttr("nvptx-libcall-callee")) {
+ emitDeclaration(&F, O);
continue;
}
- if (F->isDeclaration()) {
- if (F->use_empty())
+ if (F.isDeclaration()) {
+ if (F.use_empty())
continue;
- if (F->getIntrinsicID())
+ if (F.getIntrinsicID())
continue;
- emitDeclaration(F, O);
+ emitDeclaration(&F, O);
continue;
}
- for (const User *U : F->users()) {
+ for (const User *U : F.users()) {
if (const Constant *C = dyn_cast<Constant>(U)) {
if (usedInGlobalVarDef(C)) {
// The use is in the initialization of a global variable
// that is a function pointer, so print a declaration
// for the original function
- emitDeclaration(F, O);
+ emitDeclaration(&F, O);
break;
}
// Emit a declaration of this function if the function that
// uses this constant expr has already been seen.
if (useFuncSeen(C, seenMap)) {
- emitDeclaration(F, O);
+ emitDeclaration(&F, O);
break;
}
}
@@ -746,11 +742,11 @@ void NVPTXAsmPrinter::emitDeclarations(const Module &M, raw_ostream &O) {
// appearing in the module before the callee. so print out
// a declaration for the callee.
if (seenMap.find(caller) != seenMap.end()) {
- emitDeclaration(F, O);
+ emitDeclaration(&F, O);
break;
}
}
- seenMap[F] = true;
+ seenMap[&F] = true;
}
}
</cut>
3 years, 6 months
- 1
- 0
[TCWG CI] 458.sjeng slowed down by 5% after llvm: Reland "[LICM] Hoist LOAD without sinking the STORE"
by ci_notify＠linaro.org
After llvm commit 2cdc6f2ca62e83fec445114fbbe6276e9ab2a7d0
Author: Djordje Todorovic <djordje.todorovic(a)syrmia.com>
Reland "[LICM] Hoist LOAD without sinking the STORE"
the following benchmarks slowed down by more than 2%:
- 458.sjeng slowed down by 5% from 13781 to 14482 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-2cdc6f2ca62e83fec445114fbbe6276e9ab2a7d0
cd investigate-llvm-2cdc6f2ca62e83fec445114fbbe6276e9ab2a7d0
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 2cdc6f2ca62e83fec445114fbbe6276e9ab2a7d0
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 47616c8855fd44abcbd7cad3f7d8153d28db347b
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 2cdc6f2ca62e83fec445114fbbe6276e9ab2a7d0
Author: Djordje Todorovic <djordje.todorovic(a)syrmia.com>
Date: Thu Dec 2 03:40:00 2021 -0800
Reland "[LICM] Hoist LOAD without sinking the STORE"
When doing load/store promotion within LICM, if we
cannot prove that it is safe to sink the store we won't
hoist the load, even though we can prove the load could
be dereferenced and moved outside the loop. This patch
implements the load promotion by moving it in the loop
preheader by inserting proper PHI in the loop. The store
is kept as is in the loop. By doing this, we avoid doing
the load from a memory location in each iteration.
Please consider this small example:
loop {
var = *ptr;
if (var) break;
*ptr= var + 1;
}
After this patch, it will be:
var0 = *ptr;
loop {
var1 = phi (var0, var2);
if (var1) break;
var2 = var1 + 1;
*ptr = var2;
}
This addresses some problems from [0].
[0] https://bugs.llvm.org/show_bug.cgi?id=51193
Differential revision: https://reviews.llvm.org/D113289
---
llvm/include/llvm/Transforms/Utils/SSAUpdater.h | 4 +++
llvm/lib/Transforms/Scalar/LICM.cpp | 41 +++++++++++++++++-----
llvm/lib/Transforms/Utils/SSAUpdater.cpp | 3 ++
.../Transforms/InstMerge/st_sink_bugfix_22613.ll | 6 ++--
.../Transforms/LICM/hoist-load-without-store.ll | 5 +--
llvm/test/Transforms/LICM/promote-capture.ll | 8 +++--
.../Transforms/LICM/scalar-promote-memmodel.ll | 8 +++--
.../Transforms/LICM/scalar-promote-opaque-ptrs.ll | 8 +++--
llvm/test/Transforms/LICM/scalar-promote.ll | 8 +++--
9 files changed, 65 insertions(+), 26 deletions(-)
diff --git a/llvm/include/llvm/Transforms/Utils/SSAUpdater.h b/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
index 22b2295cc9d7..c233e3dc168e 100644
--- a/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
+++ b/llvm/include/llvm/Transforms/Utils/SSAUpdater.h
@@ -169,6 +169,10 @@ public:
/// Called to update debug info associated with the instruction.
virtual void updateDebugInfo(Instruction *I) const {}
+
+ /// Return false if a sub-class wants to keep one of the loads/stores
+ /// after the SSA construction.
+ virtual bool shouldDelete(Instruction *I) const { return true; }
};
} // end namespace llvm
diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp b/llvm/lib/Transforms/Scalar/LICM.cpp
index 0d52448efb2b..6f97f3e93123 100644
--- a/llvm/lib/Transforms/Scalar/LICM.cpp
+++ b/llvm/lib/Transforms/Scalar/LICM.cpp
@@ -1860,6 +1860,7 @@ class LoopPromoter : public LoadAndStorePromoter {
bool UnorderedAtomic;
AAMDNodes AATags;
ICFLoopSafetyInfo &SafetyInfo;
+ bool CanInsertStoresInExitBlocks;
// We're about to add a use of V in a loop exit block. Insert an LCSSA phi
// (if legal) if doing so would add an out-of-loop use to an instruction
@@ -1886,12 +1887,13 @@ public:
SmallVectorImpl<MemoryAccess *> &MSSAIP, PredIteratorCache &PIC,
MemorySSAUpdater *MSSAU, LoopInfo &li, DebugLoc dl,
Align Alignment, bool UnorderedAtomic, const AAMDNodes &AATags,
- ICFLoopSafetyInfo &SafetyInfo)
+ ICFLoopSafetyInfo &SafetyInfo, bool CanInsertStoresInExitBlocks)
: LoadAndStorePromoter(Insts, S), SomePtr(SP), PointerMustAliases(PMA),
LoopExitBlocks(LEB), LoopInsertPts(LIP), MSSAInsertPts(MSSAIP),
PredCache(PIC), MSSAU(MSSAU), LI(li), DL(std::move(dl)),
Alignment(Alignment), UnorderedAtomic(UnorderedAtomic), AATags(AATags),
- SafetyInfo(SafetyInfo) {}
+ SafetyInfo(SafetyInfo),
+ CanInsertStoresInExitBlocks(CanInsertStoresInExitBlocks) {}
bool isInstInList(Instruction *I,
const SmallVectorImpl<Instruction *> &) const override {
@@ -1903,7 +1905,7 @@ public:
return PointerMustAliases.count(Ptr);
}
- void doExtraRewritesBeforeFinalDeletion() override {
+ void insertStoresInLoopExitBlocks() {
// Insert stores after in the loop exit blocks. Each exit block gets a
// store of the live-out values that feed them. Since we've already told
// the SSA updater about the defs in the loop and the preheader
@@ -1937,10 +1939,21 @@ public:
}
}
+ void doExtraRewritesBeforeFinalDeletion() override {
+ if (CanInsertStoresInExitBlocks)
+ insertStoresInLoopExitBlocks();
+ }
+
void instructionDeleted(Instruction *I) const override {
SafetyInfo.removeInstruction(I);
MSSAU->removeMemoryAccess(I);
}
+
+ bool shouldDelete(Instruction *I) const override {
+ if (isa<StoreInst>(I))
+ return CanInsertStoresInExitBlocks;
+ return true;
+ }
};
bool isNotCapturedBeforeOrInLoop(const Value *V, const Loop *L,
@@ -2039,6 +2052,7 @@ bool llvm::promoteLoopAccessesToScalars(
bool DereferenceableInPH = false;
bool SafeToInsertStore = false;
+ bool FoundLoadToPromote = false;
SmallVector<Instruction *, 64> LoopUses;
@@ -2086,6 +2100,7 @@ bool llvm::promoteLoopAccessesToScalars(
SawUnorderedAtomic |= Load->isAtomic();
SawNotAtomic |= !Load->isAtomic();
+ FoundLoadToPromote = true;
Align InstAlignment = Load->getAlign();
@@ -2197,13 +2212,20 @@ bool llvm::promoteLoopAccessesToScalars(
}
}
- // If we've still failed to prove we can sink the store, give up.
- if (!SafeToInsertStore)
+ // If we've still failed to prove we can sink the store, hoist the load
+ // only, if possible.
+ if (!SafeToInsertStore && !FoundLoadToPromote)
+ // If we cannot hoist the load either, give up.
return false;
- // Otherwise, this is safe to promote, lets do it!
- LLVM_DEBUG(dbgs() << "LICM: Promoting value stored to in loop: " << *SomePtr
- << '\n');
+ // Lets do the promotion!
+ if (SafeToInsertStore)
+ LLVM_DEBUG(dbgs() << "LICM: Promoting load/store of the value: " << *SomePtr
+ << '\n');
+ else
+ LLVM_DEBUG(dbgs() << "LICM: Promoting load of the value: " << *SomePtr
+ << '\n');
+
ORE->emit([&]() {
return OptimizationRemark(DEBUG_TYPE, "PromoteLoopAccessesToScalar",
LoopUses[0])
@@ -2222,7 +2244,8 @@ bool llvm::promoteLoopAccessesToScalars(
SSAUpdater SSA(&NewPHIs);
LoopPromoter Promoter(SomePtr, LoopUses, SSA, PointerMustAliases, ExitBlocks,
InsertPts, MSSAInsertPts, PIC, MSSAU, *LI, DL,
- Alignment, SawUnorderedAtomic, AATags, *SafetyInfo);
+ Alignment, SawUnorderedAtomic, AATags, *SafetyInfo,
+ SafeToInsertStore);
// Set up the preheader to have a definition of the value. It is the live-out
// value from the preheader that uses in the loop will use.
diff --git a/llvm/lib/Transforms/Utils/SSAUpdater.cpp b/llvm/lib/Transforms/Utils/SSAUpdater.cpp
index 5893ce15b129..7d9992176658 100644
--- a/llvm/lib/Transforms/Utils/SSAUpdater.cpp
+++ b/llvm/lib/Transforms/Utils/SSAUpdater.cpp
@@ -446,6 +446,9 @@ void LoadAndStorePromoter::run(const SmallVectorImpl<Instruction *> &Insts) {
// Now that everything is rewritten, delete the old instructions from the
// function. They should all be dead now.
for (Instruction *User : Insts) {
+ if (!shouldDelete(User))
+ continue;
+
// If this is a load that still has uses, then the load must have been added
// as a live value in the SSAUpdate data structure for a block (e.g. because
// the loaded value was stored later). In this case, we need to recursively
diff --git a/llvm/test/Transforms/InstMerge/st_sink_bugfix_22613.ll b/llvm/test/Transforms/InstMerge/st_sink_bugfix_22613.ll
index 48882eca44cc..e5a75cca8ee7 100644
--- a/llvm/test/Transforms/InstMerge/st_sink_bugfix_22613.ll
+++ b/llvm/test/Transforms/InstMerge/st_sink_bugfix_22613.ll
@@ -5,12 +5,12 @@ target triple = "x86_64-unknown-linux-gnu"
; RUN: opt -O2 -S < %s | FileCheck %s
; CHECK-LABEL: main
-; CHECK: if.end
-; CHECK: store
; CHECK: memset
; CHECK: if.then
; CHECK: store
-; CHECK: memset
+; CHECK: if.end
+; CHECK: store
+; CHECK: store
@d = common global i32 0, align 4
@b = common global i32 0, align 4
diff --git a/llvm/test/Transforms/LICM/hoist-load-without-store.ll b/llvm/test/Transforms/LICM/hoist-load-without-store.ll
index b464f6b7328d..275a53172737 100644
--- a/llvm/test/Transforms/LICM/hoist-load-without-store.ll
+++ b/llvm/test/Transforms/LICM/hoist-load-without-store.ll
@@ -18,10 +18,11 @@ define dso_local void @f(i32* nocapture %ptr, i32 %n) {
; CHECK-NEXT: [[CMP7:%.*]] = icmp slt i32 0, [[N:%.*]]
; CHECK-NEXT: br i1 [[CMP7]], label [[FOR_BODY_LR_PH:%.*]], label [[CLEANUP1:%.*]]
; CHECK: for.body.lr.ph:
+; CHECK-NEXT: [[PTR_PROMOTED:%.*]] = load i32, i32* [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[I_08:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[IF_END:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[PTR_PROMOTED]], [[FOR_BODY_LR_PH]] ], [ 1, [[IF_END:%.*]] ]
+; CHECK-NEXT: [[I_08:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[IF_END]] ]
; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END]], label [[FOR_BODY_CLEANUP1_CRIT_EDGE:%.*]]
; CHECK: if.end:
diff --git a/llvm/test/Transforms/LICM/promote-capture.ll b/llvm/test/Transforms/LICM/promote-capture.ll
index 1a2603d1c986..945036e6e175 100644
--- a/llvm/test/Transforms/LICM/promote-capture.ll
+++ b/llvm/test/Transforms/LICM/promote-capture.ll
@@ -111,17 +111,19 @@ define void @test_captured_before_loop(i32 %len) {
; CHECK-NEXT: [[COUNT:%.*]] = alloca i32, align 4
; CHECK-NEXT: store i32 0, i32* [[COUNT]], align 4
; CHECK-NEXT: call void @capture(i32* [[COUNT]])
+; CHECK-NEXT: [[COUNT_PROMOTED:%.*]] = load i32, i32* [[COUNT]], align 4
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LATCH:%.*]] ]
+; CHECK-NEXT: [[C_INC2:%.*]] = phi i32 [ [[COUNT_PROMOTED]], [[ENTRY:%.*]] ], [ [[C_INC1:%.*]], [[LATCH:%.*]] ]
+; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[I_NEXT:%.*]], [[LATCH]] ]
; CHECK-NEXT: [[COND:%.*]] = call i1 @cond(i32 [[I]])
; CHECK-NEXT: br i1 [[COND]], label [[IF:%.*]], label [[LATCH]]
; CHECK: if:
-; CHECK-NEXT: [[C:%.*]] = load i32, i32* [[COUNT]], align 4
-; CHECK-NEXT: [[C_INC:%.*]] = add i32 [[C]], 1
+; CHECK-NEXT: [[C_INC:%.*]] = add i32 [[C_INC2]], 1
; CHECK-NEXT: store i32 [[C_INC]], i32* [[COUNT]], align 4
; CHECK-NEXT: br label [[LATCH]]
; CHECK: latch:
+; CHECK-NEXT: [[C_INC1]] = phi i32 [ [[C_INC]], [[IF]] ], [ [[C_INC2]], [[LOOP]] ]
; CHECK-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[I_NEXT]], [[LEN:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[EXIT:%.*]], label [[LOOP]]
diff --git a/llvm/test/Transforms/LICM/scalar-promote-memmodel.ll b/llvm/test/Transforms/LICM/scalar-promote-memmodel.ll
index c3bae731fb6b..33076b39e908 100644
--- a/llvm/test/Transforms/LICM/scalar-promote-memmodel.ll
+++ b/llvm/test/Transforms/LICM/scalar-promote-memmodel.ll
@@ -11,19 +11,21 @@ define void @bar(i32 %n, i32 %b) nounwind uwtable ssp {
; CHECK-LABEL: @bar(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[B:%.*]], 0
+; CHECK-NEXT: [[G_PROMOTED:%.*]] = load i32, i32* @g, align 4
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
-; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC5:%.*]], [[FOR_INC:%.*]] ]
+; CHECK-NEXT: [[INC2:%.*]] = phi i32 [ [[G_PROMOTED]], [[ENTRY:%.*]] ], [ [[INC1:%.*]], [[FOR_INC:%.*]] ]
+; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC5:%.*]], [[FOR_INC]] ]
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_0]], [[N:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
; CHECK: for.body:
; CHECK-NEXT: br i1 [[TOBOOL]], label [[FOR_INC]], label [[IF_THEN:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* @g, align 4
-; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1
+; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[INC2]], 1
; CHECK-NEXT: store i32 [[INC]], i32* @g, align 4
; CHECK-NEXT: br label [[FOR_INC]]
; CHECK: for.inc:
+; CHECK-NEXT: [[INC1]] = phi i32 [ [[INC]], [[IF_THEN]] ], [ [[INC2]], [[FOR_BODY]] ]
; CHECK-NEXT: [[INC5]] = add nsw i32 [[I_0]], 1
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end:
diff --git a/llvm/test/Transforms/LICM/scalar-promote-opaque-ptrs.ll b/llvm/test/Transforms/LICM/scalar-promote-opaque-ptrs.ll
index da4bae936dc1..b239b6fb0296 100644
--- a/llvm/test/Transforms/LICM/scalar-promote-opaque-ptrs.ll
+++ b/llvm/test/Transforms/LICM/scalar-promote-opaque-ptrs.ll
@@ -314,17 +314,19 @@ define i32 @test7bad() {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOCAL:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @capture(ptr [[LOCAL]])
+; CHECK-NEXT: [[LOCAL_PROMOTED:%.*]] = load i32, ptr [[LOCAL]], align 4
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[ELSE:%.*]] ]
-; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[LOCAL]], align 4
-; CHECK-NEXT: [[X2:%.*]] = call i32 @opaque(i32 [[X]])
+; CHECK-NEXT: [[X22:%.*]] = phi i32 [ [[LOCAL_PROMOTED]], [[ENTRY:%.*]] ], [ [[X21:%.*]], [[ELSE:%.*]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[NEXT:%.*]], [[ELSE]] ]
+; CHECK-NEXT: [[X2:%.*]] = call i32 @opaque(i32 [[X22]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X2]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[ELSE]]
; CHECK: if:
; CHECK-NEXT: store i32 [[X2]], ptr [[LOCAL]], align 4
; CHECK-NEXT: br label [[ELSE]]
; CHECK: else:
+; CHECK-NEXT: [[X21]] = phi i32 [ [[X2]], [[IF]] ], [ [[X22]], [[LOOP]] ]
; CHECK-NEXT: [[NEXT]] = add i32 [[J]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[NEXT]], 0
; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[LOOP]]
diff --git a/llvm/test/Transforms/LICM/scalar-promote.ll b/llvm/test/Transforms/LICM/scalar-promote.ll
index 290e990f8513..c064edb8cd93 100644
--- a/llvm/test/Transforms/LICM/scalar-promote.ll
+++ b/llvm/test/Transforms/LICM/scalar-promote.ll
@@ -315,17 +315,19 @@ define i32 @test7bad() {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOCAL:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @capture(i32* [[LOCAL]])
+; CHECK-NEXT: [[LOCAL_PROMOTED:%.*]] = load i32, i32* [[LOCAL]], align 4
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[ELSE:%.*]] ]
-; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[LOCAL]], align 4
-; CHECK-NEXT: [[X2:%.*]] = call i32 @opaque(i32 [[X]])
+; CHECK-NEXT: [[X22:%.*]] = phi i32 [ [[LOCAL_PROMOTED]], [[ENTRY:%.*]] ], [ [[X21:%.*]], [[ELSE:%.*]] ]
+; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[NEXT:%.*]], [[ELSE]] ]
+; CHECK-NEXT: [[X2:%.*]] = call i32 @opaque(i32 [[X22]])
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X2]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[ELSE]]
; CHECK: if:
; CHECK-NEXT: store i32 [[X2]], i32* [[LOCAL]], align 4
; CHECK-NEXT: br label [[ELSE]]
; CHECK: else:
+; CHECK-NEXT: [[X21]] = phi i32 [ [[X2]], [[IF]] ], [ [[X22]], [[LOOP]] ]
; CHECK-NEXT: [[NEXT]] = add i32 [[J]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[NEXT]], 0
; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[LOOP]]
</cut>
3 years, 6 months
- 1
- 0
[ACTIVITY] week ending Dec. 5 2021
by Alex Bennée
VirtIO Initiative ([STR-9])
===========================
- synced up on [AX_XDP task with Akashi-san]
- synced on rust-vmm
[AX_XDP task with Akashi-san]
<https://linaro.atlassian.net/browse/STR-68>
vhost-device maintainer effort ([UM-196])
- started looking at https://github.com/rust-vmm/vhost-device/pull/4
QEMU Upstream Work ([UM-2])
===========================
- posted [PULL for 6.2 0/8] more tcg, plugin, test and build fixes
Message-Id: <20211129171449.4176301-1-alex.bennee(a)linaro.org>
- commented on Re: Follow-up on the CXL discussion at OFTC Message-Id:
<20211119015207.62fhk5mjmvaj5nz4(a)intel.com> to see if I can unblock
- posted [RFC PATCH] blog post: how to get your new feature
up-streamed Message-Id:
<20211126203319.3298089-1-alex.bennee(a)linaro.org>
- posted [PATCH for 6.2?] Revert "vga: don't abort when adding a
duplicate isa-vga device" Message-Id:
<20211202164929.1119036-1-alex.bennee(a)linaro.org>
Upstream MTTCG tests ([QEMU-52])
- posted [kvm-unit-tests PATCH v9 0/9] MTTCG sanity tests for ARM
Message-Id: <20211202115352.951548-1-alex.bennee(a)linaro.org>
[QEMU-52] <https://linaro.atlassian.net/browse/QEMU-52>
Other
=====
- wrote [RFC PATCH 0/2] insn plugin tweaks for measuring frequency
Message-Id: <20211203144421.1445232-1-alex.bennee(a)linaro.org>
- might make a good basis for a TCG plugins blog post
Completed Reviews [2/2]
=======================
[PATCH] tests/plugin/syscall.c: fix compiler warnings
Message-Id: <20211128011551.2115468-1-juro.bystricky(a)intel.com>
[PATCH for-6.2? 0/2] arm_gicv3: Fix handling of LPIs in list registers
Message-Id: <20211126163915.1048353-2-peter.maydell(a)linaro.org>
Current Review Queue
====================
TODO [PATCH-4.16 v2] xen/efi: Fix Grub2 boot on arm64
Message-Id: <20211104141206.25153-1-luca.fancellu(a)arm.com>
===============================================================================================================
TODO [PATCH] cpu-models-x86.rst: Tidy up a couple of things
Message-Id: <20211015100718.17828-1-pbonzini(a)redhat.com>
===================================================================================================================
TODO [PATCH 00/16] fdt: Make OF_BOARD a boolean option
Message-Id: <20211013010120.96851-1-sjg(a)chromium.org>
===========================================================================================================
TODO [PATCH v4 00/41] linux-user: Streamline handling of SIGSEGV
Message-Id: <20211006172307.780893-1-richard.henderson(a)linaro.org>
==================================================================================================================================
--
Alex Bennée
3 years, 7 months
- 1
- 0
[ACTIVITY] report week ending 3 Dec
by Peter Maydell
Progress:
* UM-2 [QEMU upstream maintainership]
- Code review: worked through some of the backlog and accumulated
a list of series to take once the tree reopens for 7.0
- Wrote and sent some cleanup patches relating to the qemu-common.h
header file
- Fixed a bug where we miscalculated the length for TLB range
invalidations
* QEMU-420 [GICv4 emulation]
- Found the problem with PCI passthrough in my nested test setup:
apparently virtio PCI devices need an extra command line argument
to get them to honour the presence of an IOMMU. Everything is
now working and I've put some notes about the setup into
https://linaro.atlassian.net/browse/QEMU-447
- started to implement the GICv4 redistributor changes
-- PMM
3 years, 7 months
- 1
- 0
[ACTIVITY] week ending Nov. 28 2021
by Alex Bennée
VirtIO Initiative ([STR-9])
===========================
- [this weeks sync], topics on AF_XDP, virtio-video and
virtio-watchdog
[upstream rust-vmm sync meeting]
<https://etherpad.opendev.org/p/rust-vmm-sync-2021&sa=D&source=calendar&ust=…>
QEMU Upstream Work ([UM-2])
===========================
- posted [PATCH for 6.2 v2 0/7] more tcg, plugin, test and build fixes
Message-Id: <20211125154144.2904741-1-alex.bennee(a)linaro.org>
Upstream MTTCG tests ([QEMU-52])
- posted [kvm-unit-tests PATCH v8 00/10] MTTCG sanity tests for ARM
Message-Id: <20211118184650.661575-1-alex.bennee(a)linaro.org>
[mttcg tests to current state and fixed up]
<https://github.com/stsquad/qemu/tree/mttcg/current-tests-v8>
Other
=====
- renewal feedback
Completed Reviews [2/2]
=======================
[PATCH v2 0/3] KVM: qemu patches for few KVM features I developed
Message-Id: <20211101132300.192584-1-mlevitsk(a)redhat.com>
[PATCH v2] hw/intc/arm_gicv3: Update cached state after LPI state changes
Message-Id: <20211124202005.989935-1-peter.maydell(a)linaro.org>
Absences
========
- off 2 days sick
Current Review Queue
====================
TODO [PATCH-4.16 v2] xen/efi: Fix Grub2 boot on arm64
Message-Id: <20211104141206.25153-1-luca.fancellu(a)arm.com>
===============================================================================================================
TODO [PATCH] cpu-models-x86.rst: Tidy up a couple of things
Message-Id: <20211015100718.17828-1-pbonzini(a)redhat.com>
===================================================================================================================
TODO [PATCH 00/16] fdt: Make OF_BOARD a boolean option
Message-Id: <20211013010120.96851-1-sjg(a)chromium.org>
===========================================================================================================
TODO [PATCH v4 00/41] linux-user: Streamline handling of SIGSEGV
Message-Id: <20211006172307.780893-1-richard.henderson(a)linaro.org>
==================================================================================================================================
--
Alex Bennée
3 years, 7 months
- 1
- 0
[ACTIVITY] report week ending 26 Nov
by Peter Maydell
Progress:
* QEMU-420 [GICv4 emulation]
- Tracked down and fixed a bug in our ITS emulation which would
(intermittently?) result in a Linux guest reporting "irq 54:
nobody cared" and hanging, because we were not correctly
recalculating the highest priority pending interrupt when the
guest acknowledged a pending LPI. This fix will go into 6.2.
- Set up a test environment for GICv4 work -- because the major
feature of GICv4 is support for directly injecting interrupts
into a VM, the test setup needs to be nested virtualization,
where an outer L1 guest runs on pure emulated QEMU, the inner
L2 guest uses KVM (as provided by L1), and we pass a PCI device
(emulated by QEMU) through from L1 to L2. I think I have this
correctly set up now, but...
- ...the L2 guest hangs because it apparently never sees an
interrupt from the passed-through PCI device. This implies a
bug in our current GICv3 emulation somewhere: need to track
this down before starting in on GICv4 work.
- Separately, I found through code inspection a bug where we
do the wrong thing in the non-passthrough case when the L1 guest
sets a virtual interrupt for the L2 guest in the GIC list
registers and that interrupt has an ID > 1023 (ie it is an LPI).
We got this wrong both for acknowledging and ending an interrupt,
so the two bugs cancel each other out except that we don't set
the vCPU priority and so the L2 guest might get an unexpected
interrupt while it was servicing the LPI. Patches sent.
-- PMM
3 years, 7 months
- 1
- 0
[TCWG CI] 433.milc slowed down by 5% after llvm: [AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
by ci_notify＠linaro.org
After llvm commit d7e03df719464354b20a845b7853be57da863924
Author: Jay Foad <jay.foad(a)amd.com>
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
the following benchmarks slowed down by more than 2%:
- 433.milc slowed down by 5% from 12335 to 12997 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O2 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-d7e03df719464354b20a845b7853be57da863924
cd investigate-llvm-d7e03df719464354b20a845b7853be57da863924
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach d7e03df719464354b20a845b7853be57da863924
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 8a52bd82e36855b3ad842f2535d0c78a97db55dc
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit d7e03df719464354b20a845b7853be57da863924
Author: Jay Foad <jay.foad(a)amd.com>
Date: Fri Nov 12 18:02:58 2021 +0000
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
Select SelectionDAG ops smul_lohi/umul_lohi to
v_mad_i64_i32/v_mad_u64_u32 respectively, with an addend of 0.
v_mul_lo, v_mul_hi and v_mad_i64/u64 are all quarter-rate instructions
so it is better to use one instruction than two.
Further improvements are possible to make better use of the addend
operand, but this is already a strict improvement over what we have
now.
Differential Revision: https://reviews.llvm.org/D113986
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 29 +
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 1 +
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 49 +
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 +
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 23 +
llvm/lib/Target/AMDGPU/SIISelLowering.h | 1 +
.../AMDGPU/atomic_optimizations_global_pointer.ll | 104 +-
.../AMDGPU/atomic_optimizations_local_pointer.ll | 108 +-
llvm/test/CodeGen/AMDGPU/bypass-div.ll | 1064 +++++++++-----------
llvm/test/CodeGen/AMDGPU/llvm.mulo.ll | 178 ++--
llvm/test/CodeGen/AMDGPU/mad_64_32.ll | 110 +-
llvm/test/CodeGen/AMDGPU/mul.ll | 55 +-
llvm/test/CodeGen/AMDGPU/mul_int24.ll | 9 +-
llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll | 24 +-
llvm/test/CodeGen/AMDGPU/udiv.ll | 358 +++----
llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll | 126 +--
llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 16 +-
17 files changed, 1126 insertions(+), 1130 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 2e571ad01c1c..8236e6672247 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -654,6 +654,9 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
SelectMAD_64_32(N);
return;
}
+ case ISD::SMUL_LOHI:
+ case ISD::UMUL_LOHI:
+ return SelectMUL_LOHI(N);
case ISD::CopyToReg: {
const SITargetLowering& Lowering =
*static_cast<const SITargetLowering*>(getTargetLowering());
@@ -1013,6 +1016,32 @@ void AMDGPUDAGToDAGISel::SelectMAD_64_32(SDNode *N) {
CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
}
+// We need to handle this here because tablegen doesn't support matching
+// instructions with multiple outputs.
+void AMDGPUDAGToDAGISel::SelectMUL_LOHI(SDNode *N) {
+ SDLoc SL(N);
+ bool Signed = N->getOpcode() == ISD::SMUL_LOHI;
+ unsigned Opc = Signed ? AMDGPU::V_MAD_I64_I32_e64 : AMDGPU::V_MAD_U64_U32_e64;
+
+ SDValue Zero = CurDAG->getTargetConstant(0, SL, MVT::i64);
+ SDValue Clamp = CurDAG->getTargetConstant(0, SL, MVT::i1);
+ SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Zero, Clamp};
+ SDNode *Mad = CurDAG->getMachineNode(Opc, SL, N->getVTList(), Ops);
+ if (!SDValue(N, 0).use_empty()) {
+ SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32);
+ SDNode *Lo = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SL,
+ MVT::i32, SDValue(Mad, 0), Sub0);
+ ReplaceUses(SDValue(N, 0), SDValue(Lo, 0));
+ }
+ if (!SDValue(N, 1).use_empty()) {
+ SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32);
+ SDNode *Hi = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, SL,
+ MVT::i32, SDValue(Mad, 0), Sub1);
+ ReplaceUses(SDValue(N, 1), SDValue(Hi, 0));
+ }
+ CurDAG->RemoveDeadNode(N);
+}
+
bool AMDGPUDAGToDAGISel::isDSOffsetLegal(SDValue Base, unsigned Offset) const {
if (!isUInt<16>(Offset))
return false;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index 74aff9e406c9..d638d9877a9b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -235,6 +235,7 @@ private:
void SelectUADDO_USUBO(SDNode *N);
void SelectDIV_SCALE(SDNode *N);
void SelectMAD_64_32(SDNode *N);
+ void SelectMUL_LOHI(SDNode *N);
void SelectFMA_W_CHAIN(SDNode *N);
void SelectFMUL_W_CHAIN(SDNode *N);
SDNode *getBFE32(bool IsSigned, const SDLoc &DL, SDValue Val, uint32_t Offset,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 523fa2d3724b..54177564afbc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -594,6 +594,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::SRL);
setTargetDAGCombine(ISD::TRUNCATE);
setTargetDAGCombine(ISD::MUL);
+ setTargetDAGCombine(ISD::SMUL_LOHI);
+ setTargetDAGCombine(ISD::UMUL_LOHI);
setTargetDAGCombine(ISD::MULHU);
setTargetDAGCombine(ISD::MULHS);
setTargetDAGCombine(ISD::SELECT);
@@ -3462,6 +3464,50 @@ SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
return DAG.getSExtOrTrunc(Mul, DL, VT);
}
+SDValue
+AMDGPUTargetLowering::performMulLoHiCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ if (N->getValueType(0) != MVT::i32)
+ return SDValue();
+
+ SelectionDAG &DAG = DCI.DAG;
+ SDLoc DL(N);
+
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+
+ // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
+ // in the source into any_extends if the result of the mul is truncated. Since
+ // we can assume the high bits are whatever we want, use the underlying value
+ // to avoid the unknown high bits from interfering.
+ if (N0.getOpcode() == ISD::ANY_EXTEND)
+ N0 = N0.getOperand(0);
+ if (N1.getOpcode() == ISD::ANY_EXTEND)
+ N1 = N1.getOperand(0);
+
+ // Try to use two fast 24-bit multiplies (one for each half of the result)
+ // instead of one slow extending multiply.
+ unsigned LoOpcode, HiOpcode;
+ if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
+ N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
+ N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
+ LoOpcode = AMDGPUISD::MUL_U24;
+ HiOpcode = AMDGPUISD::MULHI_U24;
+ } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
+ N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
+ N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
+ LoOpcode = AMDGPUISD::MUL_I24;
+ HiOpcode = AMDGPUISD::MULHI_I24;
+ } else {
+ return SDValue();
+ }
+
+ SDValue Lo = DAG.getNode(LoOpcode, DL, MVT::i32, N0, N1);
+ SDValue Hi = DAG.getNode(HiOpcode, DL, MVT::i32, N0, N1);
+ DCI.CombineTo(N, Lo, Hi);
+ return SDValue(N, 0);
+}
+
SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
EVT VT = N->getValueType(0);
@@ -4103,6 +4149,9 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
return performTruncateCombine(N, DCI);
case ISD::MUL:
return performMulCombine(N, DCI);
+ case ISD::SMUL_LOHI:
+ case ISD::UMUL_LOHI:
+ return performMulLoHiCombine(N, DCI);
case ISD::MULHS:
return performMulhsCombine(N, DCI);
case ISD::MULHU:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 03632ac18598..daaca8737c5d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -91,6 +91,7 @@ protected:
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 519c5b936536..02440044d6e2 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -809,6 +809,11 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SMULO, MVT::i64, Custom);
setOperationAction(ISD::UMULO, MVT::i64, Custom);
+ if (Subtarget->hasMad64_32()) {
+ setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
+ setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
+ }
+
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
@@ -4691,6 +4696,9 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SMULO:
case ISD::UMULO:
return lowerXMULO(Op, DAG);
+ case ISD::SMUL_LOHI:
+ case ISD::UMUL_LOHI:
+ return lowerXMUL_LOHI(Op, DAG);
case ISD::DYNAMIC_STACKALLOC:
return LowerDYNAMIC_STACKALLOC(Op, DAG);
}
@@ -5304,6 +5312,21 @@ SDValue SITargetLowering::lowerXMULO(SDValue Op, SelectionDAG &DAG) const {
return DAG.getMergeValues({ Result, Overflow }, SL);
}
+SDValue SITargetLowering::lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const {
+ if (Op->isDivergent()) {
+ // Select to V_MAD_[IU]64_[IU]32.
+ return Op;
+ }
+ if (Subtarget->hasSMulHi()) {
+ // Expand to S_MUL_I32 + S_MUL_HI_[IU]32.
+ return SDValue();
+ }
+ // The multiply is uniform but we would have to use V_MUL_HI_[IU]32 to
+ // calculate the high part, so we might as well do the whole thing with
+ // V_MAD_[IU]64_[IU]32.
+ return Op;
+}
+
SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
if (!Subtarget->isTrapHandlerEnabled() ||
Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 1e48c96ad3c8..ea6ca3f48827 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -135,6 +135,7 @@ private:
SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 49f05fceb8ed..4ad774db6686 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -818,32 +818,29 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX8-NEXT: s_mov_b32 s13, s7
-; GFX8-NEXT: s_mul_i32 s7, s1, s6
-; GFX8-NEXT: s_mul_i32 s6, s0, s6
+; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s0, v0, 0
+; GFX8-NEXT: s_mul_i32 s6, s1, s6
; GFX8-NEXT: s_mov_b32 s15, 0xf000
; GFX8-NEXT: s_mov_b32 s14, -1
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: s_mov_b32 s13, s7
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, s6, v1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_add_x2 v[0:1], off, s[12:15], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: .LBB4_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mul_lo_u32 v0, s1, v2
-; GFX8-NEXT: v_mul_hi_u32 v3, s0, v2
+; GFX8-NEXT: v_mul_lo_u32 v4, s1, v2
+; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s0, v2, 0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
-; GFX8-NEXT: v_mul_lo_u32 v1, s0, v2
-; GFX8-NEXT: s_mov_b32 s7, 0xf000
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v1
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT: s_endpgm
;
@@ -878,17 +875,16 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX9-NEXT: .LBB4_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s2, v2, 0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; GFX9-NEXT: v_add_u32_e32 v1, v4, v3
-; GFX9-NEXT: v_mov_b32_e32 v2, s1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm
;
@@ -927,14 +923,13 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1064-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1064-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s2, v2, 0
; GFX1064-NEXT: v_readfirstlane_b32 s0, v0
; GFX1064-NEXT: v_readfirstlane_b32 s1, v1
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_mov_b32 s6, -1
-; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1064-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1064-NEXT: v_add_co_u32 v0, vcc, s0, v2
; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s1, v1, vcc
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -974,14 +969,13 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1032-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1032-NEXT: v_mad_u64_u32 v[2:3], s0, s2, v2, 0
; GFX1032-NEXT: v_readfirstlane_b32 s0, v0
; GFX1032-NEXT: v_readfirstlane_b32 s1, v1
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_mov_b32 s6, -1
-; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1032-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1032-NEXT: v_add_co_u32 v0, vcc_lo, s0, v2
; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -1955,32 +1949,29 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX8-NEXT: s_mov_b32 s12, s6
; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
; GFX8-NEXT: v_mov_b32_e32 v0, s6
-; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX8-NEXT: s_mov_b32 s13, s7
-; GFX8-NEXT: s_mul_i32 s7, s1, s6
-; GFX8-NEXT: s_mul_i32 s6, s0, s6
+; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s0, v0, 0
+; GFX8-NEXT: s_mul_i32 s6, s1, s6
; GFX8-NEXT: s_mov_b32 s15, 0xf000
; GFX8-NEXT: s_mov_b32 s14, -1
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: s_mov_b32 s13, s7
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, s6, v1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_atomic_sub_x2 v[0:1], off, s[12:15], 0 glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1_vol
; GFX8-NEXT: .LBB10_2:
; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mul_lo_u32 v0, s1, v2
-; GFX8-NEXT: v_mul_hi_u32 v3, s0, v2
+; GFX8-NEXT: v_mul_lo_u32 v4, s1, v2
+; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s0, v2, 0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
-; GFX8-NEXT: v_mul_lo_u32 v1, s0, v2
-; GFX8-NEXT: s_mov_b32 s7, 0xf000
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v1
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v2
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1
-; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
+; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT: s_endpgm
;
@@ -2015,17 +2006,16 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX9-NEXT: .LBB10_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s2, v2, 0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; GFX9-NEXT: v_add_u32_e32 v1, v4, v3
-; GFX9-NEXT: v_mov_b32_e32 v2, s1
-; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm
;
@@ -2064,14 +2054,13 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1064-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1064-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s2, v2, 0
; GFX1064-NEXT: v_readfirstlane_b32 s0, v0
; GFX1064-NEXT: v_readfirstlane_b32 s1, v1
; GFX1064-NEXT: s_mov_b32 s7, 0x31016000
; GFX1064-NEXT: s_mov_b32 s6, -1
-; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1064-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s0, v2
; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s1, v1, vcc
; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -2111,14 +2100,13 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 addrspace
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1032-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1032-NEXT: v_mad_u64_u32 v[2:3], s0, s2, v2, 0
; GFX1032-NEXT: v_readfirstlane_b32 s0, v0
; GFX1032-NEXT: v_readfirstlane_b32 s1, v1
; GFX1032-NEXT: s_mov_b32 s7, 0x31016000
; GFX1032-NEXT: s_mov_b32 s6, -1
-; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1032-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v2
; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 455f9de836ba..bf91960537a4 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -954,15 +954,13 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 %additive
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz .LBB5_2
; GFX8-NEXT: ; %bb.1:
-; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: s_bcnt1_i32_b64 s8, s[6:7]
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX8-NEXT: s_mul_i32 s7, s3, s6
-; GFX8-NEXT: s_mul_i32 s6, s2, s6
+; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[6:7], s2, v0, 0
+; GFX8-NEXT: s_mul_i32 s6, s3, s8
; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, s6, v1
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
@@ -971,18 +969,17 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 %additive
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, s0
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: v_mul_lo_u32 v0, s3, v2
-; GFX8-NEXT: v_mul_hi_u32 v3, s2, v2
; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s2, v2, 0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
-; GFX8-NEXT: v_mul_lo_u32 v1, s2, v2
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v1
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT: s_endpgm
;
@@ -1012,19 +1009,18 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 %additive
; GFX9-NEXT: .LBB5_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[2:3], s2, v2, 0
; GFX9-NEXT: s_mov_b32 s4, s0
-; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: s_mov_b32 s5, s1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; GFX9-NEXT: v_add_u32_e32 v1, v4, v3
-; GFX9-NEXT: v_mov_b32_e32 v2, s1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v1, vcc
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm
;
@@ -1057,13 +1053,12 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 %additive
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1064-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1064-NEXT: v_mad_u64_u32 v[2:3], s[2:3], s2, v2, 0
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1064-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1064-NEXT: v_add_co_u32 v0, vcc, s2, v2
; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s4, v1, vcc
@@ -1098,13 +1093,12 @@ define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 %additive
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1032-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1032-NEXT: v_mad_u64_u32 v[2:3], s2, s2, v2, 0
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1032-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1032-NEXT: v_add_co_u32 v0, vcc_lo, s2, v2
; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
@@ -2133,15 +2127,13 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 %subitive
; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8-NEXT: s_cbranch_execz .LBB12_2
; GFX8-NEXT: ; %bb.1:
-; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: s_bcnt1_i32_b64 s8, s[6:7]
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX8-NEXT: s_mul_i32 s7, s3, s6
-; GFX8-NEXT: s_mul_i32 s6, s2, s6
+; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[6:7], s2, v0, 0
+; GFX8-NEXT: s_mul_i32 s6, s3, s8
; GFX8-NEXT: v_mov_b32_e32 v3, 0
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, s7, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, s6, v1
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
@@ -2150,18 +2142,17 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 %subitive
; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, s0
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: v_mul_lo_u32 v0, s3, v2
-; GFX8-NEXT: v_mul_hi_u32 v3, s2, v2
; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX8-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s2, v2, 0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
-; GFX8-NEXT: v_mul_lo_u32 v1, s2, v2
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v3, s1
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v1
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v2
; GFX8-NEXT: s_mov_b32 s7, 0xf000
; GFX8-NEXT: s_mov_b32 s6, -1
-; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
+; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX8-NEXT: s_endpgm
;
@@ -2191,19 +2182,18 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 %subitive
; GFX9-NEXT: .LBB12_2:
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[2:3], s2, v2, 0
; GFX9-NEXT: s_mov_b32 s4, s0
-; GFX9-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: s_mov_b32 s5, s1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; GFX9-NEXT: v_add_u32_e32 v1, v4, v3
-; GFX9-NEXT: v_mov_b32_e32 v2, s1
-; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm
;
@@ -2236,13 +2226,12 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 %subitive
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1064-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1064-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1064-NEXT: v_mad_u64_u32 v[2:3], s[2:3], s2, v2, 0
; GFX1064-NEXT: v_readfirstlane_b32 s2, v0
; GFX1064-NEXT: v_readfirstlane_b32 s4, v1
; GFX1064-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1064-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1064-NEXT: v_sub_co_u32 v0, vcc, s2, v2
; GFX1064-NEXT: s_mov_b32 s2, -1
; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s4, v1, vcc
@@ -2277,13 +2266,12 @@ define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 %subitive
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v2
-; GFX1032-NEXT: v_mul_lo_u32 v2, s2, v2
+; GFX1032-NEXT: v_mul_lo_u32 v4, s3, v2
+; GFX1032-NEXT: v_mad_u64_u32 v[2:3], s2, s2, v2, 0
; GFX1032-NEXT: v_readfirstlane_b32 s2, v0
; GFX1032-NEXT: v_readfirstlane_b32 s4, v1
; GFX1032-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3
+; GFX1032-NEXT: v_add_nc_u32_e32 v1, v3, v4
; GFX1032-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v2
; GFX1032-NEXT: s_mov_b32 s2, -1
; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
index 4ff9f6159cae..907ba8dd3086 100644
--- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll
+++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
@@ -16,119 +16,107 @@ define i64 @sdiv64(i64 %a, i64 %b) {
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_2
; GFX9-NEXT: ; %bb.1:
-; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
-; GFX9-NEXT: v_xor_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4
-; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v2
-; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v3
-; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, 0, v2
-; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v3, vcc
-; GFX9-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
-; GFX9-NEXT: v_rcp_f32_e32 v5, v5
+; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v3
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc
+; GFX9-NEXT: v_xor_b32_e32 v10, v3, v9
+; GFX9-NEXT: v_xor_b32_e32 v11, v2, v9
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v11
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v10
+; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, 0, v11
+; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v10, vcc
+; GFX9-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
+; GFX9-NEXT: v_rcp_f32_e32 v2, v2
; GFX9-NEXT: v_mov_b32_e32 v14, 0
-; GFX9-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
-; GFX9-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
-; GFX9-NEXT: v_trunc_f32_e32 v6, v6
-; GFX9-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GFX9-NEXT: v_mul_lo_u32 v11, v7, v6
-; GFX9-NEXT: v_mul_lo_u32 v9, v8, v5
-; GFX9-NEXT: v_mul_hi_u32 v10, v7, v5
-; GFX9-NEXT: v_mul_lo_u32 v12, v7, v5
-; GFX9-NEXT: v_add3_u32 v9, v10, v11, v9
-; GFX9-NEXT: v_mul_lo_u32 v10, v5, v9
-; GFX9-NEXT: v_mul_hi_u32 v11, v5, v12
-; GFX9-NEXT: v_mul_hi_u32 v13, v5, v9
-; GFX9-NEXT: v_mul_hi_u32 v15, v6, v9
-; GFX9-NEXT: v_mul_lo_u32 v9, v6, v9
-; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
-; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12
-; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12
-; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v10, v13
-; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v11, v12, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v15, v14, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9
-; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
-; GFX9-NEXT: v_mul_lo_u32 v9, v7, v6
-; GFX9-NEXT: v_mul_lo_u32 v8, v8, v5
-; GFX9-NEXT: v_mul_hi_u32 v10, v7, v5
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, v5
-; GFX9-NEXT: v_add3_u32 v8, v10, v9, v8
-; GFX9-NEXT: v_mul_lo_u32 v11, v5, v8
-; GFX9-NEXT: v_mul_hi_u32 v12, v5, v7
-; GFX9-NEXT: v_mul_hi_u32 v13, v5, v8
-; GFX9-NEXT: v_mul_hi_u32 v10, v6, v7
-; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7
-; GFX9-NEXT: v_mul_hi_u32 v9, v6, v8
-; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
-; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
-; GFX9-NEXT: v_mul_lo_u32 v8, v6, v8
-; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v11, v7
-; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v12, v10, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v14, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
-; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7
-; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v8, vcc
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v7
-; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7
-; GFX9-NEXT: v_mul_lo_u32 v8, v0, v6
-; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5
-; GFX9-NEXT: v_mul_hi_u32 v10, v0, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
-; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7
-; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
-; GFX9-NEXT: v_mul_lo_u32 v10, v1, v5
-; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
-; GFX9-NEXT: v_mul_hi_u32 v11, v1, v6
-; GFX9-NEXT: v_mul_lo_u32 v6, v1, v6
-; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v14, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
-; GFX9-NEXT: v_mul_lo_u32 v8, v3, v5
-; GFX9-NEXT: v_mul_lo_u32 v9, v2, v6
-; GFX9-NEXT: v_mul_hi_u32 v10, v2, v5
-; GFX9-NEXT: v_mul_lo_u32 v11, v2, v5
-; GFX9-NEXT: v_add3_u32 v8, v10, v9, v8
-; GFX9-NEXT: v_sub_u32_e32 v9, v1, v8
-; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v11
-; GFX9-NEXT: v_subb_co_u32_e64 v9, s[4:5], v9, v3, vcc
-; GFX9-NEXT: v_sub_co_u32_e64 v10, s[4:5], v0, v2
-; GFX9-NEXT: v_subbrev_co_u32_e64 v9, s[4:5], 0, v9, s[4:5]
-; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, v10, s[4:5]
-; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 2, v5
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
-; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v6, s[4:5]
-; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_add_co_u32_e64 v12, s[4:5], 1, v5
-; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
-; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v6, s[4:5]
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v8, v6
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v6, 0
+; GFX9-NEXT: v_mul_lo_u32 v5, v7, v12
+; GFX9-NEXT: v_mul_hi_u32 v13, v6, v2
+; GFX9-NEXT: v_add3_u32 v5, v3, v5, v4
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0
+; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v13, v3
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v12, v2, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v12, v5, 0
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v13, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v15, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v6, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v12, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, v7, v12
+; GFX9-NEXT: v_mul_lo_u32 v5, v8, v13
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v13, 0
+; GFX9-NEXT: v_add3_u32 v5, v3, v4, v5
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v12, v5, 0
+; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v13, v5, 0
+; GFX9-NEXT: v_mul_hi_u32 v15, v13, v2
+; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v2, 0
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v15, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v8, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v13, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v12, v3, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v4
+; GFX9-NEXT: v_xor_b32_e32 v6, v0, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v4, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v3, 0
+; GFX9-NEXT: v_mul_hi_u32 v7, v6, v2
+; GFX9-NEXT: v_xor_b32_e32 v5, v5, v4
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v2, 0
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, v3, 0
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v7, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v8, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v14, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v10, v2
+; GFX9-NEXT: v_mul_lo_u32 v8, v11, v3
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v11, v2, 0
+; GFX9-NEXT: v_add3_u32 v1, v1, v8, v7
+; GFX9-NEXT: v_sub_u32_e32 v7, v5, v1
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v6, v0
+; GFX9-NEXT: v_subb_co_u32_e64 v6, s[4:5], v7, v10, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v7, s[4:5], v0, v11
+; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[4:5], 0, v6, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v11
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v7, s[4:5], 2, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v8, s[4:5], 0, v3, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v10
+; GFX9-NEXT: v_add_co_u32_e64 v12, s[4:5], 1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v11
+; GFX9-NEXT: v_addc_co_u32_e64 v13, s[4:5], 0, v3, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v10
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v12, v10, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v13, v11, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-NEXT: v_xor_b32_e32 v2, v7, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v12, v7, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v13, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, v4, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v2
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v1, v2
@@ -183,106 +171,94 @@ define i64 @udiv64(i64 %a, i64 %b) {
; GFX9-NEXT: ; %bb.1:
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, v3
-; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, 0, v2
-; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e32 v10, vcc, 0, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, 0, v3, vcc
; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GFX9-NEXT: v_rcp_f32_e32 v4, v4
-; GFX9-NEXT: v_mov_b32_e32 v12, 0
+; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
-; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
-; GFX9-NEXT: v_mul_lo_u32 v9, v7, v4
-; GFX9-NEXT: v_mul_hi_u32 v10, v6, v4
-; GFX9-NEXT: v_mul_lo_u32 v11, v6, v4
-; GFX9-NEXT: v_add3_u32 v8, v10, v8, v9
-; GFX9-NEXT: v_mul_hi_u32 v9, v4, v11
-; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8
-; GFX9-NEXT: v_mul_hi_u32 v13, v4, v8
-; GFX9-NEXT: v_mul_hi_u32 v14, v5, v8
-; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8
-; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10
-; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
-; GFX9-NEXT: v_mul_lo_u32 v13, v5, v11
-; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v13
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v14, v12, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
-; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
-; GFX9-NEXT: v_mul_hi_u32 v9, v6, v4
-; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
-; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7
-; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
-; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
-; GFX9-NEXT: v_mul_hi_u32 v13, v4, v7
-; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6
-; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
-; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7
-; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
-; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7
-; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v12, vcc
-; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
-; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v10, v8
+; GFX9-NEXT: v_mul_lo_u32 v7, v11, v9
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v9, 0
+; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7
+; GFX9-NEXT: v_mul_hi_u32 v12, v9, v4
+; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v9, v7, 0
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v12, v5
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v8, v4, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v6, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v8, v7, 0
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v12, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v14, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5
-; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4
-; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5
-; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5
-; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
-; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v9, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, v8, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v10, v14
+; GFX9-NEXT: v_mul_lo_u32 v7, v11, v12
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v10, v12, 0
+; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7
+; GFX9-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v14, v7, 0
+; GFX9-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v12, v7, 0
+; GFX9-NEXT: v_mul_hi_u32 v11, v12, v4
+; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v14, v4, 0
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v11, v7
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
-; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
-; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v8
-; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v12, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v10, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4
-; GFX9-NEXT: v_mul_lo_u32 v7, v2, v5
-; GFX9-NEXT: v_mul_hi_u32 v8, v2, v4
</cut>
3 years, 7 months
- 2
- 1
[ACTIVITY] week ending 21 Nov 2021
by Richard Henderson
[UM-2]
* release work
* revived some 6month old ppc fpu fixes
* reviews: loongarch, riscv, watchpoints, gdbstub.
r~
3 years, 7 months
- 1
- 0
[ACTIVITY] week ending Nov. 21 2021
by Alex Bennée
VirtIO Initiative ([STR-9])
===========================
- posted Initial thoughts for test scenarios for AF_XDP epic
Message-Id: <87k0h5v6ju.fsf(a)linaro.org>
vhost-device maintainer effort ([UM-196])
- more review
- [did some more noodling with rust] to get comfortable with generics
[UM-196] <https://linaro.atlassian.net/browse/UM-196>
[vhost-device crate] <https://github.com/rust-vmm/vhost-device>
[did some more noodling with rust]
<https://gitlab.com/stsquad/softfloat.rs>
QEMU Upstream Work ([UM-2])
===========================
- posted [PULL for 6.2 0/7] misc build and test fixes Message-Id:
<20211116162515.4100231-1-alex.bennee(a)linaro.org>
- posted [RFC PATCH] tests/avocado: fix tcg_plugin mem access count
test Message-Id: <20211117095448.136558-1-alex.bennee(a)linaro.org>
- posted Re: [RFC PATCH] plugins/meson.build: fix linker issue with
weird paths (for v6.2?) Message-Id:
<20211117111924.179776-1-alex.bennee(a)linaro.org>
- posted Re: [PATCH v2 1/3] icount: preserve cflags when custom tb is
about to execute Message-Id: <87h7cbw1tx.fsf(a)linaro.org>
- posted [RFC PATCH] gdbstub: handle a potentially racing TaskState
Message-Id: <20211119145124.942390-1-alex.bennee(a)linaro.org>
[UM-2] <https://linaro.atlassian.net/browse/UM-2>
Upstream MTTCG tests ([QEMU-52])
- posted [kvm-unit-tests PATCH v3 0/3] GIC ITS tests Message-Id:
<20211112114734.3058678-1-alex.bennee(a)linaro.org>
- posted [kvm-unit-tests PATCH v8 00/10] MTTCG sanity tests for ARM
Message-Id: <20211118184650.661575-1-alex.bennee(a)linaro.org>
[QEMU-52] <https://linaro.atlassian.net/browse/QEMU-52>
[mttcg tests to current state and fixed up]
<https://github.com/stsquad/qemu/tree/mttcg/current-tests-v8>
Completed Reviews [2/2]
=======================
[PATCH v2 0/3] Some watchpoint-related patches
Message-Id: <163662450348.125458.5494710452733592356.stgit@pasha-ThinkPad-X280>
[PATCH 0/5] Update linux-headers + NOIRQ support for KVM gdbstub
Message-Id: <20211111110604.207376-1-pbonzini(a)redhat.com>
Absences
========
- none
Current Review Queue
====================
TODO [PATCH-4.16 v2] xen/efi: Fix Grub2 boot on arm64
Message-Id: <20211104141206.25153-1-luca.fancellu(a)arm.com>
===============================================================================================================
TODO [PATCH] cpu-models-x86.rst: Tidy up a couple of things
Message-Id: <20211015100718.17828-1-pbonzini(a)redhat.com>
===================================================================================================================
TODO [PATCH 00/16] fdt: Make OF_BOARD a boolean option
Message-Id: <20211013010120.96851-1-sjg(a)chromium.org>
===========================================================================================================
TODO [PATCH v4 00/41] linux-user: Streamline handling of SIGSEGV
Message-Id: <20211006172307.780893-1-richard.henderson(a)linaro.org>
==================================================================================================================================
--
Alex Bennée
3 years, 7 months
- 1
- 0
[ACTIVITY] report week ending 19 Nov
by Peter Maydell
Progress (short week, 3 days)
* UM-2 [QEMU upstream maintainership]
- Still trying to sort out the regression of booting EL3 guest
code on the imx7 board. I got most of the way through prototyping
a cleanup which would fix this, but then spotted that the
highbank board has a more awkward-to-fix similar problem.
We're going to revert the PSCI emulation change for 6.2 so we
can take the time to get the cleanup right and land it in 7.0.
- Usual patch accumulation, review, etc during release cycle
-- PMM
3 years, 7 months
- 1
- 0
[TCWG CI] Regression caused by gcc: tree-optimization/102880 - make PHI-OPT recognize more CFGs
by ci_notify＠linaro.org
[TCWG CI] Regression caused by gcc: tree-optimization/102880 - make PHI-OPT recognize more CFGs:
commit f98f373dd822b35c52356b753d528924e9f89678
Author: Richard Biener <rguenther(a)suse.de>
tree-optimization/102880 - make PHI-OPT recognize more CFGs
Results regressed to
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
21059
# First few build errors in logs:
# 00:20:13 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c:2521:1: error: definition in block 22 does not dominate use in block 21
# 00:20:13 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c:2521:1: internal compiler error: verify_ssa failed
# 00:20:13 make[6]: *** [scripts/Makefile.build:280: drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.o] Error 1
# 00:20:20 make[5]: *** [scripts/Makefile.build:497: drivers/net/wireless/realtek/rtlwifi/rtl8192se] Error 2
# 00:24:02 make[4]: *** [scripts/Makefile.build:497: drivers/net/wireless/realtek/rtlwifi] Error 2
# 00:24:02 make[3]: *** [scripts/Makefile.build:497: drivers/net/wireless/realtek] Error 2
# 00:24:02 make[2]: *** [scripts/Makefile.build:497: drivers/net/wireless] Error 2
# 00:25:21 drivers/staging/comedi/drivers/addi_apci_3120.c:1117:1: error: definition in block 10 does not dominate use in block 11
# 00:25:21 drivers/staging/comedi/drivers/addi_apci_3120.c:1117:1: internal compiler error: verify_ssa failed
# 00:25:22 make[4]: *** [scripts/Makefile.build:280: drivers/staging/comedi/drivers/addi_apci_3120.o] Error 1
from
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1:
-5
# build_abe qemu:
-2
# linux_n_obj:
28893
# linux build successful:
all
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_kernel/gnu-master-arm-lts-allmodconfig
First_bad build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-lts-allmodc…
Last_good build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-lts-allmodc…
Baseline build: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-lts-allmodc…
Even more details: https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-lts-allmodc…
Reproduce builds:
<cut>
mkdir investigate-gcc-f98f373dd822b35c52356b753d528924e9f89678
cd investigate-gcc-f98f373dd822b35c52356b753d528924e9f89678
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-lts-allmodc… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-lts-allmodc… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_kernel-gnu-bisect-gnu-master-arm-lts-allmodc… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_kernel-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach f98f373dd822b35c52356b753d528924e9f89678
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach d699f03720fce57b319276226ac4a463a8538e9f
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit f98f373dd822b35c52356b753d528924e9f89678
Author: Richard Biener <rguenther(a)suse.de>
Date: Mon Nov 15 15:19:36 2021 +0100
tree-optimization/102880 - make PHI-OPT recognize more CFGs
This allows extra edges into the middle BB for the PHI-OPT
transforms using replace_phi_edge_with_variable that do not
end up moving stmts from that middle BB. This avoids regressing
gcc.dg/tree-ssa/ssa-hoist-4.c with the actual fix for PR102880
where CFG cleanup has the choice to remove two forwarders and
picks "the wrong" leading to
if (a > b) /
/\ /
/ <BB>
/ |
# PHI <a, b>
rather than
if (a > b) |
/\ |
<BB> \ |
/ \ |
# PHI <a, b, b>
but it's relatively straight-forward to support extra edges
into the middle-BB in paths ending in replace_phi_edge_with_variable
and that do not require moving stmts. That's because we really
only want to remove the edge from the condition to the middle BB.
Of course actually doing that means updating dominators in non-trival
ways which is why I kept the original code for the single edge
case and simply defer to CFG cleanup by adjusting the condition for
the complicated case.
The testcase needs to be a GIMPLE one since it's quite unreliable
to produce the desired CFG.
2021-11-15 Richard Biener <rguenther(a)suse.de>
PR tree-optimization/102880
* tree-ssa-phiopt.c (tree_ssa_phiopt_worker): Push
single_pred (bb1) condition to places that really need it.
(match_simplify_replacement): Likewise.
(value_replacement): Likewise.
(replace_phi_edge_with_variable): Deal with extra edges
into the middle BB.
* gcc.dg/tree-ssa/phi-opt-26.c: New testcase.
---
gcc/testsuite/gcc.dg/tree-ssa/phi-opt-26.c | 31 +++++++++++++
gcc/tree-ssa-phiopt.c | 71 +++++++++++++++++-------------
2 files changed, 72 insertions(+), 30 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-26.c b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-26.c
new file mode 100644
index 00000000000..21aa66e38b8
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-26.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fgimple -fdump-tree-phiopt1" } */
+
+int __GIMPLE (ssa,startwith("phiopt"))
+foo (int a, int b, int flag)
+{
+ int res;
+
+ __BB(2):
+ if (flag_2(D) != 0)
+ goto __BB6;
+ else
+ goto __BB4;
+
+ __BB(4):
+ if (a_3(D) > b_4(D))
+ goto __BB7;
+ else
+ goto __BB6;
+
+ __BB(6):
+ goto __BB7;
+
+ __BB(7):
+ res_1 = __PHI (__BB4: a_3(D), __BB6: b_4(D));
+ return res_1;
+}
+
+/* We should be able to detect MAX despite the extra edge into
+ the middle BB. */
+/* { dg-final { scan-tree-dump "MAX" "phiopt1" } } */
diff --git a/gcc/tree-ssa-phiopt.c b/gcc/tree-ssa-phiopt.c
index 173ac835ca6..6b22f6bedd4 100644
--- a/gcc/tree-ssa-phiopt.c
+++ b/gcc/tree-ssa-phiopt.c
@@ -220,7 +220,6 @@ tree_ssa_phiopt_worker (bool do_store_elim, bool do_hoist_loads, bool early_p)
/* If either bb1's succ or bb2 or bb2's succ is non NULL. */
if (EDGE_COUNT (bb1->succs) == 0
- || bb2 == NULL
|| EDGE_COUNT (bb2->succs) == 0)
continue;
@@ -276,14 +275,14 @@ tree_ssa_phiopt_worker (bool do_store_elim, bool do_hoist_loads, bool early_p)
|| (e1->flags & EDGE_FALLTHRU) == 0)
continue;
- /* Also make sure that bb1 only have one predecessor and that it
- is bb. */
- if (!single_pred_p (bb1)
- || single_pred (bb1) != bb)
- continue;
-
if (do_store_elim)
{
+ /* Also make sure that bb1 only have one predecessor and that it
+ is bb. */
+ if (!single_pred_p (bb1)
+ || single_pred (bb1) != bb)
+ continue;
+
/* bb1 is the middle block, bb2 the join block, bb the split block,
e1 the fallthrough edge from bb1 to bb2. We can't do the
optimization if the join block has more than two predecessors. */
@@ -328,10 +327,11 @@ tree_ssa_phiopt_worker (bool do_store_elim, bool do_hoist_loads, bool early_p)
node. */
gcc_assert (arg0 != NULL_TREE && arg1 != NULL_TREE);
- gphi *newphi = factor_out_conditional_conversion (e1, e2, phi,
- arg0, arg1,
- cond_stmt);
- if (newphi != NULL)
+ gphi *newphi;
+ if (single_pred_p (bb1)
+ && (newphi = factor_out_conditional_conversion (e1, e2, phi,
+ arg0, arg1,
+ cond_stmt)))
{
phi = newphi;
/* factor_out_conditional_conversion may create a new PHI in
@@ -350,12 +350,14 @@ tree_ssa_phiopt_worker (bool do_store_elim, bool do_hoist_loads, bool early_p)
early_p))
cfgchanged = true;
else if (!early_p
+ && single_pred_p (bb1)
&& cond_removal_in_builtin_zero_pattern (bb, bb1, e1, e2,
phi, arg0, arg1))
cfgchanged = true;
else if (minmax_replacement (bb, bb1, e1, e2, phi, arg0, arg1))
cfgchanged = true;
- else if (spaceship_replacement (bb, bb1, e1, e2, phi, arg0, arg1))
+ else if (single_pred_p (bb1)
+ && spaceship_replacement (bb, bb1, e1, e2, phi, arg0, arg1))
cfgchanged = true;
}
}
@@ -386,7 +388,6 @@ replace_phi_edge_with_variable (basic_block cond_block,
edge e, gphi *phi, tree new_tree)
{
basic_block bb = gimple_bb (phi);
- basic_block block_to_remove;
gimple_stmt_iterator gsi;
tree phi_result = PHI_RESULT (phi);
@@ -422,28 +423,33 @@ replace_phi_edge_with_variable (basic_block cond_block,
SET_USE (PHI_ARG_DEF_PTR (phi, e->dest_idx), new_tree);
/* Remove the empty basic block. */
+ edge edge_to_remove;
if (EDGE_SUCC (cond_block, 0)->dest == bb)
+ edge_to_remove = EDGE_SUCC (cond_block, 1);
+ else
+ edge_to_remove = EDGE_SUCC (cond_block, 0);
+ if (EDGE_COUNT (edge_to_remove->dest->preds) == 1)
{
- EDGE_SUCC (cond_block, 0)->flags |= EDGE_FALLTHRU;
- EDGE_SUCC (cond_block, 0)->flags &= ~(EDGE_TRUE_VALUE | EDGE_FALSE_VALUE);
- EDGE_SUCC (cond_block, 0)->probability = profile_probability::always ();
+ e->flags |= EDGE_FALLTHRU;
+ e->flags &= ~(EDGE_TRUE_VALUE | EDGE_FALSE_VALUE);
+ e->probability = profile_probability::always ();
+ delete_basic_block (edge_to_remove->dest);
- block_to_remove = EDGE_SUCC (cond_block, 1)->dest;
+ /* Eliminate the COND_EXPR at the end of COND_BLOCK. */
+ gsi = gsi_last_bb (cond_block);
+ gsi_remove (&gsi, true);
}
else
{
- EDGE_SUCC (cond_block, 1)->flags |= EDGE_FALLTHRU;
- EDGE_SUCC (cond_block, 1)->flags
- &= ~(EDGE_TRUE_VALUE | EDGE_FALSE_VALUE);
- EDGE_SUCC (cond_block, 1)->probability = profile_probability::always ();
-
- block_to_remove = EDGE_SUCC (cond_block, 0)->dest;
+ /* If there are other edges into the middle block make
+ CFG cleanup deal with the edge removal to avoid
+ updating dominators here in a non-trivial way. */
+ gcond *cond = as_a <gcond *> (last_stmt (cond_block));
+ if (edge_to_remove->flags & EDGE_TRUE_VALUE)
+ gimple_cond_make_false (cond);
+ else
+ gimple_cond_make_true (cond);
}
- delete_basic_block (block_to_remove);
-
- /* Eliminate the COND_EXPR at the end of COND_BLOCK. */
- gsi = gsi_last_bb (cond_block);
- gsi_remove (&gsi, true);
statistics_counter_event (cfun, "Replace PHI with variable", 1);
@@ -959,6 +965,9 @@ match_simplify_replacement (basic_block cond_bb, basic_block middle_bb,
allow it and move it once the transformation is done. */
if (!empty_block_p (middle_bb))
{
+ if (!single_pred_p (middle_bb))
+ return false;
+
stmt_to_move = last_and_only_stmt (middle_bb);
if (!stmt_to_move)
return false;
@@ -1351,7 +1360,10 @@ value_replacement (basic_block cond_bb, basic_block middle_bb,
}
else
{
- statistics_counter_event (cfun, "Replace PHI with variable/value_replacement", 1);
+ if (!single_pred_p (middle_bb))
+ return 0;
+ statistics_counter_event (cfun, "Replace PHI with "
+ "variable/value_replacement", 1);
/* Replace the PHI arguments with arg. */
SET_PHI_ARG_DEF (phi, e0->dest_idx, arg);
@@ -1367,7 +1379,6 @@ value_replacement (basic_block cond_bb, basic_block middle_bb,
}
return 1;
}
-
}
/* Now optimize (x != 0) ? x + y : y to just x + y. */
</cut>
3 years, 7 months
- 2
- 1
[TCWG CI] 464.h264ref slowed down by 6% after llvm: [unroll] Keep unrolled iterations with initial iteration
by ci_notify＠linaro.org
After llvm commit de2fed61528a5584dc54c47f6754408597be24de
Author: Philip Reames <listmail(a)philipreames.com>
[unroll] Keep unrolled iterations with initial iteration
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 6% from 10902 to 11518 perf samples
- 464.h264ref:[.] FastFullPelBlockMotionSearch slowed down by 43% from 1494 to 2141 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-de2fed61528a5584dc54c47f6754408597be24de
cd investigate-llvm-de2fed61528a5584dc54c47f6754408597be24de
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach de2fed61528a5584dc54c47f6754408597be24de
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach da25f968a90ad4560fc920a6d18fc2a0221d2750
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit de2fed61528a5584dc54c47f6754408597be24de
Author: Philip Reames <listmail(a)philipreames.com>
Date: Fri Nov 12 11:35:28 2021 -0800
[unroll] Keep unrolled iterations with initial iteration
The unrolling code was previously inserting new cloned blocks at the end of the function. The result of this with typical loop structures is that the new iterations are placed far from the initial iteration.
With unrolling, the general assumption is that the a) the loop is reasonable hot, and b) the first Count-1 copies of the loop are rarely (if ever) loop exiting. As such, placing Count-1 copies out of line is a fairly poor code placement choice. We'd much rather fall through into the hot (non-exiting) path. For code with branch profiles, later layout would fix this, but this may have a positive impact on non-PGO compiled code.
However, the real motivation for this change isn't performance. Its readability and human understanding. Having to jump around long distances in an IR file to trace an unrolled loop structure is error prone and tedious.
---
llvm/lib/Transforms/Utils/LoopUnroll.cpp | 6 +-
llvm/test/DebugInfo/unrolled-loop-remainder.ll | 86 +-
.../Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll | 66 +-
.../Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll | 24 +-
.../LoopUnroll/AArch64/runtime-unroll-generic.ll | 4 +-
.../LoopUnroll/AArch64/thresholdO3-cost-model.ll | 8 +-
.../LoopUnroll/AArch64/unroll-upperbound.ll | 4 +-
.../Transforms/LoopUnroll/ARM/loop-unrolling.ll | 4 +-
.../test/Transforms/LoopUnroll/ARM/multi-blocks.ll | 230 +-
llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll | 10 +-
.../LoopUnroll/full-unroll-keep-first-exit.ll | 16 +-
.../full-unroll-one-unpredictable-exit.ll | 16 +-
llvm/test/Transforms/LoopUnroll/multiple-exits.ll | 8 +-
llvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll | 20 +-
.../LoopUnroll/partial-unroll-non-latch-exit.ll | 14 +-
.../partially-unroll-unconditional-latch.ll | 4 +-
.../LoopUnroll/runtime-loop-at-most-two-exits.ll | 120 +-
.../runtime-loop-multiexit-dom-verify.ll | 206 +-
.../LoopUnroll/runtime-loop-multiple-exits.ll | 2560 ++++++++++----------
llvm/test/Transforms/LoopUnroll/runtime-loop5.ll | 34 +-
.../LoopUnroll/runtime-multiexit-heuristic.ll | 122 +-
.../LoopUnroll/runtime-small-upperbound.ll | 8 +-
.../LoopUnroll/runtime-unroll-remainder.ll | 62 +-
llvm/test/Transforms/LoopUnroll/scevunroll.ll | 48 +-
.../Transforms/LoopUnroll/shifted-tripcount.ll | 4 +-
...er-exiting-with-phis-multiple-exiting-blocks.ll | 20 +-
.../LoopUnroll/unroll-unconditional-latch.ll | 12 +-
.../Transforms/LoopUnrollAndJam/unroll-and-jam.ll | 68 +-
.../PhaseOrdering/AArch64/matrix-extract-insert.ll | 4 +-
29 files changed, 1896 insertions(+), 1892 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/LoopUnroll.cpp b/llvm/lib/Transforms/Utils/LoopUnroll.cpp
index ce463927fd50..b0c622b98d5e 100644
--- a/llvm/lib/Transforms/Utils/LoopUnroll.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUnroll.cpp
@@ -514,6 +514,10 @@ LoopUnrollResult llvm::UnrollLoop(Loop *L, UnrollLoopOptions ULO, LoopInfo *LI,
SmallVector<MDNode *, 6> LoopLocalNoAliasDeclScopes;
identifyNoAliasScopesToClone(L->getBlocks(), LoopLocalNoAliasDeclScopes);
+ // We place the unrolled iterations immediately after the original loop
+ // latch. This is a reasonable default placement if we don't have block
+ // frequencies, and if we do, well the layout will be adjusted later.
+ auto BlockInsertPt = std::next(LatchBlock->getIterator());
for (unsigned It = 1; It != ULO.Count; ++It) {
SmallVector<BasicBlock *, 8> NewBlocks;
SmallDenseMap<const Loop *, Loop *, 4> NewLoops;
@@ -522,7 +526,7 @@ LoopUnrollResult llvm::UnrollLoop(Loop *L, UnrollLoopOptions ULO, LoopInfo *LI,
for (LoopBlocksDFS::RPOIterator BB = BlockBegin; BB != BlockEnd; ++BB) {
ValueToValueMapTy VMap;
BasicBlock *New = CloneBasicBlock(*BB, VMap, "." + Twine(It));
- Header->getParent()->getBasicBlockList().push_back(New);
+ Header->getParent()->getBasicBlockList().insert(BlockInsertPt, New);
assert((*BB != Header || LI->getLoopFor(*BB) == L) &&
"Header should not be in a sub-loop");
diff --git a/llvm/test/DebugInfo/unrolled-loop-remainder.ll b/llvm/test/DebugInfo/unrolled-loop-remainder.ll
index 83c30dec780d..ba4ce1f409f6 100644
--- a/llvm/test/DebugInfo/unrolled-loop-remainder.ll
+++ b/llvm/test/DebugInfo/unrolled-loop-remainder.ll
@@ -38,71 +38,71 @@ define i32 @func_c() local_unnamed_addr #0 !dbg !14 {
; CHECK-NEXT: [[PROL_ITER_SUB:%.*]] = sub i32 [[XTRAITER]], 1, !dbg [[DBG24]]
; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i32 [[PROL_ITER_SUB]], 0, !dbg [[DBG24]]
; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[FOR_BODY_PROL_1:%.*]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !dbg [[DBG24]]
+; CHECK: for.body.prol.1:
+; CHECK-NEXT: [[ARRAYIDX_PROL_1:%.*]] = getelementptr inbounds i32, i32* [[TMP6]], i64 1, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_PROL_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
+; CHECK-NEXT: [[CONV_PROL_1:%.*]] = sext i32 [[TMP7]] to i64, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[CONV_PROL_1]] to i32*, !dbg [[DBG28]]
+; CHECK-NEXT: [[ADD_PROL_1:%.*]] = add nsw i32 [[ADD_PROL]], 2, !dbg [[DBG29]]
+; CHECK-NEXT: [[PROL_ITER_SUB_1:%.*]] = sub i32 [[PROL_ITER_SUB]], 1, !dbg [[DBG24]]
+; CHECK-NEXT: [[PROL_ITER_CMP_1:%.*]] = icmp ne i32 [[PROL_ITER_SUB_1]], 0, !dbg [[DBG24]]
+; CHECK-NEXT: br i1 [[PROL_ITER_CMP_1]], label [[FOR_BODY_PROL_2:%.*]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]], !dbg [[DBG24]]
+; CHECK: for.body.prol.2:
+; CHECK-NEXT: [[ARRAYIDX_PROL_2:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 1, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX_PROL_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
+; CHECK-NEXT: [[CONV_PROL_2:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[CONV_PROL_2]] to i32*, !dbg [[DBG28]]
+; CHECK-NEXT: [[ADD_PROL_2:%.*]] = add nsw i32 [[ADD_PROL_1]], 2, !dbg [[DBG29]]
+; CHECK-NEXT: br label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]]
; CHECK: for.body.prol.loopexit.unr-lcssa:
-; CHECK-NEXT: [[DOTLCSSA_UNR_PH:%.*]] = phi i32* [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP20:%.*]], [[FOR_BODY_PROL_1]] ], [ [[TMP22:%.*]], [[FOR_BODY_PROL_2:%.*]] ]
-; CHECK-NEXT: [[DOTUNR_PH:%.*]] = phi i32* [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP20]], [[FOR_BODY_PROL_1]] ], [ [[TMP22]], [[FOR_BODY_PROL_2]] ]
-; CHECK-NEXT: [[DOTUNR1_PH:%.*]] = phi i32 [ [[ADD_PROL]], [[FOR_BODY_PROL]] ], [ [[ADD_PROL_1:%.*]], [[FOR_BODY_PROL_1]] ], [ [[ADD_PROL_2:%.*]], [[FOR_BODY_PROL_2]] ]
+; CHECK-NEXT: [[DOTLCSSA_UNR_PH:%.*]] = phi i32* [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP8]], [[FOR_BODY_PROL_1]] ], [ [[TMP10]], [[FOR_BODY_PROL_2]] ]
+; CHECK-NEXT: [[DOTUNR_PH:%.*]] = phi i32* [ [[TMP6]], [[FOR_BODY_PROL]] ], [ [[TMP8]], [[FOR_BODY_PROL_1]] ], [ [[TMP10]], [[FOR_BODY_PROL_2]] ]
+; CHECK-NEXT: [[DOTUNR1_PH:%.*]] = phi i32 [ [[ADD_PROL]], [[FOR_BODY_PROL]] ], [ [[ADD_PROL_1]], [[FOR_BODY_PROL_1]] ], [ [[ADD_PROL_2]], [[FOR_BODY_PROL_2]] ]
; CHECK-NEXT: br label [[FOR_BODY_PROL_LOOPEXIT]], !dbg [[DBG24]]
; CHECK: for.body.prol.loopexit:
; CHECK-NEXT: [[DOTLCSSA_UNR:%.*]] = phi i32* [ undef, [[FOR_BODY_LR_PH]] ], [ [[DOTLCSSA_UNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[DOTUNR:%.*]] = phi i32* [ [[A_PROMOTED]], [[FOR_BODY_LR_PH]] ], [ [[DOTUNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
; CHECK-NEXT: [[DOTUNR1:%.*]] = phi i32 [ [[DOTPR]], [[FOR_BODY_LR_PH]] ], [ [[DOTUNR1_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP3]], 3, !dbg [[DBG24]]
-; CHECK-NEXT: br i1 [[TMP7]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY_LR_PH_NEW:%.*]], !dbg [[DBG24]]
+; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP3]], 3, !dbg [[DBG24]]
+; CHECK-NEXT: br i1 [[TMP11]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]], label [[FOR_BODY_LR_PH_NEW:%.*]], !dbg [[DBG24]]
; CHECK: for.body.lr.ph.new:
; CHECK-NEXT: br label [[FOR_BODY:%.*]], !dbg [[DBG24]]
; CHECK: for.body:
-; CHECK-NEXT: [[TMP8:%.*]] = phi i32* [ [[DOTUNR]], [[FOR_BODY_LR_PH_NEW]] ], [ [[TMP17:%.*]], [[FOR_BODY]] ], !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[DOTUNR1]], [[FOR_BODY_LR_PH_NEW]] ], [ [[ADD_3:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 1, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
-; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[CONV]] to i32*, !dbg [[DBG28]]
-; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 2, !dbg [[DBG29]]
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i64 1, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
-; CHECK-NEXT: [[CONV_1:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[CONV_1]] to i32*, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP12:%.*]] = phi i32* [ [[DOTUNR]], [[FOR_BODY_LR_PH_NEW]] ], [ [[TMP21:%.*]], [[FOR_BODY]] ], !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ [[DOTUNR1]], [[FOR_BODY_LR_PH_NEW]] ], [ [[ADD_3:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i64 1, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
+; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[CONV]] to i32*, !dbg [[DBG28]]
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 2, !dbg [[DBG29]]
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i64 1, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
+; CHECK-NEXT: [[CONV_1:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[CONV_1]] to i32*, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[ADD]], 2, !dbg [[DBG29]]
-; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[TMP13]], i64 1, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
-; CHECK-NEXT: [[CONV_2:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[CONV_2]] to i32*, !dbg [[DBG28]]
+; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 1, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
+; CHECK-NEXT: [[CONV_2:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[CONV_2]] to i32*, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[ADD_1]], 2, !dbg [[DBG29]]
-; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i64 1, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
-; CHECK-NEXT: [[CONV_3:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP17]] = inttoptr i64 [[CONV_3]] to i32*, !dbg [[DBG28]]
+; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 1, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
+; CHECK-NEXT: [[CONV_3:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG28]]
+; CHECK-NEXT: [[TMP21]] = inttoptr i64 [[CONV_3]] to i32*, !dbg [[DBG28]]
; CHECK-NEXT: [[ADD_3]] = add nsw i32 [[ADD_2]], 2, !dbg [[DBG29]]
; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq i32 [[ADD_3]], 0, !dbg [[DBG24]]
; CHECK-NEXT: br i1 [[TOBOOL_3]], label [[FOR_COND_FOR_END_CRIT_EDGE_UNR_LCSSA:%.*]], label [[FOR_BODY]], !dbg [[DBG24]], !llvm.loop [[LOOP30:![0-9]+]]
; CHECK: for.cond.for.end_crit_edge.unr-lcssa:
-; CHECK-NEXT: [[DOTLCSSA_PH:%.*]] = phi i32* [ [[TMP17]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[DOTLCSSA_PH:%.*]] = phi i32* [ [[TMP21]], [[FOR_BODY]] ]
; CHECK-NEXT: br label [[FOR_COND_FOR_END_CRIT_EDGE]], !dbg [[DBG24]]
; CHECK: for.cond.for.end_crit_edge:
; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32* [ [[DOTLCSSA_UNR]], [[FOR_BODY_PROL_LOOPEXIT]] ], [ [[DOTLCSSA_PH]], [[FOR_COND_FOR_END_CRIT_EDGE_UNR_LCSSA]] ], !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP2]], 2, !dbg [[DBG24]]
+; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP2]], 2, !dbg [[DBG24]]
; CHECK-NEXT: store i32* [[DOTLCSSA]], i32** @a, align 8, !dbg [[DBG25]], !tbaa [[TBAA26]]
-; CHECK-NEXT: store i32 [[TMP18]], i32* @b, align 4, !dbg [[DBG33:![0-9]+]], !tbaa [[TBAA20]]
+; CHECK-NEXT: store i32 [[TMP22]], i32* @b, align 4, !dbg [[DBG33:![0-9]+]], !tbaa [[TBAA20]]
; CHECK-NEXT: br label [[FOR_END]], !dbg [[DBG24]]
; CHECK: for.end:
; CHECK-NEXT: ret i32 undef, !dbg [[DBG34:![0-9]+]]
-; CHECK: for.body.prol.1:
-; CHECK-NEXT: [[ARRAYIDX_PROL_1:%.*]] = getelementptr inbounds i32, i32* [[TMP6]], i64 1, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[ARRAYIDX_PROL_1]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
-; CHECK-NEXT: [[CONV_PROL_1:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP20]] = inttoptr i64 [[CONV_PROL_1]] to i32*, !dbg [[DBG28]]
-; CHECK-NEXT: [[ADD_PROL_1]] = add nsw i32 [[ADD_PROL]], 2, !dbg [[DBG29]]
-; CHECK-NEXT: [[PROL_ITER_SUB_1:%.*]] = sub i32 [[PROL_ITER_SUB]], 1, !dbg [[DBG24]]
-; CHECK-NEXT: [[PROL_ITER_CMP_1:%.*]] = icmp ne i32 [[PROL_ITER_SUB_1]], 0, !dbg [[DBG24]]
-; CHECK-NEXT: br i1 [[PROL_ITER_CMP_1]], label [[FOR_BODY_PROL_2]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]], !dbg [[DBG24]]
-; CHECK: for.body.prol.2:
-; CHECK-NEXT: [[ARRAYIDX_PROL_2:%.*]] = getelementptr inbounds i32, i32* [[TMP20]], i64 1, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[ARRAYIDX_PROL_2]], align 4, !dbg [[DBG28]], !tbaa [[TBAA20]]
-; CHECK-NEXT: [[CONV_PROL_2:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP22]] = inttoptr i64 [[CONV_PROL_2]] to i32*, !dbg [[DBG28]]
-; CHECK-NEXT: [[ADD_PROL_2]] = add nsw i32 [[ADD_PROL_1]], 2, !dbg [[DBG29]]
-; CHECK-NEXT: br label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]]
;
entry:
%.pr = load i32, i32* @b, align 4, !dbg !17, !tbaa !20
diff --git a/llvm/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll b/llvm/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
index 3e611430d69e..7bb2d732195a 100644
--- a/llvm/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
+++ b/llvm/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
@@ -17,24 +17,24 @@ define void @test1(i32 %i, i32 %j) nounwind uwtable ssp {
; CHECK-NEXT: [[SUB5:%.*]] = sub i32 [[SUB]], [[J:%.*]]
; CHECK-NEXT: [[COND2:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND2]], label [[IF_THEN_LOOPEXIT:%.*]], label [[IF_ELSE_1:%.*]]
-; CHECK: if.then.loopexit:
-; CHECK-NEXT: [[SUB5_LCSSA:%.*]] = phi i32 [ [[SUB5]], [[IF_ELSE]] ], [ [[SUB5_1:%.*]], [[IF_ELSE_1]] ], [ [[SUB5_2:%.*]], [[IF_ELSE_2:%.*]] ], [ [[SUB5_3]], [[IF_ELSE_3]] ]
-; CHECK-NEXT: br label [[IF_THEN]]
-; CHECK: if.then:
-; CHECK-NEXT: [[I_TR:%.*]] = phi i32 [ [[I]], [[ENTRY:%.*]] ], [ [[SUB5_LCSSA]], [[IF_THEN_LOOPEXIT]] ]
-; CHECK-NEXT: ret void
; CHECK: if.else.1:
-; CHECK-NEXT: [[SUB5_1]] = sub i32 [[SUB5]], [[J]]
+; CHECK-NEXT: [[SUB5_1:%.*]] = sub i32 [[SUB5]], [[J]]
; CHECK-NEXT: [[COND2_1:%.*]] = call zeroext i1 @check()
-; CHECK-NEXT: br i1 [[COND2_1]], label [[IF_THEN_LOOPEXIT]], label [[IF_ELSE_2]]
+; CHECK-NEXT: br i1 [[COND2_1]], label [[IF_THEN_LOOPEXIT]], label [[IF_ELSE_2:%.*]]
; CHECK: if.else.2:
-; CHECK-NEXT: [[SUB5_2]] = sub i32 [[SUB5_1]], [[J]]
+; CHECK-NEXT: [[SUB5_2:%.*]] = sub i32 [[SUB5_1]], [[J]]
; CHECK-NEXT: [[COND2_2:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND2_2]], label [[IF_THEN_LOOPEXIT]], label [[IF_ELSE_3]]
; CHECK: if.else.3:
; CHECK-NEXT: [[SUB5_3]] = sub i32 [[SUB5_2]], [[J]]
; CHECK-NEXT: [[COND2_3:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND2_3]], label [[IF_THEN_LOOPEXIT]], label [[IF_ELSE]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: if.then.loopexit:
+; CHECK-NEXT: [[SUB5_LCSSA:%.*]] = phi i32 [ [[SUB5]], [[IF_ELSE]] ], [ [[SUB5_1]], [[IF_ELSE_1]] ], [ [[SUB5_2]], [[IF_ELSE_2]] ], [ [[SUB5_3]], [[IF_ELSE_3]] ]
+; CHECK-NEXT: br label [[IF_THEN]]
+; CHECK: if.then:
+; CHECK-NEXT: [[I_TR:%.*]] = phi i32 [ [[I]], [[ENTRY:%.*]] ], [ [[SUB5_LCSSA]], [[IF_THEN_LOOPEXIT]] ]
+; CHECK-NEXT: ret void
;
entry:
%cond1 = call zeroext i1 @check()
@@ -77,17 +77,11 @@ define i32 @test2(i32* nocapture %p, i32 %n) nounwind readonly {
; CHECK-NEXT: [[INDVAR_NEXT:%.*]] = add nuw nsw i64 [[INDVAR]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVAR_NEXT]], [[TMP]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB_1:%.*]], label [[BB1_BB2_CRIT_EDGE:%.*]]
-; CHECK: bb1.bb2_crit_edge:
-; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP2]], [[BB1]] ], [ [[TMP4:%.*]], [[BB1_1:%.*]] ], [ [[TMP6:%.*]], [[BB1_2:%.*]] ], [ [[TMP8]], [[BB1_3]] ]
-; CHECK-NEXT: br label [[BB2]]
-; CHECK: bb2:
-; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB1_BB2_CRIT_EDGE]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: ret i32 [[S_0_LCSSA]]
; CHECK: bb.1:
; CHECK-NEXT: [[SCEVGEP_1:%.*]] = getelementptr i32, i32* [[P]], i64 [[INDVAR_NEXT]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[SCEVGEP_1]], align 1
-; CHECK-NEXT: [[TMP4]] = add nsw i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: br label [[BB1_1]]
+; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT: br label [[BB1_1:%.*]]
; CHECK: bb1.1:
; CHECK-NEXT: [[INDVAR_NEXT_1:%.*]] = add nuw nsw i64 [[INDVAR_NEXT]], 1
; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp ne i64 [[INDVAR_NEXT_1]], [[TMP]]
@@ -95,8 +89,8 @@ define i32 @test2(i32* nocapture %p, i32 %n) nounwind readonly {
; CHECK: bb.2:
; CHECK-NEXT: [[SCEVGEP_2:%.*]] = getelementptr i32, i32* [[P]], i64 [[INDVAR_NEXT_1]]
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[SCEVGEP_2]], align 1
-; CHECK-NEXT: [[TMP6]] = add nsw i32 [[TMP5]], [[TMP4]]
-; CHECK-NEXT: br label [[BB1_2]]
+; CHECK-NEXT: [[TMP6:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
+; CHECK-NEXT: br label [[BB1_2:%.*]]
; CHECK: bb1.2:
; CHECK-NEXT: [[INDVAR_NEXT_2:%.*]] = add nuw nsw i64 [[INDVAR_NEXT_1]], 1
; CHECK-NEXT: [[EXITCOND_2:%.*]] = icmp ne i64 [[INDVAR_NEXT_2]], [[TMP]]
@@ -110,6 +104,12 @@ define i32 @test2(i32* nocapture %p, i32 %n) nounwind readonly {
; CHECK-NEXT: [[INDVAR_NEXT_3]] = add i64 [[INDVAR_NEXT_2]], 1
; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp ne i64 [[INDVAR_NEXT_3]], [[TMP]]
; CHECK-NEXT: br i1 [[EXITCOND_3]], label [[BB]], label [[BB1_BB2_CRIT_EDGE]], !llvm.loop [[LOOP2:![0-9]+]]
+; CHECK: bb1.bb2_crit_edge:
+; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP2]], [[BB1]] ], [ [[TMP4]], [[BB1_1]] ], [ [[TMP6]], [[BB1_2]] ], [ [[TMP8]], [[BB1_3]] ]
+; CHECK-NEXT: br label [[BB2]]
+; CHECK: bb2:
+; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ [[DOTLCSSA]], [[BB1_BB2_CRIT_EDGE]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i32 [[S_0_LCSSA]]
;
entry:
%0 = icmp sgt i32 %n, 0 ; <i1> [#uses=1]
@@ -162,20 +162,12 @@ define i32 @test3() nounwind uwtable ssp align 2 {
; CHECK: do.cond:
; CHECK-NEXT: [[COND3:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND3]], label [[DO_END:%.*]], label [[DO_BODY_1:%.*]]
-; CHECK: do.end:
-; CHECK-NEXT: br label [[RETURN]]
-; CHECK: return.loopexit:
-; CHECK-NEXT: [[TMP7_I_LCSSA:%.*]] = phi i32 [ [[TMP7_I]], [[LAND_LHS_TRUE]] ], [ [[TMP7_I_1:%.*]], [[LAND_LHS_TRUE_1:%.*]] ], [ [[TMP7_I_2:%.*]], [[LAND_LHS_TRUE_2:%.*]] ], [ [[TMP7_I_3:%.*]], [[LAND_LHS_TRUE_3:%.*]] ]
-; CHECK-NEXT: br label [[RETURN]]
-; CHECK: return:
-; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[DO_END]] ], [ 0, [[ENTRY:%.*]] ], [ [[TMP7_I_LCSSA]], [[RETURN_LOOPEXIT]] ]
-; CHECK-NEXT: ret i32 [[RETVAL_0]]
; CHECK: do.body.1:
; CHECK-NEXT: [[COND2_1:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND2_1]], label [[EXIT_1:%.*]], label [[DO_COND_1:%.*]]
; CHECK: exit.1:
-; CHECK-NEXT: [[TMP7_I_1]] = load i32, i32* undef, align 8
-; CHECK-NEXT: br i1 undef, label [[DO_COND_1]], label [[LAND_LHS_TRUE_1]]
+; CHECK-NEXT: [[TMP7_I_1:%.*]] = load i32, i32* undef, align 8
+; CHECK-NEXT: br i1 undef, label [[DO_COND_1]], label [[LAND_LHS_TRUE_1:%.*]]
; CHECK: land.lhs.true.1:
; CHECK-NEXT: br i1 true, label [[RETURN_LOOPEXIT]], label [[DO_COND_1]]
; CHECK: do.cond.1:
@@ -185,8 +177,8 @@ define i32 @test3() nounwind uwtable ssp align 2 {
; CHECK-NEXT: [[COND2_2:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND2_2]], label [[EXIT_2:%.*]], label [[DO_COND_2:%.*]]
; CHECK: exit.2:
-; CHECK-NEXT: [[TMP7_I_2]] = load i32, i32* undef, align 8
-; CHECK-NEXT: br i1 undef, label [[DO_COND_2]], label [[LAND_LHS_TRUE_2]]
+; CHECK-NEXT: [[TMP7_I_2:%.*]] = load i32, i32* undef, align 8
+; CHECK-NEXT: br i1 undef, label [[DO_COND_2]], label [[LAND_LHS_TRUE_2:%.*]]
; CHECK: land.lhs.true.2:
; CHECK-NEXT: br i1 true, label [[RETURN_LOOPEXIT]], label [[DO_COND_2]]
; CHECK: do.cond.2:
@@ -196,13 +188,21 @@ define i32 @test3() nounwind uwtable ssp align 2 {
; CHECK-NEXT: [[COND2_3:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND2_3]], label [[EXIT_3:%.*]], label [[DO_COND_3:%.*]]
; CHECK: exit.3:
-; CHECK-NEXT: [[TMP7_I_3]] = load i32, i32* undef, align 8
-; CHECK-NEXT: br i1 undef, label [[DO_COND_3]], label [[LAND_LHS_TRUE_3]]
+; CHECK-NEXT: [[TMP7_I_3:%.*]] = load i32, i32* undef, align 8
+; CHECK-NEXT: br i1 undef, label [[DO_COND_3]], label [[LAND_LHS_TRUE_3:%.*]]
; CHECK: land.lhs.true.3:
; CHECK-NEXT: br i1 true, label [[RETURN_LOOPEXIT]], label [[DO_COND_3]]
; CHECK: do.cond.3:
; CHECK-NEXT: [[COND3_3:%.*]] = call zeroext i1 @check()
; CHECK-NEXT: br i1 [[COND3_3]], label [[DO_END]], label [[DO_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: do.end:
+; CHECK-NEXT: br label [[RETURN]]
+; CHECK: return.loopexit:
+; CHECK-NEXT: [[TMP7_I_LCSSA:%.*]] = phi i32 [ [[TMP7_I]], [[LAND_LHS_TRUE]] ], [ [[TMP7_I_1]], [[LAND_LHS_TRUE_1]] ], [ [[TMP7_I_2]], [[LAND_LHS_TRUE_2]] ], [ [[TMP7_I_3]], [[LAND_LHS_TRUE_3]] ]
+; CHECK-NEXT: br label [[RETURN]]
+; CHECK: return:
+; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[DO_END]] ], [ 0, [[ENTRY:%.*]] ], [ [[TMP7_I_LCSSA]], [[RETURN_LOOPEXIT]] ]
+; CHECK-NEXT: ret i32 [[RETVAL_0]]
;
entry:
%cond1 = call zeroext i1 @check()
diff --git a/llvm/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll b/llvm/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll
index be4b6ff64fdd..af648bae8642 100644
--- a/llvm/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll
+++ b/llvm/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll
@@ -33,16 +33,13 @@ define i32 @foo() uwtable ssp align 2 {
; CHECK: do.cond:
; CHECK-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[CALL2]], -1
; CHECK-NEXT: br i1 [[CMP18]], label [[LAND_LHS_TRUE_I_1:%.*]], label [[RETURN]]
-; CHECK: return:
-; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[TMP7_I]], [[LAND_LHS_TRUE]] ], [ 0, [[DO_COND]] ], [ [[TMP7_I_1:%.*]], [[LAND_LHS_TRUE_1:%.*]] ], [ 0, [[DO_COND_1:%.*]] ], [ [[TMP7_I_2:%.*]], [[LAND_LHS_TRUE_2:%.*]] ], [ 0, [[DO_COND_2:%.*]] ], [ [[TMP7_I_3:%.*]], [[LAND_LHS_TRUE_3:%.*]] ], [ 0, [[DO_COND_3:%.*]] ]
-; CHECK-NEXT: ret i32 [[RETVAL_0]]
; CHECK: land.lhs.true.i.1:
; CHECK-NEXT: [[CMP4_I_1:%.*]] = call zeroext i1 @check() #[[ATTR0]]
-; CHECK-NEXT: br i1 [[CMP4_I_1]], label [[BAR_EXIT_1:%.*]], label [[DO_COND_1]]
+; CHECK-NEXT: br i1 [[CMP4_I_1]], label [[BAR_EXIT_1:%.*]], label [[DO_COND_1:%.*]]
; CHECK: bar.exit.1:
-; CHECK-NEXT: [[TMP7_I_1]] = call i32 @getval() #[[ATTR0]]
+; CHECK-NEXT: [[TMP7_I_1:%.*]] = call i32 @getval() #[[ATTR0]]
; CHECK-NEXT: [[CMP_NOT_1:%.*]] = icmp eq i32 [[TMP7_I_1]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT_1]], label [[DO_COND_1]], label [[LAND_LHS_TRUE_1]]
+; CHECK-NEXT: br i1 [[CMP_NOT_1]], label [[DO_COND_1]], label [[LAND_LHS_TRUE_1:%.*]]
; CHECK: land.lhs.true.1:
; CHECK-NEXT: [[CALL10_1:%.*]] = call i32 @getval()
; CHECK-NEXT: [[CMP11_1:%.*]] = icmp eq i32 [[CALL10_1]], 0
@@ -52,11 +49,11 @@ define i32 @foo() uwtable ssp align 2 {
; CHECK-NEXT: br i1 [[CMP18_1]], label [[LAND_LHS_TRUE_I_2:%.*]], label [[RETURN]]
; CHECK: land.lhs.true.i.2:
; CHECK-NEXT: [[CMP4_I_2:%.*]] = call zeroext i1 @check() #[[ATTR0]]
-; CHECK-NEXT: br i1 [[CMP4_I_2]], label [[BAR_EXIT_2:%.*]], label [[DO_COND_2]]
+; CHECK-NEXT: br i1 [[CMP4_I_2]], label [[BAR_EXIT_2:%.*]], label [[DO_COND_2:%.*]]
; CHECK: bar.exit.2:
-; CHECK-NEXT: [[TMP7_I_2]] = call i32 @getval() #[[ATTR0]]
+; CHECK-NEXT: [[TMP7_I_2:%.*]] = call i32 @getval() #[[ATTR0]]
; CHECK-NEXT: [[CMP_NOT_2:%.*]] = icmp eq i32 [[TMP7_I_2]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT_2]], label [[DO_COND_2]], label [[LAND_LHS_TRUE_2]]
+; CHECK-NEXT: br i1 [[CMP_NOT_2]], label [[DO_COND_2]], label [[LAND_LHS_TRUE_2:%.*]]
; CHECK: land.lhs.true.2:
; CHECK-NEXT: [[CALL10_2:%.*]] = call i32 @getval()
; CHECK-NEXT: [[CMP11_2:%.*]] = icmp eq i32 [[CALL10_2]], 0
@@ -66,11 +63,11 @@ define i32 @foo() uwtable ssp align 2 {
; CHECK-NEXT: br i1 [[CMP18_2]], label [[LAND_LHS_TRUE_I_3:%.*]], label [[RETURN]]
; CHECK: land.lhs.true.i.3:
; CHECK-NEXT: [[CMP4_I_3:%.*]] = call zeroext i1 @check() #[[ATTR0]]
-; CHECK-NEXT: br i1 [[CMP4_I_3]], label [[BAR_EXIT_3:%.*]], label [[DO_COND_3]]
+; CHECK-NEXT: br i1 [[CMP4_I_3]], label [[BAR_EXIT_3:%.*]], label [[DO_COND_3:%.*]]
; CHECK: bar.exit.3:
-; CHECK-NEXT: [[TMP7_I_3]] = call i32 @getval() #[[ATTR0]]
+; CHECK-NEXT: [[TMP7_I_3:%.*]] = call i32 @getval() #[[ATTR0]]
; CHECK-NEXT: [[CMP_NOT_3:%.*]] = icmp eq i32 [[TMP7_I_3]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT_3]], label [[DO_COND_3]], label [[LAND_LHS_TRUE_3]]
+; CHECK-NEXT: br i1 [[CMP_NOT_3]], label [[DO_COND_3]], label [[LAND_LHS_TRUE_3:%.*]]
; CHECK: land.lhs.true.3:
; CHECK-NEXT: [[CALL10_3:%.*]] = call i32 @getval()
; CHECK-NEXT: [[CMP11_3:%.*]] = icmp eq i32 [[CALL10_3]], 0
@@ -78,6 +75,9 @@ define i32 @foo() uwtable ssp align 2 {
; CHECK: do.cond.3:
; CHECK-NEXT: [[CMP18_3:%.*]] = icmp sgt i32 [[CALL2]], -1
; CHECK-NEXT: br i1 [[CMP18_3]], label [[LAND_LHS_TRUE_I]], label [[RETURN]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: return:
+; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[TMP7_I]], [[LAND_LHS_TRUE]] ], [ 0, [[DO_COND]] ], [ [[TMP7_I_1]], [[LAND_LHS_TRUE_1]] ], [ 0, [[DO_COND_1]] ], [ [[TMP7_I_2]], [[LAND_LHS_TRUE_2]] ], [ 0, [[DO_COND_2]] ], [ [[TMP7_I_3]], [[LAND_LHS_TRUE_3]] ], [ 0, [[DO_COND_3]] ]
+; CHECK-NEXT: ret i32 [[RETVAL_0]]
;
entry:
br i1 undef, label %return, label %if.end
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
index 5bbab929c936..5c8f9ca01679 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
@@ -67,8 +67,6 @@ define void @runtime_unroll_generic(i32 %arg_0, i32* %arg_1, i16* %arg_2, i16* %
; CHECK-A55-NEXT: store i32 [[ADD21_EPIL]], i32* [[ARRAYIDX20]], align 4
; CHECK-A55-NEXT: [[EPIL_ITER_CMP_NOT:%.*]] = icmp eq i32 [[XTRAITER]], 1
; CHECK-A55-NEXT: br i1 [[EPIL_ITER_CMP_NOT]], label [[FOR_END]], label [[FOR_BODY6_EPIL_1:%.*]]
-; CHECK-A55: for.end:
-; CHECK-A55-NEXT: ret void
; CHECK-A55: for.body6.epil.1:
; CHECK-A55-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX10]], align 2
; CHECK-A55-NEXT: [[CONV_EPIL_1:%.*]] = sext i16 [[TMP14]] to i32
@@ -90,6 +88,8 @@ define void @runtime_unroll_generic(i32 %arg_0, i32* %arg_1, i16* %arg_2, i16* %
; CHECK-A55-NEXT: [[ADD21_EPIL_2:%.*]] = add nsw i32 [[MUL16_EPIL_2]], [[TMP19]]
; CHECK-A55-NEXT: store i32 [[ADD21_EPIL_2]], i32* [[ARRAYIDX20]], align 4
; CHECK-A55-NEXT: br label [[FOR_END]]
+; CHECK-A55: for.end:
+; CHECK-A55-NEXT: ret void
;
; CHECK-GENERIC-LABEL: @runtime_unroll_generic(
; CHECK-GENERIC-NEXT: entry:
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/thresholdO3-cost-model.ll b/llvm/test/Transforms/LoopUnroll/AArch64/thresholdO3-cost-model.ll
index ee07518f8cac..5c6ac690c0ca 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/thresholdO3-cost-model.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/thresholdO3-cost-model.ll
@@ -21,10 +21,6 @@ define i32 @tripcount_11() {
; CHECK-NEXT: br label [[DO_BODY6:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: br i1 true, label [[FOR_COND_1:%.*]], label [[IF_THEN11:%.*]]
-; CHECK: do.body6:
-; CHECK-NEXT: br i1 true, label [[FOR_COND:%.*]], label [[IF_THEN11]]
-; CHECK: if.then11:
-; CHECK-NEXT: unreachable
; CHECK: for.cond.1:
; CHECK-NEXT: br i1 true, label [[FOR_COND_2:%.*]], label [[IF_THEN11]]
; CHECK: for.cond.2:
@@ -45,6 +41,10 @@ define i32 @tripcount_11() {
; CHECK-NEXT: br i1 true, label [[FOR_COND_10:%.*]], label [[IF_THEN11]]
; CHECK: for.cond.10:
; CHECK-NEXT: ret i32 0
+; CHECK: do.body6:
+; CHECK-NEXT: br i1 true, label [[FOR_COND:%.*]], label [[IF_THEN11]]
+; CHECK: if.then11:
+; CHECK-NEXT: unreachable
;
do.body6.preheader:
br label %do.body6
diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/unroll-upperbound.ll b/llvm/test/Transforms/LoopUnroll/AArch64/unroll-upperbound.ll
index 3b82365d1a6e..ee905e5b10fe 100644
--- a/llvm/test/Transforms/LoopUnroll/AArch64/unroll-upperbound.ll
+++ b/llvm/test/Transforms/LoopUnroll/AArch64/unroll-upperbound.ll
@@ -18,8 +18,6 @@ define void @test(i1 %cond) {
; CHECK-NEXT: br label [[LATCH]]
; CHECK: latch:
; CHECK-NEXT: br i1 false, label [[FOR_END:%.*]], label [[FOR_BODY_1:%.*]]
-; CHECK: for.end:
-; CHECK-NEXT: ret void
; CHECK: for.body.1:
; CHECK-NEXT: switch i32 1, label [[SW_DEFAULT_1:%.*]] [
; CHECK-NEXT: i32 2, label [[LATCH_1:%.*]]
@@ -38,6 +36,8 @@ define void @test(i1 %cond) {
; CHECK-NEXT: br label [[LATCH_2]]
; CHECK: latch.2:
; CHECK-NEXT: br label [[FOR_END]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
;
entry:
%0 = select i1 %cond, i32 2, i32 3
diff --git a/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll b/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
index f2e748ade0a2..e12dbf031b3b 100644
--- a/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
+++ b/llvm/test/Transforms/LoopUnroll/ARM/loop-unrolling.ll
@@ -121,14 +121,14 @@ for.body4:
; CHECK-NOUNROLL: br
; CHECK-UNROLL: for.body4.epil:
+; CHECK-UNROLL: for.body4.epil.1:
+; CHECK-UNROLL: for.body4.epil.2:
; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body4 ]
; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
; CHECK-UNROLL: [[IV4]] = add nuw i32 [[IV3]], 1
; CHECK-UNROLL: br
-; CHECK-UNROLL: for.body4.epil.1:
-; CHECK-UNROLL: for.body4.epil.2:
%w.024 = phi i32 [ 0, %for.body4.lr.ph ], [ %inc, %for.body4 ]
%add = add i32 %w.024, %mul
diff --git a/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll b/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
index 156c0ab10658..8c4257698ab7 100644
--- a/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
+++ b/llvm/test/Transforms/LoopUnroll/ARM/multi-blocks.ll
@@ -45,8 +45,37 @@ define void @test_three_blocks(i32* nocapture %Output,
; CHECK-NEXT: [[EPIL_ITER_SUB:%.*]] = sub i32 [[XTRAITER]], 1
; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 [[EPIL_ITER_SUB]], 0
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_BODY_EPIL_1:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA:%.*]]
+; CHECK: for.body.epil.1:
+; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC_EPIL]]
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_1]], align 4
+; CHECK-NEXT: [[TOBOOL_EPIL_1:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[TOBOOL_EPIL_1]], label [[FOR_INC_EPIL_1:%.*]], label [[IF_THEN_EPIL_1:%.*]]
+; CHECK: if.then.epil.1:
+; CHECK-NEXT: [[ARRAYIDX1_EPIL_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_EPIL]]
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX1_EPIL_1]], align 4
+; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add i32 [[TMP5]], [[TEMP_1_EPIL]]
+; CHECK-NEXT: br label [[FOR_INC_EPIL_1]]
+; CHECK: for.inc.epil.1:
+; CHECK-NEXT: [[TEMP_1_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[TEMP_1_EPIL]], [[FOR_BODY_EPIL_1]] ]
+; CHECK-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[INC_EPIL]], 1
+; CHECK-NEXT: [[EPIL_ITER_SUB_1:%.*]] = sub i32 [[EPIL_ITER_SUB]], 1
+; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 [[EPIL_ITER_SUB_1]], 0
+; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_BODY_EPIL_2:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
+; CHECK: for.body.epil.2:
+; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC_EPIL_1]]
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_2]], align 4
+; CHECK-NEXT: [[TOBOOL_EPIL_2:%.*]] = icmp eq i32 [[TMP6]], 0
+; CHECK-NEXT: br i1 [[TOBOOL_EPIL_2]], label [[FOR_INC_EPIL_2:%.*]], label [[IF_THEN_EPIL_2:%.*]]
+; CHECK: if.then.epil.2:
+; CHECK-NEXT: [[ARRAYIDX1_EPIL_2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_EPIL_1]]
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX1_EPIL_2]], align 4
+; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add i32 [[TMP7]], [[TEMP_1_EPIL_1]]
+; CHECK-NEXT: br label [[FOR_INC_EPIL_2]]
+; CHECK: for.inc.epil.2:
+; CHECK-NEXT: [[TEMP_1_EPIL_2:%.*]] = phi i32 [ [[ADD_EPIL_2]], [[IF_THEN_EPIL_2]] ], [ [[TEMP_1_EPIL_1]], [[FOR_BODY_EPIL_2]] ]
+; CHECK-NEXT: br label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.cond.cleanup.loopexit.epilog-lcssa:
-; CHECK-NEXT: [[TEMP_1_LCSSA_PH1:%.*]] = phi i32 [ [[TEMP_1_EPIL]], [[FOR_INC_EPIL]] ], [ [[TEMP_1_EPIL_1:%.*]], [[FOR_INC_EPIL_1:%.*]] ], [ [[TEMP_1_EPIL_2:%.*]], [[FOR_INC_EPIL_2:%.*]] ]
+; CHECK-NEXT: [[TEMP_1_LCSSA_PH1:%.*]] = phi i32 [ [[TEMP_1_EPIL]], [[FOR_INC_EPIL]] ], [ [[TEMP_1_EPIL_1]], [[FOR_INC_EPIL_1]] ], [ [[TEMP_1_EPIL_2]], [[FOR_INC_EPIL_2]] ]
; CHECK-NEXT: br label [[FOR_COND_CLEANUP_LOOPEXIT]]
; CHECK: for.cond.cleanup.loopexit:
; CHECK-NEXT: [[TEMP_1_LCSSA:%.*]] = phi i32 [ [[TEMP_1_LCSSA_PH]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ], [ [[TEMP_1_LCSSA_PH1]], [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]] ]
@@ -60,51 +89,22 @@ define void @test_three_blocks(i32* nocapture %Output,
; CHECK-NEXT: [[TEMP_09:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[TEMP_1_3]], [[FOR_INC_3]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ [[UNROLL_ITER]], [[FOR_BODY_PREHEADER_NEW]] ], [ [[NITER_NSUB_3:%.*]], [[FOR_INC_3]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[J_010]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP4]], 0
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP8]], 0
; CHECK-NEXT: br i1 [[TOBOOL]], label [[FOR_INC:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[J_010]]
-; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP5]], [[TEMP_09]]
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP9]], [[TEMP_09]]
; CHECK-NEXT: br label [[FOR_INC]]
; CHECK: for.inc:
; CHECK-NEXT: [[TEMP_1:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ [[TEMP_09]], [[FOR_BODY]] ]
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_010]], 1
; CHECK-NEXT: [[NITER_NSUB:%.*]] = sub i32 [[NITER]], 1
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC]]
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
-; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[TMP6]], 0
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
+; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[TMP10]], 0
; CHECK-NEXT: br i1 [[TOBOOL_1]], label [[FOR_INC_1:%.*]], label [[IF_THEN_1:%.*]]
-; CHECK: for.body.epil.1:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC_EPIL]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_1]], align 4
-; CHECK-NEXT: [[TOBOOL_EPIL_1:%.*]] = icmp eq i32 [[TMP7]], 0
-; CHECK-NEXT: br i1 [[TOBOOL_EPIL_1]], label [[FOR_INC_EPIL_1]], label [[IF_THEN_EPIL_1:%.*]]
-; CHECK: if.then.epil.1:
-; CHECK-NEXT: [[ARRAYIDX1_EPIL_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_EPIL]]
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX1_EPIL_1]], align 4
-; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add i32 [[TMP8]], [[TEMP_1_EPIL]]
-; CHECK-NEXT: br label [[FOR_INC_EPIL_1]]
-; CHECK: for.inc.epil.1:
-; CHECK-NEXT: [[TEMP_1_EPIL_1]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[TEMP_1_EPIL]], [[FOR_BODY_EPIL_1]] ]
-; CHECK-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[INC_EPIL]], 1
-; CHECK-NEXT: [[EPIL_ITER_SUB_1:%.*]] = sub i32 [[EPIL_ITER_SUB]], 1
-; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 [[EPIL_ITER_SUB_1]], 0
-; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_BODY_EPIL_2:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
-; CHECK: for.body.epil.2:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC_EPIL_1]]
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_2]], align 4
-; CHECK-NEXT: [[TOBOOL_EPIL_2:%.*]] = icmp eq i32 [[TMP9]], 0
-; CHECK-NEXT: br i1 [[TOBOOL_EPIL_2]], label [[FOR_INC_EPIL_2]], label [[IF_THEN_EPIL_2:%.*]]
-; CHECK: if.then.epil.2:
-; CHECK-NEXT: [[ARRAYIDX1_EPIL_2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_EPIL_1]]
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX1_EPIL_2]], align 4
-; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add i32 [[TMP10]], [[TEMP_1_EPIL_1]]
-; CHECK-NEXT: br label [[FOR_INC_EPIL_2]]
-; CHECK: for.inc.epil.2:
-; CHECK-NEXT: [[TEMP_1_EPIL_2]] = phi i32 [ [[ADD_EPIL_2]], [[IF_THEN_EPIL_2]] ], [ [[TEMP_1_EPIL_1]], [[FOR_BODY_EPIL_2]] ]
-; CHECK-NEXT: br label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: if.then.1:
; CHECK-NEXT: [[ARRAYIDX1_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC]]
; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX1_1]], align 4
@@ -203,41 +203,34 @@ define void @test_two_exits(i32* nocapture %Output,
; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_016]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[INC]], [[MAXJ]]
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY_1:%.*]], label [[CLEANUP_LOOPEXIT]]
-; CHECK: cleanup.loopexit:
-; CHECK-NEXT: [[TEMP_0_LCSSA_PH:%.*]] = phi i32 [ [[TEMP_0_ADD]], [[IF_END]] ], [ [[TEMP_015]], [[FOR_BODY]] ], [ [[TEMP_0_ADD]], [[FOR_BODY_1]] ], [ [[TEMP_0_ADD_1:%.*]], [[IF_END_1:%.*]] ], [ [[TEMP_0_ADD_1]], [[FOR_BODY_2:%.*]] ], [ [[TEMP_0_ADD_2:%.*]], [[IF_END_2:%.*]] ], [ [[TEMP_0_ADD_2]], [[FOR_BODY_3:%.*]] ], [ [[TEMP_0_ADD_3]], [[IF_END_3]] ]
-; CHECK-NEXT: br label [[CLEANUP]]
-; CHECK: cleanup:
-; CHECK-NEXT: [[TEMP_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TEMP_0_LCSSA_PH]], [[CLEANUP_LOOPEXIT]] ]
-; CHECK-NEXT: store i32 [[TEMP_0_LCSSA]], i32* [[OUTPUT:%.*]], align 4
-; CHECK-NEXT: ret void
; CHECK: for.body.1:
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ugt i32 [[TMP2]], 65535
-; CHECK-NEXT: br i1 [[CMP1_1]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_1]]
+; CHECK-NEXT: br i1 [[CMP1_1]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_1:%.*]]
; CHECK: if.end.1:
; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX2_1]], align 4
; CHECK-NEXT: [[TOBOOL_1:%.*]] = icmp eq i32 [[TMP3]], 0
; CHECK-NEXT: [[ADD_1:%.*]] = select i1 [[TOBOOL_1]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT: [[TEMP_0_ADD_1]] = add i32 [[ADD_1]], [[TEMP_0_ADD]]
+; CHECK-NEXT: [[TEMP_0_ADD_1:%.*]] = add i32 [[ADD_1]], [[TEMP_0_ADD]]
; CHECK-NEXT: [[INC_1:%.*]] = add nuw nsw i32 [[INC]], 1
; CHECK-NEXT: [[CMP_1:%.*]] = icmp ult i32 [[INC_1]], [[MAXJ]]
-; CHECK-NEXT: br i1 [[CMP_1]], label [[FOR_BODY_2]], label [[CLEANUP_LOOPEXIT]]
+; CHECK-NEXT: br i1 [[CMP_1]], label [[FOR_BODY_2:%.*]], label [[CLEANUP_LOOPEXIT]]
; CHECK: for.body.2:
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_1]]
; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ugt i32 [[TMP4]], 65535
-; CHECK-NEXT: br i1 [[CMP1_2]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_2]]
+; CHECK-NEXT: br i1 [[CMP1_2]], label [[CLEANUP_LOOPEXIT]], label [[IF_END_2:%.*]]
; CHECK: if.end.2:
; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC_1]]
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX2_2]], align 4
; CHECK-NEXT: [[TOBOOL_2:%.*]] = icmp eq i32 [[TMP5]], 0
; CHECK-NEXT: [[ADD_2:%.*]] = select i1 [[TOBOOL_2]], i32 0, i32 [[TMP4]]
-; CHECK-NEXT: [[TEMP_0_ADD_2]] = add i32 [[ADD_2]], [[TEMP_0_ADD_1]]
+; CHECK-NEXT: [[TEMP_0_ADD_2:%.*]] = add i32 [[ADD_2]], [[TEMP_0_ADD_1]]
; CHECK-NEXT: [[INC_2:%.*]] = add nuw nsw i32 [[INC_1]], 1
; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i32 [[INC_2]], [[MAXJ]]
-; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_BODY_3]], label [[CLEANUP_LOOPEXIT]]
+; CHECK-NEXT: br i1 [[CMP_2]], label [[FOR_BODY_3:%.*]], label [[CLEANUP_LOOPEXIT]]
; CHECK: for.body.3:
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_2]]
; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
@@ -252,6 +245,13 @@ define void @test_two_exits(i32* nocapture %Output,
; CHECK-NEXT: [[INC_3]] = add nuw i32 [[INC_2]], 1
; CHECK-NEXT: [[CMP_3:%.*]] = icmp ult i32 [[INC_3]], [[MAXJ]]
; CHECK-NEXT: br i1 [[CMP_3]], label [[FOR_BODY]], label [[CLEANUP_LOOPEXIT]]
+; CHECK: cleanup.loopexit:
+; CHECK-NEXT: [[TEMP_0_LCSSA_PH:%.*]] = phi i32 [ [[TEMP_0_ADD]], [[IF_END]] ], [ [[TEMP_015]], [[FOR_BODY]] ], [ [[TEMP_0_ADD]], [[FOR_BODY_1]] ], [ [[TEMP_0_ADD_1]], [[IF_END_1]] ], [ [[TEMP_0_ADD_1]], [[FOR_BODY_2]] ], [ [[TEMP_0_ADD_2]], [[IF_END_2]] ], [ [[TEMP_0_ADD_2]], [[FOR_BODY_3]] ], [ [[TEMP_0_ADD_3]], [[IF_END_3]] ]
+; CHECK-NEXT: br label [[CLEANUP]]
+; CHECK: cleanup:
+; CHECK-NEXT: [[TEMP_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TEMP_0_LCSSA_PH]], [[CLEANUP_LOOPEXIT]] ]
+; CHECK-NEXT: store i32 [[TEMP_0_LCSSA]], i32* [[OUTPUT:%.*]], align 4
+; CHECK-NEXT: ret void
;
i32* nocapture readonly %Condition,
i32* nocapture readonly %Input,
@@ -417,100 +417,100 @@ define void @test_four_blocks(i32* nocapture %Output,
; CHECK-NEXT: [[EPIL_ITER_SUB:%.*]] = sub i32 [[XTRAITER]], 1
; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 [[EPIL_ITER_SUB]], 0
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_BODY_EPIL_1:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA:%.*]]
-; CHECK: for.cond.cleanup.loopexit.epilog-lcssa:
-; CHECK-NEXT: [[TEMP_1_LCSSA_PH1:%.*]] = phi i32 [ [[TEMP_1_EPIL]], [[FOR_INC_EPIL]] ], [ [[TEMP_1_EPIL_1:%.*]], [[FOR_INC_EPIL_1:%.*]] ], [ [[TEMP_1_EPIL_2:%.*]], [[FOR_INC_EPIL_2:%.*]] ]
-; CHECK-NEXT: br label [[FOR_COND_CLEANUP_LOOPEXIT]]
-; CHECK: for.cond.cleanup.loopexit:
-; CHECK-NEXT: [[TEMP_1_LCSSA:%.*]] = phi i32 [ [[TEMP_1_LCSSA_PH]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ], [ [[TEMP_1_LCSSA_PH1]], [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]] ]
-; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
-; CHECK: for.cond.cleanup:
-; CHECK-NEXT: [[TEMP_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TEMP_1_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT]] ]
-; CHECK-NEXT: store i32 [[TEMP_0_LCSSA]], i32* [[OUTPUT:%.*]], align 4
-; CHECK-NEXT: ret void
-; CHECK: for.body:
-; CHECK-NEXT: [[TMP6:%.*]] = phi i32 [ [[DOTPRE]], [[FOR_BODY_LR_PH_NEW]] ], [ [[TMP23]], [[FOR_INC_3]] ]
-; CHECK-NEXT: [[J_027:%.*]] = phi i32 [ 1, [[FOR_BODY_LR_PH_NEW]] ], [ [[INC_3]], [[FOR_INC_3]] ]
-; CHECK-NEXT: [[TEMP_026:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH_NEW]] ], [ [[TEMP_1_3]], [[FOR_INC_3]] ]
-; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ [[UNROLL_ITER]], [[FOR_BODY_LR_PH_NEW]] ], [ [[NITER_NSUB_3:%.*]], [[FOR_INC_3]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[J_027]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[TMP7]], 65535
-; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[J_027]]
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX2]], align 4
-; CHECK-NEXT: [[CMP4:%.*]] = icmp ugt i32 [[TMP8]], [[TMP6]]
-; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
-; CHECK: if.then:
-; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP4]] to i32
-; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TEMP_026]], [[COND]]
-; CHECK-NEXT: br label [[FOR_INC:%.*]]
-; CHECK: if.else:
-; CHECK-NEXT: [[NOT_CMP4:%.*]] = xor i1 [[CMP4]], true
-; CHECK-NEXT: [[SUB:%.*]] = sext i1 [[NOT_CMP4]] to i32
-; CHECK-NEXT: [[SUB10_SINK:%.*]] = add i32 [[J_027]], [[SUB]]
-; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[SUB10_SINK]]
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4
-; CHECK-NEXT: [[SUB13:%.*]] = sub i32 [[TEMP_026]], [[TMP9]]
-; CHECK-NEXT: br label [[FOR_INC]]
-; CHECK: for.inc:
-; CHECK-NEXT: [[TEMP_1:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ [[SUB13]], [[IF_ELSE]] ]
-; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_027]], 1
-; CHECK-NEXT: [[NITER_NSUB:%.*]] = sub i32 [[NITER]], 1
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC]]
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
-; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ugt i32 [[TMP10]], 65535
-; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC]]
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX2_1]], align 4
-; CHECK-NEXT: [[CMP4_1:%.*]] = icmp ugt i32 [[TMP11]], [[TMP8]]
-; CHECK-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]]
; CHECK: for.body.epil.1:
; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC_EPIL]]
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_1]], align 4
-; CHECK-NEXT: [[CMP1_EPIL_1:%.*]] = icmp ugt i32 [[TMP12]], 65535
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_1]], align 4
+; CHECK-NEXT: [[CMP1_EPIL_1:%.*]] = icmp ugt i32 [[TMP6]], 65535
; CHECK-NEXT: [[ARRAYIDX2_EPIL_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_EPIL]]
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX2_EPIL_1]], align 4
-; CHECK-NEXT: [[CMP4_EPIL_1:%.*]] = icmp ugt i32 [[TMP13]], [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX2_EPIL_1]], align 4
+; CHECK-NEXT: [[CMP4_EPIL_1:%.*]] = icmp ugt i32 [[TMP7]], [[TMP4]]
; CHECK-NEXT: br i1 [[CMP1_EPIL_1]], label [[IF_THEN_EPIL_1:%.*]], label [[IF_ELSE_EPIL_1:%.*]]
; CHECK: if.else.epil.1:
; CHECK-NEXT: [[NOT_CMP4_EPIL_1:%.*]] = xor i1 [[CMP4_EPIL_1]], true
; CHECK-NEXT: [[SUB_EPIL_1:%.*]] = sext i1 [[NOT_CMP4_EPIL_1]] to i32
; CHECK-NEXT: [[SUB10_SINK_EPIL_1:%.*]] = add i32 [[INC_EPIL]], [[SUB_EPIL_1]]
; CHECK-NEXT: [[ARRAYIDX11_EPIL_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[SUB10_SINK_EPIL_1]]
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX11_EPIL_1]], align 4
-; CHECK-NEXT: [[SUB13_EPIL_1:%.*]] = sub i32 [[TEMP_1_EPIL]], [[TMP14]]
-; CHECK-NEXT: br label [[FOR_INC_EPIL_1]]
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[ARRAYIDX11_EPIL_1]], align 4
+; CHECK-NEXT: [[SUB13_EPIL_1:%.*]] = sub i32 [[TEMP_1_EPIL]], [[TMP8]]
+; CHECK-NEXT: br label [[FOR_INC_EPIL_1:%.*]]
; CHECK: if.then.epil.1:
; CHECK-NEXT: [[COND_EPIL_1:%.*]] = zext i1 [[CMP4_EPIL_1]] to i32
; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add i32 [[TEMP_1_EPIL]], [[COND_EPIL_1]]
; CHECK-NEXT: br label [[FOR_INC_EPIL_1]]
; CHECK: for.inc.epil.1:
-; CHECK-NEXT: [[TEMP_1_EPIL_1]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[SUB13_EPIL_1]], [[IF_ELSE_EPIL_1]] ]
+; CHECK-NEXT: [[TEMP_1_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], [[IF_THEN_EPIL_1]] ], [ [[SUB13_EPIL_1]], [[IF_ELSE_EPIL_1]] ]
; CHECK-NEXT: [[INC_EPIL_1:%.*]] = add nuw i32 [[INC_EPIL]], 1
; CHECK-NEXT: [[EPIL_ITER_SUB_1:%.*]] = sub i32 [[EPIL_ITER_SUB]], 1
; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 [[EPIL_ITER_SUB_1]], 0
; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label [[FOR_BODY_EPIL_2:%.*]], label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
; CHECK: for.body.epil.2:
; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC_EPIL_1]]
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_2]], align 4
-; CHECK-NEXT: [[CMP1_EPIL_2:%.*]] = icmp ugt i32 [[TMP15]], 65535
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX_EPIL_2]], align 4
+; CHECK-NEXT: [[CMP1_EPIL_2:%.*]] = icmp ugt i32 [[TMP9]], 65535
; CHECK-NEXT: [[ARRAYIDX2_EPIL_2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_EPIL_1]]
-; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX2_EPIL_2]], align 4
-; CHECK-NEXT: [[CMP4_EPIL_2:%.*]] = icmp ugt i32 [[TMP16]], [[TMP13]]
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX2_EPIL_2]], align 4
+; CHECK-NEXT: [[CMP4_EPIL_2:%.*]] = icmp ugt i32 [[TMP10]], [[TMP7]]
; CHECK-NEXT: br i1 [[CMP1_EPIL_2]], label [[IF_THEN_EPIL_2:%.*]], label [[IF_ELSE_EPIL_2:%.*]]
; CHECK: if.else.epil.2:
; CHECK-NEXT: [[NOT_CMP4_EPIL_2:%.*]] = xor i1 [[CMP4_EPIL_2]], true
; CHECK-NEXT: [[SUB_EPIL_2:%.*]] = sext i1 [[NOT_CMP4_EPIL_2]] to i32
; CHECK-NEXT: [[SUB10_SINK_EPIL_2:%.*]] = add i32 [[INC_EPIL_1]], [[SUB_EPIL_2]]
; CHECK-NEXT: [[ARRAYIDX11_EPIL_2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[SUB10_SINK_EPIL_2]]
-; CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARRAYIDX11_EPIL_2]], align 4
-; CHECK-NEXT: [[SUB13_EPIL_2:%.*]] = sub i32 [[TEMP_1_EPIL_1]], [[TMP17]]
-; CHECK-NEXT: br label [[FOR_INC_EPIL_2]]
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX11_EPIL_2]], align 4
+; CHECK-NEXT: [[SUB13_EPIL_2:%.*]] = sub i32 [[TEMP_1_EPIL_1]], [[TMP11]]
+; CHECK-NEXT: br label [[FOR_INC_EPIL_2:%.*]]
; CHECK: if.then.epil.2:
; CHECK-NEXT: [[COND_EPIL_2:%.*]] = zext i1 [[CMP4_EPIL_2]] to i32
; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add i32 [[TEMP_1_EPIL_1]], [[COND_EPIL_2]]
; CHECK-NEXT: br label [[FOR_INC_EPIL_2]]
; CHECK: for.inc.epil.2:
-; CHECK-NEXT: [[TEMP_1_EPIL_2]] = phi i32 [ [[ADD_EPIL_2]], [[IF_THEN_EPIL_2]] ], [ [[SUB13_EPIL_2]], [[IF_ELSE_EPIL_2]] ]
+; CHECK-NEXT: [[TEMP_1_EPIL_2:%.*]] = phi i32 [ [[ADD_EPIL_2]], [[IF_THEN_EPIL_2]] ], [ [[SUB13_EPIL_2]], [[IF_ELSE_EPIL_2]] ]
; CHECK-NEXT: br label [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]]
+; CHECK: for.cond.cleanup.loopexit.epilog-lcssa:
+; CHECK-NEXT: [[TEMP_1_LCSSA_PH1:%.*]] = phi i32 [ [[TEMP_1_EPIL]], [[FOR_INC_EPIL]] ], [ [[TEMP_1_EPIL_1]], [[FOR_INC_EPIL_1]] ], [ [[TEMP_1_EPIL_2]], [[FOR_INC_EPIL_2]] ]
+; CHECK-NEXT: br label [[FOR_COND_CLEANUP_LOOPEXIT]]
+; CHECK: for.cond.cleanup.loopexit:
+; CHECK-NEXT: [[TEMP_1_LCSSA:%.*]] = phi i32 [ [[TEMP_1_LCSSA_PH]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ], [ [[TEMP_1_LCSSA_PH1]], [[FOR_COND_CLEANUP_LOOPEXIT_EPILOG_LCSSA]] ]
+; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
+; CHECK: for.cond.cleanup:
+; CHECK-NEXT: [[TEMP_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TEMP_1_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT]] ]
+; CHECK-NEXT: store i32 [[TEMP_0_LCSSA]], i32* [[OUTPUT:%.*]], align 4
+; CHECK-NEXT: ret void
+; CHECK: for.body:
+; CHECK-NEXT: [[TMP12:%.*]] = phi i32 [ [[DOTPRE]], [[FOR_BODY_LR_PH_NEW]] ], [ [[TMP23]], [[FOR_INC_3]] ]
+; CHECK-NEXT: [[J_027:%.*]] = phi i32 [ 1, [[FOR_BODY_LR_PH_NEW]] ], [ [[INC_3]], [[FOR_INC_3]] ]
+; CHECK-NEXT: [[TEMP_026:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH_NEW]] ], [ [[TEMP_1_3]], [[FOR_INC_3]] ]
+; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ [[UNROLL_ITER]], [[FOR_BODY_LR_PH_NEW]] ], [ [[NITER_NSUB_3:%.*]], [[FOR_INC_3]] ]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[J_027]]
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[TMP13]], 65535
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[J_027]]
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX2]], align 4
+; CHECK-NEXT: [[CMP4:%.*]] = icmp ugt i32 [[TMP14]], [[TMP12]]
+; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP4]] to i32
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TEMP_026]], [[COND]]
+; CHECK-NEXT: br label [[FOR_INC:%.*]]
+; CHECK: if.else:
+; CHECK-NEXT: [[NOT_CMP4:%.*]] = xor i1 [[CMP4]], true
+; CHECK-NEXT: [[SUB:%.*]] = sext i1 [[NOT_CMP4]] to i32
+; CHECK-NEXT: [[SUB10_SINK:%.*]] = add i32 [[J_027]], [[SUB]]
+; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[SUB10_SINK]]
+; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4
+; CHECK-NEXT: [[SUB13:%.*]] = sub i32 [[TEMP_026]], [[TMP15]]
+; CHECK-NEXT: br label [[FOR_INC]]
+; CHECK: for.inc:
+; CHECK-NEXT: [[TEMP_1:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ [[SUB13]], [[IF_ELSE]] ]
+; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[J_027]], 1
+; CHECK-NEXT: [[NITER_NSUB:%.*]] = sub i32 [[NITER]], 1
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[CONDITION]], i32 [[INC]]
+; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
+; CHECK-NEXT: [[CMP1_1:%.*]] = icmp ugt i32 [[TMP16]], 65535
+; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC]]
+; CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARRAYIDX2_1]], align 4
+; CHECK-NEXT: [[CMP4_1:%.*]] = icmp ugt i32 [[TMP17]], [[TMP14]]
+; CHECK-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]]
; CHECK: if.else.1:
; CHECK-NEXT: [[NOT_CMP4_1:%.*]] = xor i1 [[CMP4_1]], true
; CHECK-NEXT: [[SUB_1:%.*]] = sext i1 [[NOT_CMP4_1]] to i32
@@ -532,7 +532,7 @@ define void @test_four_blocks(i32* nocapture %Output,
; CHECK-NEXT: [[CMP1_2:%.*]] = icmp ugt i32 [[TMP19]], 65535
; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, i32* [[INPUT]], i32 [[INC_1]]
; CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[ARRAYIDX2_2]], align 4
-; CHECK-NEXT: [[CMP4_2:%.*]] = icmp ugt i32 [[TMP20]], [[TMP11]]
+; CHECK-NEXT: [[CMP4_2:%.*]] = icmp ugt i32 [[TMP20]], [[TMP17]]
; CHECK-NEXT: br i1 [[CMP1_2]], label [[IF_THEN_2:%.*]], label [[IF_ELSE_2:%.*]]
; CHECK: if.else.2:
; CHECK-NEXT: [[NOT_CMP4_2:%.*]] = xor i1 [[CMP4_2]], true
@@ -742,10 +742,6 @@ define void @iterate_inc(%struct.Node* %n, i32 %limit) {
; CHECK-NEXT: [[TMP2:%.*]] = load %struct.Node*, %struct.Node** [[TMP1]], align 4
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq %struct.Node* [[TMP2]], null
; CHECK-NEXT: br i1 [[TOBOOL]], label [[WHILE_END_LOOPEXIT]], label [[LAND_RHS_1:%.*]]
-; CHECK: while.end.loopexit:
-; CHECK-NEXT: br label [[WHILE_END]]
-; CHECK: while.end:
-; CHECK-NEXT: ret void
; CHECK: land.rhs.1:
; CHECK-NEXT: [[VAL_1:%.*]] = getelementptr inbounds [[STRUCT_NODE]], %struct.Node* [[TMP2]], i32 0, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[VAL_1]], align 4
@@ -782,6 +778,10 @@ define void @iterate_inc(%struct.Node* %n, i32 %limit) {
; CHECK-NEXT: [[TMP11]] = load %struct.Node*, %struct.Node** [[TMP10]], align 4
; CHECK-NEXT: [[TOBOOL_3:%.*]] = icmp eq %struct.Node* [[TMP11]], null
; CHECK-NEXT: br i1 [[TOBOOL_3]], label [[WHILE_END_LOOPEXIT]], label [[LAND_RHS]]
+; CHECK: while.end.loopexit:
+; CHECK-NEXT: br label [[WHILE_END]]
+; CHECK: while.end:
+; CHECK-NEXT: ret void
;
entry:
%tobool5 = icmp eq %struct.Node* %n, null
diff --git a/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll b/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll
index ea18d3aa1054..33151c68b319 100644
--- a/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll
+++ b/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll
@@ -20,8 +20,6 @@ define void @test(i32* %x, i32 %n) {
; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[X]], i64 1
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[REM]], 1
; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY_1:%.*]], label [[WHILE_END]]
-; CHECK: while.end:
-; CHECK-NEXT: ret void
; CHECK: while.body.1:
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[INCDEC_PTR]], align 4
; CHECK-NEXT: [[CMP1_1:%.*]] = icmp slt i32 [[TMP1]], 10
@@ -40,6 +38,8 @@ define void @test(i32* %x, i32 %n) {
; CHECK: if.then.2:
; CHECK-NEXT: store i32 0, i32* [[INCDEC_PTR_1]], align 4
; CHECK-NEXT: br label [[WHILE_END]]
+; CHECK: while.end:
+; CHECK-NEXT: ret void
;
entry:
%sub = add nsw i32 %n, -1
@@ -76,9 +76,9 @@ define i32 @test2(i32 %l86) {
; CHECK-NEXT: [[L86_OFF:%.*]] = add i32 [[L86:%.*]], -1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[L86_OFF]], 24
; CHECK-NEXT: [[DOTNOT30:%.*]] = icmp ne i32 [[L86]], 25
-; CHECK-NEXT: [[SPEC_SELECT24:%.*]] = zext i1 [[DOTNOT30]] to i32
-; CHECK-NEXT: [[COMMON_RET31_OP:%.*]] = select i1 [[SWITCH]], i32 0, i32 [[SPEC_SELECT24]]
-; CHECK-NEXT: ret i32 [[COMMON_RET31_OP]]
+; CHECK-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[DOTNOT30]] to i32
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[SWITCH]], i32 0, i32 [[SPEC_SELECT]]
+; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
;
entry:
br label %for.body.i.i
diff --git a/llvm/test/Transforms/LoopUnroll/full-unroll-keep-first-exit.ll b/llvm/test/Transforms/LoopUnroll/full-unroll-keep-first-exit.ll
index 316051715584..cdc8e944715e 100644
--- a/llvm/test/Transforms/LoopUnroll/full-unroll-keep-first-exit.ll
+++ b/llvm/test/Transforms/LoopUnroll/full-unroll-keep-first-exit.ll
@@ -15,12 +15,12 @@ define void @s32_max1(i32 %n, i32* %p) {
; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[N]], [[ADD]]
; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]]
-; CHECK: do.end:
-; CHECK-NEXT: ret void
; CHECK: do.body.1:
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, i32* [[P]], i32 [[INC]]
; CHECK-NEXT: store i32 [[INC]], i32* [[ARRAYIDX_1]], align 4
; CHECK-NEXT: br label [[DO_END]]
+; CHECK: do.end:
+; CHECK-NEXT: ret void
;
entry:
%add = add i32 %n, 1
@@ -51,8 +51,6 @@ define void @s32_max2(i32 %n, i32* %p) {
; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[N]], [[ADD]]
; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]]
-; CHECK: do.end:
-; CHECK-NEXT: ret void
; CHECK: do.body.1:
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, i32* [[P]], i32 [[INC]]
; CHECK-NEXT: store i32 [[INC]], i32* [[ARRAYIDX_1]], align 4
@@ -60,6 +58,8 @@ define void @s32_max2(i32 %n, i32* %p) {
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, i32* [[P]], i32 [[INC_1]]
; CHECK-NEXT: store i32 [[INC_1]], i32* [[ARRAYIDX_2]], align 4
; CHECK-NEXT: br label [[DO_END]]
+; CHECK: do.end:
+; CHECK-NEXT: ret void
;
entry:
%add = add i32 %n, 2
@@ -163,12 +163,12 @@ define void @u32_max1(i32 %n, i32* %p) {
; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[N]], [[ADD]]
; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]]
-; CHECK: do.end:
-; CHECK-NEXT: ret void
; CHECK: do.body.1:
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, i32* [[P]], i32 [[INC]]
; CHECK-NEXT: store i32 [[INC]], i32* [[ARRAYIDX_1]], align 4
; CHECK-NEXT: br label [[DO_END]]
+; CHECK: do.end:
+; CHECK-NEXT: ret void
;
entry:
%add = add i32 %n, 1
@@ -199,8 +199,6 @@ define void @u32_max2(i32 %n, i32* %p) {
; CHECK-NEXT: [[INC:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[N]], [[ADD]]
; CHECK-NEXT: br i1 [[CMP]], label [[DO_BODY_1:%.*]], label [[DO_END:%.*]]
-; CHECK: do.end:
-; CHECK-NEXT: ret void
; CHECK: do.body.1:
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr i32, i32* [[P]], i32 [[INC]]
; CHECK-NEXT: store i32 [[INC]], i32* [[ARRAYIDX_1]], align 4
@@ -208,6 +206,8 @@ define void @u32_max2(i32 %n, i32* %p) {
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr i32, i32* [[P]], i32 [[INC_1]]
; CHECK-NEXT: store i32 [[INC_1]], i32* [[ARRAYIDX_2]], align 4
; CHECK-NEXT: br label [[DO_END]]
+; CHECK: do.end:
+; CHECK-NEXT: ret void
;
entry:
%add = add i32 %n, 2
diff --git a/llvm/test/Transforms/LoopUnroll/full-unroll-one-unpredictable-exit.ll b/llvm/test/Transforms/LoopUnroll/full-unroll-one-unpredictable-exit.ll
index 095a7c1e1dd1..b7d7e00fa0c9 100644
--- a/llvm/test/Transforms/LoopUnroll/full-unroll-one-unpredictable-exit.ll
+++ b/llvm/test/Transforms/LoopUnroll/full-unroll-one-unpredictable-exit.ll
@@ -34,11 +34,11 @@ define i1 @test_latch() {
; CHECK-NEXT: [[LOAD2_1:%.*]] = load i64, i64* [[GEP2_1]], align 8
; CHECK-NEXT: [[EXITCOND2_1:%.*]] = icmp eq i64 [[LOAD1_1]], [[LOAD2_1]]
; CHECK-NEXT: br i1 [[EXITCOND2_1]], label [[LATCH_1:%.*]], label [[EXIT]]
+; CHECK: latch.1:
+; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: [[EXIT_VAL:%.*]] = phi i1 [ false, [[LOOP]] ], [ false, [[LATCH]] ], [ true, [[LATCH_1]] ]
; CHECK-NEXT: ret i1 [[EXIT_VAL]]
-; CHECK: latch.1:
-; CHECK-NEXT: br label [[EXIT]]
;
start:
%a1 = alloca [2 x i64], align 8
@@ -95,22 +95,22 @@ define i1 @test_non_latch() {
; CHECK-NEXT: [[LOAD2:%.*]] = load i64, i64* [[GEP2]], align 8
; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp eq i64 [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: br i1 [[EXITCOND2]], label [[LOOP_1:%.*]], label [[EXIT:%.*]]
-; CHECK: exit:
-; CHECK-NEXT: [[EXIT_VAL:%.*]] = phi i1 [ false, [[LATCH]] ], [ false, [[LATCH_1:%.*]] ], [ true, [[LOOP_2:%.*]] ], [ false, [[LATCH_2:%.*]] ]
-; CHECK-NEXT: ret i1 [[EXIT_VAL]]
; CHECK: loop.1:
-; CHECK-NEXT: br label [[LATCH_1]]
+; CHECK-NEXT: br label [[LATCH_1:%.*]]
; CHECK: latch.1:
; CHECK-NEXT: [[GEP1_1:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[A1]], i64 0, i64 1
; CHECK-NEXT: [[GEP2_1:%.*]] = getelementptr inbounds [2 x i64], [2 x i64]* [[A2]], i64 0, i64 1
; CHECK-NEXT: [[LOAD1_1:%.*]] = load i64, i64* [[GEP1_1]], align 8
; CHECK-NEXT: [[LOAD2_1:%.*]] = load i64, i64* [[GEP2_1]], align 8
; CHECK-NEXT: [[EXITCOND2_1:%.*]] = icmp eq i64 [[LOAD1_1]], [[LOAD2_1]]
-; CHECK-NEXT: br i1 [[EXITCOND2_1]], label [[LOOP_2]], label [[EXIT]]
+; CHECK-NEXT: br i1 [[EXITCOND2_1]], label [[LOOP_2:%.*]], label [[EXIT]]
; CHECK: loop.2:
-; CHECK-NEXT: br i1 true, label [[EXIT]], label [[LATCH_2]]
+; CHECK-NEXT: br i1 true, label [[EXIT]], label [[LATCH_2:%.*]]
; CHECK: latch.2:
; CHECK-NEXT: br label [[EXIT]]
+; CHECK: exit:
+; CHECK-NEXT: [[EXIT_VAL:%.*]] = phi i1 [ false, [[LATCH]] ], [ false, [[LATCH_1]] ], [ true, [[LOOP_2]] ], [ false, [[LATCH_2]] ]
+; CHECK-NEXT: ret i1 [[EXIT_VAL]]
;
start:
%a1 = alloca [2 x i64], align 8
diff --git a/llvm/test/Transforms/LoopUnroll/multiple-exits.ll b/llvm/test/Transforms/LoopUnroll/multiple-exits.ll
index 0bea86350b99..9f40f51c10e6 100644
--- a/llvm/test/Transforms/LoopUnroll/multiple-exits.ll
+++ b/llvm/test/Transforms/LoopUnroll/multiple-exits.ll
@@ -14,8 +14,6 @@ define void @test1() {
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: call void @bar()
; CHECK-NEXT: br label [[LATCH_1:%.*]]
-; CHECK: exit:
-; CHECK-NEXT: ret void
; CHECK: latch.1:
</cut>
3 years, 7 months
- 1
- 0
[TCWG CI] 482.sphinx3 slowed down by 6% after llvm: Making the code compliant to the documentation about Floating Point support default values for C/C++. FPP-MODEL=PRECISE enables FFP-CONTRACT(FMA is enabled).
by ci_notify＠linaro.org
After llvm commit f04e387055e495e3e14570087d68e93593cf2918
Author: Zahira Ammarguellat <zahira.ammarguellat(a)intel.com>
Making the code compliant to the documentation about Floating Point
support default values for C/C++. FPP-MODEL=PRECISE enables
FFP-CONTRACT(FMA is enabled).
the following benchmarks slowed down by more than 2%:
- 482.sphinx3 slowed down by 6% from 25875 to 27484 perf samples
- 482.sphinx3:[.] mgau_eval slowed down by 12% from 9996 to 11165 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O2
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-f04e387055e495e3e14570087d68e93593cf2918
cd investigate-llvm-f04e387055e495e3e14570087d68e93593cf2918
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach f04e387055e495e3e14570087d68e93593cf2918
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 491beae71d69960a3bb0298b17d4ef1f3119b767
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit f04e387055e495e3e14570087d68e93593cf2918
Author: Zahira Ammarguellat <zahira.ammarguellat(a)intel.com>
Date: Tue Nov 9 09:35:25 2021 -0500
Making the code compliant to the documentation about Floating Point
support default values for C/C++. FPP-MODEL=PRECISE enables
FFP-CONTRACT(FMA is enabled).
Fix for https://bugs.llvm.org/show_bug.cgi?id=50222
---
clang/docs/ReleaseNotes.rst | 10 +++
clang/docs/UsersManual.rst | 47 +++++++++++-
clang/lib/Driver/ToolChains/Clang.cpp | 48 +++++++-----
clang/test/CodeGen/ffp-contract-option.c | 127 +++++++++++++++++++++++++++++--
clang/test/CodeGen/ffp-model.c | 48 ++++++++++++
clang/test/CodeGen/ppc-emmintrin.c | 4 +-
clang/test/CodeGen/ppc-xmmintrin.c | 4 +-
clang/test/Driver/fp-model.c | 2 +-
clang/test/Misc/ffp-contract.c | 10 +++
9 files changed, 263 insertions(+), 37 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 57c5150becae..00582b689862 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -202,6 +202,16 @@ Arm and AArch64 Support in Clang
architecture features, but will enable certain optimizations specific to
Cortex-A57 CPUs and enable the use of a more accurate scheduling model.
+
+Floating Point Support in Clang
+-------------------------------
+- The -ffp-model=precise now implies -ffp-contract=on rather than
+ -ffp-contract=fast, and the documentation of these features has been
+ clarified. Previously, the documentation claimed that -ffp-model=precise was
+ the default, but this was incorrect because the precise model implied
+ -ffp-contract=fast, whereas the default behavior is -ffp-contract=on.
+ -ffp-model=precise is now exactly the default mode of the compiler.
+
Internal API Changes
--------------------
diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst
index 8c6922db6b37..406efb093d55 100644
--- a/clang/docs/UsersManual.rst
+++ b/clang/docs/UsersManual.rst
@@ -1260,8 +1260,49 @@ installed.
Controlling Floating Point Behavior
-----------------------------------
-Clang provides a number of ways to control floating point behavior. The options
-are listed below.
+Clang provides a number of ways to control floating point behavior, including
+with command line options and source pragmas. This section
+describes the various floating point semantic modes and the corresponding options.
+
+.. csv-table:: Floating Point Semantic Modes
+ :header: "Mode", "Values"
+ :widths: 15, 30, 30
+
+ "ffp-exception-behavior", "{ignore, strict, may_trap}",
+ "fenv_access", "{off, on}", "(none)"
+ "frounding-math", "{dynamic, tonearest, downward, upward, towardzero}"
+ "ffp-contract", "{on, off, fast, fast-honor-pragmas}"
+ "fdenormal-fp-math", "{IEEE, PreserveSign, PositiveZero}"
+ "fdenormal-fp-math-fp32", "{IEEE, PreserveSign, PositiveZero}"
+ "fmath-errno", "{on, off}"
+ "fhonor-nans", "{on, off}"
+ "fhonor-infinities", "{on, off}"
+ "fsigned-zeros", "{on, off}"
+ "freciprocal-math", "{on, off}"
+ "allow_approximate_fns", "{on, off}"
+ "fassociative-math", "{on, off}"
+
+This table describes the option settings that correspond to the three
+floating point semantic models: precise (the default), strict, and fast.
+
+
+.. csv-table:: Floating Point Models
+ :header: "Mode", "Precise", "Strict", "Fast"
+ :widths: 25, 15, 15, 15
+
+ "except_behavior", "ignore", "strict", "ignore"
+ "fenv_access", "off", "on", "off"
+ "rounding_mode", "tonearest", "dynamic", "tonearest"
+ "contract", "on", "off", "fast"
+ "denormal_fp_math", "IEEE", "IEEE", "PreserveSign"
+ "denormal_fp32_math", "IEEE","IEEE", "PreserveSign"
+ "support_math_errno", "on", "on", "off"
+ "no_honor_nans", "off", "off", "on"
+ "no_honor_infinities", "off", "off", "on"
+ "no_signed_zeros", "off", "off", "on"
+ "allow_reciprocal", "off", "off", "on"
+ "allow_approximate_fns", "off", "off", "on"
+ "allow_reassociation", "off", "off", "on"
.. option:: -ffast-math
@@ -1467,7 +1508,7 @@ Note that floating-point operations performed as part of constant initialization
and ``fast``.
Details:
- * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=fast``). This is the default behavior.
+ * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=on``). This is the default behavior.
* ``strict`` Enables ``-frounding-math`` and ``-ffp-exception-behavior=strict``, and disables contractions (FMA). All of the ``-ffast-math`` enablements are disabled. Enables ``STDC FENV_ACCESS``: by default ``FENV_ACCESS`` is disabled. This option setting behaves as though ``#pragma STDC FENV_ACESS ON`` appeared at the top of the source file.
* ``fast`` Behaves identically to specifying both ``-ffast-math`` and ``ffp-contract=fast``
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index e8ad105a7829..5d6f8e9fba0e 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2666,10 +2666,14 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
llvm::DenormalMode DenormalFPMath = DefaultDenormalFPMath;
llvm::DenormalMode DenormalFP32Math = DefaultDenormalFP32Math;
- StringRef FPContract = "";
+ // CUDA and HIP don't rely on the frontend to pass an ffp-contract option.
+ // If one wasn't given by the user, don't pass it here.
+ StringRef FPContract;
+ if (!JA.isDeviceOffloading(Action::OFK_Cuda) &&
+ !JA.isOffloading(Action::OFK_HIP))
+ FPContract = "on";
bool StrictFPModel = false;
-
if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) {
CmdArgs.push_back("-mlimit-float-precision");
CmdArgs.push_back(A->getValue());
@@ -2691,7 +2695,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
ReciprocalMath = false;
SignedZeros = true;
// -fno_fast_math restores default denormal and fpcontract handling
- FPContract = "";
+ FPContract = "on";
DenormalFPMath = llvm::DenormalMode::getIEEE();
// FIXME: The target may have picked a non-IEEE default mode here based on
@@ -2711,12 +2715,10 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
// ffp-model= is a Driver option, it is entirely rewritten into more
// granular options before being passed into cc1.
// Use the gcc option in the switch below.
- if (!FPModel.empty() && !FPModel.equals(Val)) {
+ if (!FPModel.empty() && !FPModel.equals(Val))
D.Diag(clang::diag::warn_drv_overriding_flag_option)
- << Args.MakeArgString("-ffp-model=" + FPModel)
- << Args.MakeArgString("-ffp-model=" + Val);
- FPContract = "";
- }
+ << Args.MakeArgString("-ffp-model=" + FPModel)
+ << Args.MakeArgString("-ffp-model=" + Val);
if (Val.equals("fast")) {
optID = options::OPT_ffast_math;
FPModel = Val;
@@ -2724,7 +2726,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
} else if (Val.equals("precise")) {
optID = options::OPT_ffp_contract;
FPModel = Val;
- FPContract = "fast";
+ FPContract = "on";
PreciseFPModel = true;
} else if (Val.equals("strict")) {
StrictFPModel = true;
@@ -2812,9 +2814,9 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
case options::OPT_ffp_contract: {
StringRef Val = A->getValue();
if (PreciseFPModel) {
- // -ffp-model=precise enables ffp-contract=fast as a side effect
- // the FPContract value has already been set to a string literal
- // and the Val string isn't a pertinent value.
+ // -ffp-model=precise enables ffp-contract=on.
+ // -ffp-model=precise sets PreciseFPModel to on and Val to
+ // "precise". FPContract is set.
;
} else if (Val.equals("fast") || Val.equals("on") || Val.equals("off"))
FPContract = Val;
@@ -2907,23 +2909,27 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D,
AssociativeMath = false;
ReciprocalMath = false;
SignedZeros = true;
- TrappingMath = false;
- RoundingFPMath = false;
// -fno_fast_math restores default denormal and fpcontract handling
DenormalFPMath = DefaultDenormalFPMath;
DenormalFP32Math = llvm::DenormalMode::getIEEE();
- FPContract = "";
+ if (!JA.isDeviceOffloading(Action::OFK_Cuda) &&
+ !JA.isOffloading(Action::OFK_HIP))
+ if (FPContract == "fast") {
+ FPContract = "on";
+ D.Diag(clang::diag::warn_drv_overriding_flag_option)
+ << "-ffp-contract=fast"
+ << "-ffp-contract=on";
+ }
break;
}
if (StrictFPModel) {
// If -ffp-model=strict has been specified on command line but
// subsequent options conflict then emit warning diagnostic.
- if (HonorINFs && HonorNaNs &&
- !AssociativeMath && !ReciprocalMath &&
- SignedZeros && TrappingMath && RoundingFPMath &&
- (FPContract.equals("off") || FPContract.empty()) &&
- DenormalFPMath == llvm::DenormalMode::getIEEE() &&
- DenormalFP32Math == llvm::DenormalMode::getIEEE())
+ if (HonorINFs && HonorNaNs && !AssociativeMath && !ReciprocalMath &&
+ SignedZeros && TrappingMath && RoundingFPMath &&
+ DenormalFPMath == llvm::DenormalMode::getIEEE() &&
+ DenormalFP32Math == llvm::DenormalMode::getIEEE() &&
+ FPContract.equals("off"))
// OK: Current Arg doesn't conflict with -ffp-model=strict
;
else {
diff --git a/clang/test/CodeGen/ffp-contract-option.c b/clang/test/CodeGen/ffp-contract-option.c
index 52b750795940..857a9c2369ef 100644
--- a/clang/test/CodeGen/ffp-contract-option.c
+++ b/clang/test/CodeGen/ffp-contract-option.c
@@ -1,9 +1,120 @@
-// RUN: %clang_cc1 -O3 -ffp-contract=fast -triple=aarch64-apple-darwin -S -o - %s | FileCheck %s
-// REQUIRES: aarch64-registered-target
-
-float fma_test1(float a, float b, float c) {
-// CHECK: fmadd
- float x = a * b;
- float y = x + c;
- return y;
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 -triple=x86_64 %s -emit-llvm -o - \
+// RUN:| FileCheck --check-prefixes CHECK,CHECK-DEFAULT %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffp-contract=off %s -emit-llvm -o - \
+// RUN:| FileCheck --check-prefixes CHECK,CHECK-DEFAULT %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffp-contract=on %s -emit-llvm -o - \
+// RUN:| FileCheck --check-prefixes CHECK,CHECK-ON %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffp-contract=fast %s -emit-llvm -o - \
+// RUN:| FileCheck --check-prefixes CHECK,CHECK-CONTRACTFAST %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffast-math %s -emit-llvm -o - \
+// RUN:| FileCheck --check-prefixes CHECK,CHECK-CONTRACTOFF %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffast-math -ffp-contract=off %s -emit-llvm \
+// RUN: -o - | FileCheck --check-prefixes CHECK,CHECK-CONTRACTOFF %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffast-math -ffp-contract=on %s -emit-llvm \
+// RUN: -o - | FileCheck --check-prefixes CHECK,CHECK-ONFAST %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffast-math -ffp-contract=fast %s -emit-llvm \
+// RUN: -o - | FileCheck --check-prefixes CHECK,CHECK-FASTFAST %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffp-contract=fast -ffast-math %s \
+// RUN: -emit-llvm \
+// RUN: -o - | FileCheck --check-prefixes CHECK,CHECK-FASTFAST %s
+
+// RUN: %clang_cc1 -triple=x86_64 -ffp-contract=off -fmath-errno \
+// RUN: -fno-rounding-math %s -emit-llvm -o - \
+// RUN: -o - | FileCheck --check-prefixes CHECK,CHECK-NOFAST %s
+
+// RUN: %clang -S -emit-llvm -fno-fast-math %s -o - \
+// RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-FPC-ON
+
+// RUN: %clang -S -emit-llvm -ffp-contract=fast -fno-fast-math \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPC-ON
+
+// RUN: %clang -S -emit-llvm -ffp-contract=on -fno-fast-math \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPC-ON
+
+// RUN: %clang -S -emit-llvm -ffp-contract=off -fno-fast-math \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPC-OFF
+
+// RUN: %clang -S -emit-llvm -ffp-model=fast -fno-fast-math \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPC-ON
+
+// RUN: %clang -S -emit-llvm -ffp-model=precise -fno-fast-math \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPC-ON
+
+// RUN: %clang -S -emit-llvm -ffp-model=strict -fno-fast-math \
+// RUN: -target x86_64 %s -o - | FileCheck %s \
+// RUN: --check-prefixes=CHECK,CHECK-FPSC-OFF
+
+// RUN: %clang -S -emit-llvm -ffast-math -fno-fast-math \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FPC-ON
+
+float mymuladd(float x, float y, float z) {
+ // CHECK: define{{.*}} float @mymuladd
+ return x * y + z;
+ // expected-warning{{overriding '-ffp-contract=fast' option with '-ffp-contract=on'}}
+
+ // CHECK-DEFAULT: load float, float*
+ // CHECK-DEFAULT: fmul float
+ // CHECK-DEFAULT: load float, float*
+ // CHECK-DEFAULT: fadd float
+
+ // CHECK-ON: load float, float*
+ // CHECK-ON: load float, float*
+ // CHECK-ON: load float, float*
+ // CHECK-ON: call float @llvm.fmuladd.f32(float {{.*}}, float {{.*}}, float {{.*}})
+
+ // CHECK-CONTRACTFAST: load float, float*
+ // CHECK-CONTRACTFAST: load float, float*
+ // CHECK-CONTRACTFAST: fmul contract float
+ // CHECK-CONTRACTFAST: load float, float*
+ // CHECK-CONTRACTFAST: fadd contract float
+
+ // CHECK-CONTRACTOFF: load float, float*
+ // CHECK-CONTRACTOFF: load float, float*
+ // CHECK-CONTRACTOFF: fmul reassoc nnan ninf nsz arcp afn float
+ // CHECK-CONTRACTOFF: load float, float*
+ // CHECK-CONTRACTOFF: fadd reassoc nnan ninf nsz arcp afn float {{.*}}, {{.*}}
+
+ // CHECK-ONFAST: load float, float*
+ // CHECK-ONFAST: load float, float*
+ // CHECK-ONFAST: load float, float*
+ // CHECK-ONFAST: call reassoc nnan ninf nsz arcp afn float @llvm.fmuladd.f32(float {{.*}}, float {{.*}}, float {{.*}})
+
+ // CHECK-FASTFAST: load float, float*
+ // CHECK-FASTFAST: load float, float*
+ // CHECK-FASTFAST: fmul fast float
+ // CHECK-FASTFAST: load float, float*
+ // CHECK-FASTFAST: fadd fast float {{.*}}, {{.*}}
+
+ // CHECK-NOFAST: load float, float*
+ // CHECK-NOFAST: load float, float*
+ // CHECK-NOFAST: fmul float {{.*}}, {{.*}}
+ // CHECK-NOFAST: load float, float*
+ // CHECK-NOFAST: fadd float {{.*}}, {{.*}}
+
+ // CHECK-FPC-ON: load float, float*
+ // CHECK-FPC-ON: load float, float*
+ // CHECK-FPC-ON: load float, float*
+ // CHECK-FPC-ON: call float @llvm.fmuladd.f32(float {{.*}}, float {{.*}}, float {{.*}})
+
+ // CHECK-FPC-OFF: load float, float*
+ // CHECK-FPC-OFF: load float, float*
+ // CHECK-FPC-OFF: fmul float
+ // CHECK-FPC-OFF: load float, float*
+ // CHECK-FPC-OFF: fadd float {{.*}}, {{.*}}
+
+ // CHECK-FFPC-OFF: load float, float*
+ // CHECK-FFPC-OFF: load float, float*
+ // CHECK-FPSC-OFF: call float @llvm.experimental.constrained.fmul.f32(float {{.*}}, float {{.*}}, {{.*}})
+ // CHECK-FPSC-OFF: load float, float*
+ // CHECK-FPSC-OFF: [[RES:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, {{.*}})
+
}
diff --git a/clang/test/CodeGen/ffp-model.c b/clang/test/CodeGen/ffp-model.c
new file mode 100644
index 000000000000..21dbc8de99aa
--- /dev/null
+++ b/clang/test/CodeGen/ffp-model.c
@@ -0,0 +1,48 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang -S -emit-llvm -ffp-model=fast -emit-llvm %s -o - \
+// RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-FAST
+
+// RUN: %clang -S -emit-llvm -ffp-model=precise %s -o - \
+// RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-PRECISE
+
+// RUN: %clang -S -emit-llvm -ffp-model=strict %s -o - \
+// RUN: -target x86_64 | FileCheck %s --check-prefixes=CHECK,CHECK-STRICT
+
+// RUN: %clang -S -emit-llvm -ffp-model=strict -ffast-math \
+// RUN: -target x86_64 %s -o - | FileCheck %s \
+// RUN: --check-prefixes CHECK,CHECK-STRICT-FAST
+
+// RUN: %clang -S -emit-llvm -ffp-model=precise -ffast-math \
+// RUN: %s -o - | FileCheck %s --check-prefixes CHECK,CHECK-FAST1
+
+float mymuladd(float x, float y, float z) {
+ // CHECK: define{{.*}} float @mymuladd
+ return x * y + z;
+
+ // CHECK-FAST: fmul fast float
+ // CHECK-FAST: load float, float*
+ // CHECK-FAST: fadd fast float
+
+ // CHECK-PRECISE: load float, float*
+ // CHECK-PRECISE: load float, float*
+ // CHECK-PRECISE: load float, float*
+ // CHECK-PRECISE: call float @llvm.fmuladd.f32(float {{.*}}, float {{.*}}, float {{.*}})
+
+ // CHECK-STRICT: load float, float*
+ // CHECK-STRICT: load float, float*
+ // CHECK-STRICT: call float @llvm.experimental.constrained.fmul.f32(float {{.*}}, float {{.*}}, {{.*}})
+ // CHECK-STRICT: load float, float*
+ // CHECK-STRICT: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, {{.*}})
+
+ // CHECK-STRICT-FAST: load float, float*
+ // CHECK-STRICT-FAST: load float, float*
+ // CHECK-STRICT-FAST: call fast float @llvm.experimental.constrained.fmul.f32(float {{.*}}, float {{.*}}, {{.*}})
+ // CHECK-STRICT-FAST: load float, float*
+ // CHECK-STRICT-FAST: call fast float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, {{.*}}
+
+ // CHECK-FAST1: load float, float*
+ // CHECK-FAST1: load float, float*
+ // CHECK-FAST1: fmul fast float {{.*}}, {{.*}}
+ // CHECK-FAST1: load float, float* {{.*}}
+ // CHECK-FAST1: fadd fast float {{.*}}, {{.*}}
+}
diff --git a/clang/test/CodeGen/ppc-emmintrin.c b/clang/test/CodeGen/ppc-emmintrin.c
index fa3801f50a01..4a246ff92d76 100644
--- a/clang/test/CodeGen/ppc-emmintrin.c
+++ b/clang/test/CodeGen/ppc-emmintrin.c
@@ -2,9 +2,9 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE
// CHECK-BE-DAG: @_mm_movemask_pd.perm_mask = internal constant <4 x i32> <i32 -2139062144, i32 -2139062144, i32 -2139062144, i32 -2139078656>, align 16
// CHECK-BE-DAG: @_mm_shuffle_epi32.permute_selectors = internal constant [4 x i32] [i32 66051, i32 67438087, i32 134810123, i32 202182159], align 4
diff --git a/clang/test/CodeGen/ppc-xmmintrin.c b/clang/test/CodeGen/ppc-xmmintrin.c
index d3f18bfbb1e5..4aff7a7c3dda 100644
--- a/clang/test/CodeGen/ppc-xmmintrin.c
+++ b/clang/test/CodeGen/ppc-xmmintrin.c
@@ -2,11 +2,11 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
// RUN: %clang -x c++ -fsyntax-only -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns
// RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
-// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE
// RUN: %clang -x c++ -fsyntax-only -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns
diff --git a/clang/test/Driver/fp-model.c b/clang/test/Driver/fp-model.c
index 5fa9d110dd83..0824b3e2c596 100644
--- a/clang/test/Driver/fp-model.c
+++ b/clang/test/Driver/fp-model.c
@@ -99,7 +99,7 @@
// RUN: %clang -### -nostdinc -ffp-model=precise -c %s 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-FPM-PRECISE %s
// CHECK-FPM-PRECISE: "-cc1"
-// CHECK-FPM-PRECISE: "-ffp-contract=fast"
+// CHECK-FPM-PRECISE: "-ffp-contract=on"
// CHECK-FPM-PRECISE: "-fno-rounding-math"
// RUN: %clang -### -nostdinc -ffp-model=strict -c %s 2>&1 \
diff --git a/clang/test/Misc/ffp-contract.c b/clang/test/Misc/ffp-contract.c
new file mode 100644
index 000000000000..0d26905d4ef2
--- /dev/null
+++ b/clang/test/Misc/ffp-contract.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -O3 -ffp-contract=fast -triple=aarch64-apple-darwin \
+// RUN: -S -o - %s | FileCheck --check-prefix=CHECK-FMADD %s
+// REQUIRES: aarch64-registered-target
+
+float fma_test1(float a, float b, float c) {
+ // CHECK-FMADD: fmadd
+ float x = a * b;
+ float y = x + c;
+ return y;
+}
</cut>
3 years, 7 months
- 1
- 0
[ACTIVITY] week ending Nov. 14 2021
by Alex Bennée
VirtIO Initiative ([STR-9])
===========================
- project admin
[STR-9] <https://linaro.atlassian.net/browse/STR-9>
[upstream rust-vmm sync meeting]
<https://etherpad.opendev.org/p/rust-vmm-sync-2021&sa=D&source=calendar&ust=…>
[proposal] <https://github.com/rust-vmm/vhost-device/pull/57>
vhost-device maintainer effort ([UM-196])
- did a bunch of review on [vhost-device crate]
[UM-196] <https://linaro.atlassian.net/browse/UM-196>
[vhost-device crate] <https://github.com/rust-vmm/vhost-device>
QEMU Upstream Work ([UM-2])
===========================
[UM-2] <https://linaro.atlassian.net/browse/UM-2>
Upstream MTTCG tests ([QEMU-52])
- posted [kvm-unit-tests PATCH v3 0/3] GIC ITS tests Message-Id:
<20211112114734.3058678-1-alex.bennee(a)linaro.org>
- might as well flush the tree state as I left it
- posted [RFC PATCH] hw/intc: clean-up error reporting for failed
ITS cmd Message-Id:
<20211112170454.3158925-1-alex.bennee(a)linaro.org>
- re-based [mttcg tests to current state and fixed up]
[QEMU-52] <https://linaro.atlassian.net/browse/QEMU-52>
[mttcg tests to current state and fixed up]
<https://github.com/stsquad/qemu/tree/mttcg/current-tests-v8>
Completed Reviews [2/2]
=======================
[PATCH v2 0/3] Some watchpoint-related patches
Message-Id: <163662450348.125458.5494710452733592356.stgit@pasha-ThinkPad-X280>
[PATCH 0/5] Update linux-headers + NOIRQ support for KVM gdbstub
Message-Id: <20211111110604.207376-1-pbonzini(a)redhat.com>
Absences
========
- none
Current Review Queue
====================
TODO [PATCH] cpu-models-x86.rst: Tidy up a couple of things
Message-Id: <20211015100718.17828-1-pbonzini(a)redhat.com>
===================================================================================================================
TODO [PATCH 00/16] fdt: Make OF_BOARD a boolean option
Message-Id: <20211013010120.96851-1-sjg(a)chromium.org>
===========================================================================================================
TODO [PATCH v4 00/41] linux-user: Streamline handling of SIGSEGV
Message-Id: <20211006172307.780893-1-richard.henderson(a)linaro.org>
==================================================================================================================================
TODO [PATCH] softmmu: fix watchpoint processing in icount mode
Message-Id: <163101424137.678744.18360776310711795413.stgit@pasha-ThinkPad-X280>
==============================================================================================================================================
--
Alex Bennée
3 years, 7 months
- 1
- 0
[ACTIVITY] report week ending 11 Nov
by Peter Maydell
Progress (short week, 3 days)
* UM-2 [QEMU upstream maintainership]
- recent changes to QEMU's PSCI emulation broke booting of guest code
at EL3 on the imx7 board, which was previously accidentally
relying on PSCI-emulation-via-SMC not getting in its way despite
being enabled. We need to make this board disable PSCI when the
guest code is booting to EL3, as the virt board does, but it's
trickier here because the CPU-creation code is hidden inside a
model of an SoC object. After some on-list discussion I have a
plan for how to restructure this, and need to write some code...
* QEMU-420 [GICv4 emulation]
- re-read the GIC architecture specification, acquired a better
understanding of the required work, and broke this epic down into
stories
- discussed with Leif how the ITS support should be landed in the
sbsa-ref board
Misc:
* higher-than-usual amount of meetings and meeting-prep this week
-- PMM
3 years, 7 months
- 1
- 0
[TCWG CI] 456.hmmer slowed down by 3% after llvm: [flang] Fix crash in semantic error recovery situation
by ci_notify＠linaro.org
After llvm commit f411c1dd95092139c8b992260705ac0b75c8583f
Author: Peter Klausler <pklausler(a)nvidia.com>
[flang] Fix crash in semantic error recovery situation
the following benchmarks slowed down by more than 2%:
- 456.hmmer slowed down by 3% from 7600 to 7806 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O2 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-f411c1dd95092139c8b992260705ac0b75c8583f
cd investigate-llvm-f411c1dd95092139c8b992260705ac0b75c8583f
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach f411c1dd95092139c8b992260705ac0b75c8583f
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach c0b298fc213c1b33e97ca72fba58597365375875
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit f411c1dd95092139c8b992260705ac0b75c8583f
Author: Peter Klausler <pklausler(a)nvidia.com>
Date: Tue Nov 2 16:41:15 2021 -0700
[flang] Fix crash in semantic error recovery situation
A CHECK() in semantics is triggering when analyzing a program
with an undefined derived type pointer because the CHECK is
expecting a new error message to have been issued in a function
but not allowing for the case that a diagnostic could have been
produced earlier. Adjust the predicate.
Differential Revision: https://reviews.llvm.org/D113307
---
flang/lib/Semantics/expression.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/flang/lib/Semantics/expression.cpp b/flang/lib/Semantics/expression.cpp
index 331b9b2cf5bc..8ee8c9a9c9ce 100644
--- a/flang/lib/Semantics/expression.cpp
+++ b/flang/lib/Semantics/expression.cpp
@@ -1916,7 +1916,7 @@ auto ExpressionAnalyzer::AnalyzeProcedureComponentRef(
"Base of procedure component reference is not a derived-type object"_err_en_US);
}
}
- CHECK(!GetContextualMessages().empty());
+ CHECK(context_.AnyFatalError());
return std::nullopt;
}
</cut>
3 years, 7 months
- 1
- 0
ARM Cortex A55 support
by Stefan Johansson A
Hello,
We have been using Linaro GCC 7.5-2019.12 for the A53.
As we move on to new tech there seems to be no support for "-
mcpu=cortex-a55".
Today, we use the aarch64-elf- toolchain.
What GCC do you suggest we start using for A55 ?
Thanks,
Stefan
3 years, 7 months
- 2
- 1
[TCWG CI] 473.astar:[.] wayobj::makebound2 grew in size by 14% after llvm: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default
by ci_notify＠linaro.org
After llvm commit 7584ef766a7219b6ee5a400637206d26e0fa98ac
Author: Juneyoung Lee <aqjune(a)gmail.com>
[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default
the following hot functions grew in size by more than 10% (but their benchmarks grew in size by less than 1%):
- 473.astar:[.] wayobj::makebound2 grew in size by 14% from 404 to 462 bytes
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: arm-linux-gnueabihf
- Compiler flags: -Oz -mthumb
- Hardware: APM Mustang 8x X-Gene1
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-7584ef766a7219b6ee5a400637206d26e0fa98ac
cd investigate-llvm-7584ef766a7219b6ee5a400637206d26e0fa98ac
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 7584ef766a7219b6ee5a400637206d26e0fa98ac
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 1ab9a2906e19cca87cafac25cc31231a36de4843
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 7584ef766a7219b6ee5a400637206d26e0fa98ac
Author: Juneyoung Lee <aqjune(a)gmail.com>
Date: Sat Nov 6 15:34:49 2021 +0900
[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default
Turning on `enable_noundef_analysis` flag allows better codegen by removing freeze instructions.
I modified clang by renaming `enable_noundef_analysis` flag to `disable-noundef-analysis` and turning it off by default.
Test updates are made as a separate patch: D108453
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D105169
---
clang/include/clang/Basic/CodeGenOptions.def | 2 +-
clang/include/clang/Driver/Options.td | 6 +-
clang/lib/CodeGen/CGCall.cpp | 4 +-
clang/test/CXX/except/except.spec/p14-ir.cpp | 4 +-
.../expr.prim/expr.prim.lambda/blocks-irgen.mm | 4 +-
clang/test/CodeGen/2005-01-02-ConstantInits.c | 10 +-
clang/test/CodeGen/2006-05-19-SingleEltReturn.c | 2 +-
clang/test/CodeGen/2007-06-18-SextAttrAggregate.c | 2 +-
.../test/CodeGen/2009-02-13-zerosize-union-field.c | 2 +-
clang/test/CodeGen/2009-05-04-EnumInreg.c | 2 +-
clang/test/CodeGen/64bit-swiftcall.c | 8 +-
clang/test/CodeGen/RISCV/riscv-inline-asm.c | 2 +-
clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c | 8 +-
.../test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c | 8 +-
.../RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c | 48 +-
clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c | 24 +-
clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c | 6 +-
.../test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c | 16 +-
clang/test/CodeGen/RISCV/riscv64-lp64-abi.c | 6 +-
clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c | 4 +-
.../CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c | 58 +-
clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c | 12 +-
clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c | 16 +-
clang/test/CodeGen/SystemZ/systemz-abi-vector.c | 18 +-
clang/test/CodeGen/SystemZ/systemz-abi.c | 22 +-
clang/test/CodeGen/SystemZ/systemz-inline-asm.c | 24 +-
clang/test/CodeGen/WebAssembly/wasm-arguments.c | 38 +-
.../test/CodeGen/WebAssembly/wasm-main_argc_argv.c | 2 +-
clang/test/CodeGen/X86/avx-union.c | 6 +-
clang/test/CodeGen/X86/avx512fp16-complex-abi.c | 2 +-
clang/test/CodeGen/X86/ms-x86-intrinsics.c | 32 +-
clang/test/CodeGen/X86/strictfp_builtins.c | 8 +-
clang/test/CodeGen/X86/x86-atomic-long_double.c | 36 +-
.../CodeGen/X86/x86-inline-asm-min-vector-width.c | 12 +-
clang/test/CodeGen/X86/x86-long-double.cpp | 6 +-
clang/test/CodeGen/X86/x86-soft-float.c | 4 +-
clang/test/CodeGen/X86/x86-vec-i128.c | 22 +-
clang/test/CodeGen/X86/x86_32-arguments-darwin.c | 62 +-
clang/test/CodeGen/X86/x86_32-arguments-iamcu.c | 24 +-
clang/test/CodeGen/X86/x86_32-arguments-linux.c | 30 +-
clang/test/CodeGen/X86/x86_32-arguments-nommx.c | 4 +-
clang/test/CodeGen/X86/x86_32-arguments-realign.c | 2 +-
clang/test/CodeGen/X86/x86_32-arguments-win32.c | 12 +-
clang/test/CodeGen/X86/x86_64-arguments-nacl.c | 6 +-
clang/test/CodeGen/X86/x86_64-arguments-win32.c | 12 +-
clang/test/CodeGen/X86/x86_64-arguments.c | 82 +-
clang/test/CodeGen/X86/x86_64-longdouble.c | 36 +-
clang/test/CodeGen/aapcs-align.cpp | 56 +-
clang/test/CodeGen/aapcs64-align.cpp | 34 +-
clang/test/CodeGen/aarch64-args.cpp | 18 +-
clang/test/CodeGen/aarch64-byval-temp.c | 8 +-
clang/test/CodeGen/aarch64-neon-3v.c | 160 +-
clang/test/CodeGen/aarch64-neon-across.c | 88 +-
clang/test/CodeGen/aarch64-neon-dot-product.c | 24 +-
clang/test/CodeGen/aarch64-neon-extract.c | 48 +-
clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c | 42 +-
clang/test/CodeGen/aarch64-neon-fma.c | 44 +-
clang/test/CodeGen/aarch64-neon-ldst-one.c | 540 ++--
clang/test/CodeGen/aarch64-neon-scalar-copy.c | 48 +-
.../CodeGen/aarch64-neon-scalar-x-indexed-elem.c | 80 +-
clang/test/CodeGen/aarch64-neon-tbl.c | 144 +-
clang/test/CodeGen/aarch64-neon-vcombine.c | 28 +-
clang/test/CodeGen/aarch64-neon-vget-hilo.c | 56 +-
clang/test/CodeGen/aarch64-neon-vget.c | 96 +-
clang/test/CodeGen/aarch64-poly128.c | 62 +-
clang/test/CodeGen/aarch64-poly64.c | 96 +-
clang/test/CodeGen/aarch64-strictfp-builtins.c | 8 +-
...4-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c | 16 +-
...sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp | 8 +-
clang/test/CodeGen/aarch64-varargs.c | 2 +-
clang/test/CodeGen/address-space-field1.c | 2 +-
clang/test/CodeGen/address-space.c | 2 +-
clang/test/CodeGen/aix-alignment.c | 8 +-
clang/test/CodeGen/aix-altivec.c | 10 +-
clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp | 12 +-
clang/test/CodeGen/aix-return.c | 16 +-
clang/test/CodeGen/aix-struct-arg.c | 44 +-
clang/test/CodeGen/aix-vaargs.c | 4 +-
clang/test/CodeGen/alias.c | 12 +-
clang/test/CodeGen/align_value.cpp | 63 +-
clang/test/CodeGen/alloc-align-attr.c | 46 +-
clang/test/CodeGen/alloc-fns-alignment.c | 2 +-
clang/test/CodeGen/alloc-size-fnptr.c | 12 +-
clang/test/CodeGen/arc/arguments.c | 26 +-
clang/test/CodeGen/arithmetic-fence-builtin.c | 10 +-
clang/test/CodeGen/arm-aapcs-vfp.c | 24 +-
clang/test/CodeGen/arm-abi-vector.c | 48 +-
clang/test/CodeGen/arm-arguments.c | 10 +-
clang/test/CodeGen/arm-bf16-params-returns.c | 10 +-
clang/test/CodeGen/arm-byval-align.c | 2 +-
clang/test/CodeGen/arm-cmse-attr.c | 4 +-
clang/test/CodeGen/arm-cmse-call.c | 4 +-
clang/test/CodeGen/arm-float-helpers.c | 76 +-
clang/test/CodeGen/arm-fp16-arguments.c | 12 +-
clang/test/CodeGen/arm-homogenous.c | 2 +-
clang/test/CodeGen/arm-mangle-bf16.cpp | 2 +-
clang/test/CodeGen/arm-neon-directed-rounding.c | 30 +-
clang/test/CodeGen/arm-neon-dot-product.c | 16 +-
clang/test/CodeGen/arm-neon-fma.c | 8 +-
clang/test/CodeGen/arm-neon-numeric-maxmin.c | 8 +-
clang/test/CodeGen/arm-neon-vcvtX.c | 32 +-
clang/test/CodeGen/arm-swiftcall.c | 6 +-
clang/test/CodeGen/arm-varargs.c | 2 +-
clang/test/CodeGen/arm-vector-arguments.c | 10 +-
clang/test/CodeGen/arm-vfp16-arguments.c | 12 +-
clang/test/CodeGen/arm64-aapcs-arguments.c | 12 +-
clang/test/CodeGen/arm64-abi-vector.c | 42 +-
clang/test/CodeGen/arm64-arguments.c | 96 +-
clang/test/CodeGen/arm64-microsoft-arguments.cpp | 6 +-
clang/test/CodeGen/arm64_32.c | 2 +-
clang/test/CodeGen/arm64_vcopy.c | 20 +-
clang/test/CodeGen/arm64_vdupq_n_f64.c | 12 +-
clang/test/CodeGen/armv7k-abi.c | 6 +-
clang/test/CodeGen/asm-label.c | 12 +-
.../assume-aligned-and-alloc-align-attributes.c | 12 +-
clang/test/CodeGen/atomic-arm64.c | 2 +-
clang/test/CodeGen/atomic-ops-libcall.c | 34 +-
clang/test/CodeGen/atomic-ops.c | 44 +-
clang/test/CodeGen/atomic_ops.c | 10 +-
clang/test/CodeGen/atomics-inlining.c | 52 +-
clang/test/CodeGen/attr-func-def.c | 4 +-
clang/test/CodeGen/attr-naked.c | 2 +-
clang/test/CodeGen/attr-no-tail.c | 8 +-
clang/test/CodeGen/attr-nomerge.cpp | 20 +-
clang/test/CodeGen/attr-noundef.cpp | 4 +-
clang/test/CodeGen/attr-target-mv-func-ptrs.c | 4 +-
clang/test/CodeGen/attr-target-mv-va-args.c | 24 +-
clang/test/CodeGen/attr-target-mv.c | 28 +-
clang/test/CodeGen/attr-x86-interrupt.c | 16 +-
clang/test/CodeGen/attributes.c | 2 +-
clang/test/CodeGen/available-externally-hidden.cpp | 2 +-
clang/test/CodeGen/available-externally-suppress.c | 2 +-
clang/test/CodeGen/avr/struct.c | 4 +-
clang/test/CodeGen/big-atomic-ops.c | 30 +-
clang/test/CodeGen/bittest-intrin.c | 8 +-
clang/test/CodeGen/blocks.c | 6 +-
clang/test/CodeGen/bool-convert.c | 2 +-
clang/test/CodeGen/builtin-align-array.c | 8 +-
clang/test/CodeGen/builtin-align.c | 24 +-
clang/test/CodeGen/builtin-assume-aligned.c | 31 +-
clang/test/CodeGen/builtin-attributes.c | 20 +-
clang/test/CodeGen/builtin-memfns.c | 4 +-
clang/test/CodeGen/builtin-sqrt.c | 2 +-
clang/test/CodeGen/builtins-arm.c | 24 +-
clang/test/CodeGen/builtins-memcpy-inline.c | 8 +-
clang/test/CodeGen/builtins-ms.c | 4 +-
clang/test/CodeGen/builtins-multiprecision.c | 4 +-
clang/test/CodeGen/builtins-overflow.c | 12 +-
clang/test/CodeGen/builtins-ppc-xlcompat-macros.c | 4 +-
clang/test/CodeGen/builtins.c | 44 +-
clang/test/CodeGen/c-strings.c | 2 +-
clang/test/CodeGen/c11atomics-ios.c | 8 +-
clang/test/CodeGen/c11atomics.c | 52 +-
clang/test/CodeGen/calling-conv-ignored.c | 32 +-
...-assumption-attribute-align_value-on-lvalue.cpp | 2 +-
...ssumption-attribute-align_value-on-paramvar.cpp | 4 +-
...-attribute-alloc_align-on-function-variable.cpp | 6 +-
...ssumption-attribute-alloc_align-on-function.cpp | 8 +-
...ibute-assume_aligned-on-function-two-params.cpp | 6 +-
...mption-attribute-assume_aligned-on-function.cpp | 8 +-
...uiltin_assume_aligned-three-params-variable.cpp | 2 +-
...umption-builtin_assume_aligned-three-params.cpp | 2 +-
...ssumption-builtin_assume_aligned-two-params.cpp | 2 +-
.../CodeGen/catch-alignment-assumption-openmp.cpp | 2 +-
.../CodeGen/catch-implicit-integer-sign-changes.c | 18 +-
...icit-signed-integer-truncation-or-sign-change.c | 10 +-
...tr-and-nonzero-offset-when-nullptr-is-defined.c | 2 +-
.../CodeGen/catch-nullptr-and-nonzero-offset.c | 14 +-
.../test/CodeGen/catch-pointer-overflow-volatile.c | 2 +-
clang/test/CodeGen/catch-pointer-overflow.c | 16 +-
clang/test/CodeGen/cfi-check-fail.c | 2 +-
clang/test/CodeGen/cfi-check-fail2.c | 2 +-
clang/test/CodeGen/cmse-clear-arg.c | 2 +-
clang/test/CodeGen/complex-builtins.c | 228 +-
clang/test/CodeGen/complex-indirect.c | 2 +-
clang/test/CodeGen/complex-libcalls.c | 228 +-
clang/test/CodeGen/complex-math.c | 12 +-
clang/test/CodeGen/complex-strictfp.c | 42 +-
clang/test/CodeGen/constructor-attribute.c | 2 +-
clang/test/CodeGen/debug-info-block-vars.c | 2 +-
clang/test/CodeGen/debug-info-pseudo-probe.cpp | 4 +-
clang/test/CodeGen/decl.c | 2 +-
clang/test/CodeGen/default-address-space.c | 4 +-
clang/test/CodeGen/exceptions-seh-finally.c | 14 +-
clang/test/CodeGen/exceptions-seh-leave.c | 30 +-
clang/test/CodeGen/exceptions-seh-nested-finally.c | 4 +-
clang/test/CodeGen/exceptions-seh.c | 26 +-
clang/test/CodeGen/exceptions.c | 2 +-
clang/test/CodeGen/ext-int-cc.c | 58 +-
clang/test/CodeGen/extend-arg-64.c | 2 +-
clang/test/CodeGen/fp-function-attrs.cpp | 6 +-
clang/test/CodeGen/fp-options-to-fast-math-flags.c | 18 +-
clang/test/CodeGen/fpconstrained-cmp-double.c | 24 +-
clang/test/CodeGen/fpconstrained-cmp-float.c | 24 +-
clang/test/CodeGen/function-attributes.c | 20 +-
clang/test/CodeGen/functions.c | 4 +-
clang/test/CodeGen/hexagon-hvx-abi.c | 8 +-
clang/test/CodeGen/incomplete-function-type-2.c | 2 +-
clang/test/CodeGen/indirect-noundef.cpp | 2 +-
clang/test/CodeGen/inline.c | 4 +-
clang/test/CodeGen/lanai-arguments.c | 12 +-
clang/test/CodeGen/lanai-regparm.c | 12 +-
clang/test/CodeGen/libcall-declarations.c | 636 ++--
clang/test/CodeGen/libcalls.c | 54 +-
clang/test/CodeGen/long_double_fp128.cpp | 14 +-
clang/test/CodeGen/malign-double-x86-nacl.c | 6 +-
clang/test/CodeGen/mangle-blocks.c | 6 +-
clang/test/CodeGen/mangle-windows.c | 2 +-
clang/test/CodeGen/math-builtins-long.c | 386 +--
clang/test/CodeGen/math-builtins.c | 648 ++--
clang/test/CodeGen/math-libcalls.c | 474 +--
clang/test/CodeGen/matrix-cast.c | 26 +-
clang/test/CodeGen/matrix-type-builtins.c | 4 +-
.../test/CodeGen/matrix-type-operators-fast-math.c | 12 +-
clang/test/CodeGen/matrix-type-operators.c | 84 +-
clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | 2 +-
clang/test/CodeGen/memcpy-inline-builtin.c | 2 +-
clang/test/CodeGen/microsoft-call-conv-x64.c | 2 +-
clang/test/CodeGen/microsoft-call-conv.c | 2 +-
clang/test/CodeGen/mingw-long-double.c | 12 +-
clang/test/CodeGen/mips-unsigned-ext-var.c | 6 +-
clang/test/CodeGen/mips-unsigned-extend.c | 6 +-
clang/test/CodeGen/mips-vector-arg.c | 16 +-
clang/test/CodeGen/mips-zero-sized-struct.c | 6 +-
clang/test/CodeGen/mips64-padding-arg.c | 24 +-
clang/test/CodeGen/mrtd.c | 6 +-
clang/test/CodeGen/ms-inline-asm.c | 2 +-
clang/test/CodeGen/ms-intrinsics-cpuid.c | 4 +-
clang/test/CodeGen/ms-intrinsics-other.c | 2 +-
clang/test/CodeGen/ms-mixed-ptr-sizes.c | 20 +-
clang/test/CodeGen/ms_abi.c | 4 +-
clang/test/CodeGen/ms_abi_aarch64.c | 4 +-
clang/test/CodeGen/named_reg_global.c | 2 +-
clang/test/CodeGen/no-bitfield-type-align.c | 2 +-
clang/test/CodeGen/no-builtin.cpp | 12 +-
clang/test/CodeGen/no-prototype.c | 2 +-
clang/test/CodeGen/noduplicate-cxx11-test.cpp | 2 +-
.../CodeGen/non-power-of-2-alignment-assumptions.c | 10 +-
clang/test/CodeGen/nonnull.c | 28 +-
clang/test/CodeGen/nrvo-tracking.cpp | 2 +-
clang/test/CodeGen/nvptx-abi.c | 10 +-
clang/test/CodeGen/object-size.c | 4 +-
clang/test/CodeGen/padding-init.c | 6 +-
clang/test/CodeGen/pass-by-value-noalias.c | 4 +-
clang/test/CodeGen/pass-object-size.c | 114 +-
clang/test/CodeGen/pch-dllexport.cpp | 4 +-
clang/test/CodeGen/powerpc-c99complex.c | 14 +-
clang/test/CodeGen/ppc-emmintrin.c | 750 ++---
clang/test/CodeGen/ppc-mm-malloc-le.c | 8 +-
clang/test/CodeGen/ppc-mm-malloc.c | 8 +-
clang/test/CodeGen/ppc-mmintrin.c | 124 +-
clang/test/CodeGen/ppc-pmmintrin.c | 177 +-
clang/test/CodeGen/ppc-signbit.c | 2 +-
clang/test/CodeGen/ppc-smmintrin.c | 32 +-
clang/test/CodeGen/ppc-tmmintrin.c | 290 +-
clang/test/CodeGen/ppc-xmmintrin.c | 400 +--
clang/test/CodeGen/ppc64-align-struct.c | 26 +-
clang/test/CodeGen/ppc64-complex-parms.c | 38 +-
clang/test/CodeGen/ppc64-complex-return.c | 20 +-
clang/test/CodeGen/ppc64-extend.c | 4 +-
clang/test/CodeGen/ppc64-inline-asm.c | 14 +-
clang/test/CodeGen/ppc64-long-double.cpp | 6 +-
clang/test/CodeGen/ppc64-soft-float.c | 6 +-
clang/test/CodeGen/ppc64-vector.c | 10 +-
clang/test/CodeGen/ppc64le-aggregates.c | 8 +-
clang/test/CodeGen/ppc64le-f128Aggregates.c | 4 +-
clang/test/CodeGen/ppc64le-varargs-f128.c | 12 +-
clang/test/CodeGen/pr25786.c | 4 +-
clang/test/CodeGen/pr5406.c | 2 +-
clang/test/CodeGen/pr9614.c | 4 +-
clang/test/CodeGen/pragma-weak.c | 2 +-
clang/test/CodeGen/ps4-dllimport-dllexport.c | 2 +-
clang/test/CodeGen/regcall.c | 100 +-
clang/test/CodeGen/regparm-flag.c | 12 +-
clang/test/CodeGen/regparm-struct.c | 36 +-
clang/test/CodeGen/regparm.c | 6 +-
clang/test/CodeGen/renderscript.c | 14 +-
clang/test/CodeGen/restrict.c | 10 +-
.../sanitize-thread-no-checking-at-run-time.m | 2 +-
clang/test/CodeGen/sparc-arguments.c | 4 +-
clang/test/CodeGen/sparcv8-abi.c | 6 +-
clang/test/CodeGen/sparcv8-inline-asm.c | 2 +-
clang/test/CodeGen/sparcv9-abi.c | 16 +-
clang/test/CodeGen/spir-half-type.cpp | 2 +-
clang/test/CodeGen/stack-protector.c | 4 +-
clang/test/CodeGen/stdcall-fastcall.c | 24 +-
clang/test/CodeGen/strictfp_builtins.c | 26 +-
clang/test/CodeGen/swift-async-call-conv.c | 22 +-
clang/test/CodeGen/switch-dce.c | 4 +-
clang/test/CodeGen/sysv_abi.c | 8 +-
clang/test/CodeGen/temporary-lifetime.cpp | 4 +-
clang/test/CodeGen/transparent-union-redecl.c | 8 +-
clang/test/CodeGen/transparent-union.c | 8 +-
clang/test/CodeGen/ubsan-function.cpp | 2 +-
.../CodeGen/unique-internal-linkage-names-dwarf.c | 4 +-
.../unique-internal-linkage-names-dwarf.cpp | 12 +-
.../test/CodeGen/unique-internal-linkage-names.cpp | 16 +-
clang/test/CodeGen/variadic-null-win64.c | 12 +-
clang/test/CodeGen/ve-abi.c | 34 +-
clang/test/CodeGen/vectorcall.c | 86 +-
clang/test/CodeGen/vla.c | 22 +-
clang/test/CodeGen/win64-i128.c | 4 +-
clang/test/CodeGen/windows-itanium.c | 2 +-
.../CodeGen/windows-on-arm-dllimport-dllexport.c | 2 +-
.../CodeGen/windows-seh-EHa-CppCatchDotDotDot.cpp | 2 +-
.../test/CodeGen/windows-seh-EHa-CppCondiTemps.cpp | 18 +-
clang/test/CodeGen/windows-seh-EHa-CppDtors01.cpp | 2 +-
.../test/CodeGen/windows-seh-EHa-TryInFinally.cpp | 4 +-
clang/test/CodeGen/windows-seh-abnormal-exits.c | 2 +-
clang/test/CodeGen/windows-swiftcall.c | 22 +-
clang/test/CodeGen/x86_32-align-linux.c | 6 +-
clang/test/CodeGen/xcore-abi.c | 14 +-
clang/test/CodeGen/xray-log-args.cpp | 4 +-
clang/test/CodeGenCUDA/address-spaces.cu | 2 +-
.../CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu | 10 +-
clang/test/CodeGenCUDA/builtins-amdgcn.cu | 2 +-
clang/test/CodeGenCUDA/cuda-builtin-vars.cu | 2 +-
clang/test/CodeGenCUDA/kernel-args-alignment.cu | 2 +-
clang/test/CodeGenCUDA/kernel-args.cu | 8 +-
clang/test/CodeGenCUDA/kernel-stub-name.cu | 4 +-
clang/test/CodeGenCUDA/lambda.cu | 8 +-
clang/test/CodeGenCUDA/redux-builtins.cu | 2 +-
clang/test/CodeGenCUDA/surface.cu | 4 +-
clang/test/CodeGenCUDA/texture.cu | 6 +-
clang/test/CodeGenCUDA/unnamed-types.cu | 8 +-
clang/test/CodeGenCUDA/usual-deallocators.cu | 36 +-
clang/test/CodeGenCUDA/vtbl.cu | 2 +-
.../CodeGenCXX/2009-05-04-PureConstNounwind.cpp | 10 +-
.../test/CodeGenCXX/2011-12-19-init-list-ctor.cpp | 6 +-
.../diamond-virtual-inheritance.cpp | 2 +-
.../CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp | 8 +-
.../RelativeVTablesABI/member-function-pointer.cpp | 2 +-
.../RelativeVTablesABI/multiple-inheritance.cpp | 2 +-
.../parent-and-child-in-comdats.cpp | 2 +-
.../CodeGenCXX/RelativeVTablesABI/type-info.cpp | 2 +-
.../CodeGenCXX/RelativeVTablesABI/vbase-offset.cpp | 2 +-
.../RelativeVTablesABI/virtual-function-call.cpp | 2 +-
clang/test/CodeGenCXX/address-space-cast.cpp | 14 +-
clang/test/CodeGenCXX/address-space-ref.cpp | 8 +-
clang/test/CodeGenCXX/aix-alignment.cpp | 6 +-
.../aix-static-init-temp-spec-and-inline-var.cpp | 14 +-
clang/test/CodeGenCXX/aix-static-init.cpp | 4 +-
.../test/CodeGenCXX/align-avx-complete-objects.cpp | 4 +-
clang/test/CodeGenCXX/alignment.cpp | 20 +-
clang/test/CodeGenCXX/alloc-size.cpp | 16 +-
.../test/CodeGenCXX/amdgcn-automatic-variable.cpp | 10 +-
clang/test/CodeGenCXX/amdgcn-func-arg.cpp | 24 +-
clang/test/CodeGenCXX/amdgcn_declspec_get.cpp | 2 +-
clang/test/CodeGenCXX/anonymous-namespaces.cpp | 4 +-
.../test/CodeGenCXX/apple-kext-indirect-call-2.cpp | 8 +-
clang/test/CodeGenCXX/apple-kext-linkage.cpp | 4 +-
clang/test/CodeGenCXX/arm-cc.cpp | 4 +-
clang/test/CodeGenCXX/arm-swiftcall.cpp | 2 +-
clang/test/CodeGenCXX/arm.cpp | 4 +-
clang/test/CodeGenCXX/arm64-constructor-return.cpp | 4 +-
clang/test/CodeGenCXX/arm64-darwinpcs.cpp | 4 +-
clang/test/CodeGenCXX/atomic-dllexport.cpp | 4 +-
clang/test/CodeGenCXX/atomic-inline.cpp | 2 +-
clang/test/CodeGenCXX/atomicinit.cpp | 8 +-
.../CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp | 28 +-
clang/test/CodeGenCXX/attr-disable-tail-calls.cpp | 12 +-
clang/test/CodeGenCXX/attr-musttail.cpp | 40 +-
clang/test/CodeGenCXX/attr-notail.cpp | 10 +-
clang/test/CodeGenCXX/attr-target-mv-diff-ns.cpp | 42 +-
clang/test/CodeGenCXX/attr-target-mv-func-ptrs.cpp | 6 +-
clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp | 16 +-
.../CodeGenCXX/attr-target-mv-member-funcs.cpp | 96 +-
.../CodeGenCXX/attr-target-mv-out-of-line-defs.cpp | 22 +-
clang/test/CodeGenCXX/attr-target-mv-overloads.cpp | 36 +-
...used-member-function-implicit-instantiation.cpp | 2 +-
clang/test/CodeGenCXX/attr-x86-interrupt.cpp | 24 +-
clang/test/CodeGenCXX/blocks-cxx11.cpp | 16 +-
clang/test/CodeGenCXX/blocks.cpp | 4 +-
clang/test/CodeGenCXX/builtin-calling-conv.cpp | 18 +-
.../CodeGenCXX/builtin-is-constant-evaluated.cpp | 8 +-
.../CodeGenCXX/builtin-operator-new-delete.cpp | 20 +-
clang/test/CodeGenCXX/builtin-source-location.cpp | 20 +-
clang/test/CodeGenCXX/builtin_FUNCTION.cpp | 6 +-
clang/test/CodeGenCXX/builtin_LINE.cpp | 24 +-
clang/test/CodeGenCXX/builtins.cpp | 4 +-
clang/test/CodeGenCXX/call-with-static-chain.cpp | 16 +-
clang/test/CodeGenCXX/catch-undef-behavior.cpp | 10 +-
clang/test/CodeGenCXX/cfi-cast.cpp | 4 +-
clang/test/CodeGenCXX/cfi-multiple-inheritance.cpp | 2 +-
.../test/CodeGenCXX/cfi-vcall-check-after-args.cpp | 2 +-
clang/test/CodeGenCXX/clang-sections.cpp | 2 +-
clang/test/CodeGenCXX/compound-literals.cpp | 6 +-
clang/test/CodeGenCXX/condition.cpp | 30 +-
clang/test/CodeGenCXX/conditional-gnu-ext.cpp | 14 +-
clang/test/CodeGenCXX/conditional-temporaries.cpp | 44 +-
clang/test/CodeGenCXX/const-init-cxx11.cpp | 16 +-
.../constructor-destructor-return-this.cpp | 100 +-
clang/test/CodeGenCXX/constructor-direct-call.cpp | 14 +-
clang/test/CodeGenCXX/constructor-init.cpp | 10 +-
clang/test/CodeGenCXX/constructors.cpp | 24 +-
clang/test/CodeGenCXX/convert-to-fptr.cpp | 4 +-
clang/test/CodeGenCXX/copy-assign-synthesis-1.cpp | 2 +-
clang/test/CodeGenCXX/copy-constructor-elim-2.cpp | 2 +-
.../CodeGenCXX/copy-constructor-synthesis-2.cpp | 2 +-
.../test/CodeGenCXX/copy-constructor-synthesis.cpp | 6 +-
clang/test/CodeGenCXX/copy-elision.cpp | 2 +-
clang/test/CodeGenCXX/copy-initialization.cpp | 2 +-
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clang/test/CodeGenCXX/cxx11-thread-local.cpp | 38 +-
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clang/test/CodeGenCXX/cxx1y-variable-template.cpp | 2 +-
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clang/test/CodeGenCXX/dllexport-ctor-closure.cpp | 10 +-
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clang/test/CodeGenCXX/dllimport-members.cpp | 12 +-
clang/test/CodeGenCXX/dllimport-runtime-fns.cpp | 6 +-
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clang/test/CodeGenCXX/ext-int.cpp | 16 +-
clang/test/CodeGenCXX/fastcall.cpp | 2 +-
clang/test/CodeGenCXX/float128-declarations.cpp | 20 +-
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clang/test/CodeGenCXX/for-cond-var.cpp | 16 +-
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clang/test/CodeGenCXX/inalloca-overaligned.cpp | 38 +-
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clang/test/CodeGenCXX/inalloca-vector.cpp | 40 +-
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clang/test/CodeGenCXX/inline-functions.cpp | 2 +-
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clang/test/CodeGenCXX/microsoft-abi-methods.cpp | 10 +-
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clang/test/CodeGenCXX/microsoft-abi-vbase-dtor.cpp | 2 +-
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clang/test/CodeGenCXX/split-stacks.cpp | 12 +-
clang/test/CodeGenCXX/stack-reuse-miscompile.cpp | 8 +-
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clang/test/CodeGenCXX/static-destructor.cpp | 4 +-
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clang/test/CodeGenCXX/static-init-wasm.cpp | 4 +-
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clang/test/CodeGenCXX/stmtexpr.cpp | 16 +-
clang/test/CodeGenCXX/switch-case-folding-2.cpp | 2 +-
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clang/test/CodeGenCXX/trivial_abi.cpp | 46 +-
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clang/test/CodeGenCXX/variadic-templates.cpp | 2 +-
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.../CodeGenOpenCL/constant-addr-space-globals.cl | 2 +-
clang/test/CodeGenOpenCL/convergent.cl | 4 +-
clang/test/CodeGenOpenCL/fpmath.cl | 4 +-
clang/test/CodeGenOpenCL/half.cl | 8 +-
.../kernels-have-spir-cc-by-default.cl | 8 +-
clang/test/CodeGenOpenCL/no-half.cl | 4 +-
clang/test/CodeGenOpenCL/overload.cl | 20 +-
clang/test/CodeGenOpenCL/printf.cl | 12 +-
clang/test/CodeGenOpenCL/size_t.cl | 60 +-
clang/test/CodeGenOpenCL/spir-calling-conv.cl | 10 +-
.../CodeGenOpenCLCXX/address-space-deduction.clcpp | 2 +-
.../CodeGenOpenCLCXX/addrspace-derived-base.clcpp | 4 +-
.../CodeGenOpenCLCXX/addrspace-new-delete.clcpp | 2 +-
.../test/CodeGenOpenCLCXX/addrspace-of-this.clcpp | 32 +-
.../CodeGenOpenCLCXX/addrspace-operators.clcpp | 4 +-
.../CodeGenOpenCLCXX/addrspace-references.clcpp | 2 +-
.../CodeGenOpenCLCXX/addrspace-with-class.clcpp | 22 +-
.../CodeGenOpenCLCXX/template-address-spaces.clcpp | 6 +-
.../test/CodeGenSYCL/address-space-conversions.cpp | 52 +-
clang/test/CodeGenSYCL/address-space-mangling.cpp | 16 +-
clang/test/CodeGenSYCL/unique_stable_name.cpp | 40 +-
clang/test/Headers/ms-arm64-intrin.cpp | 6 +-
clang/test/Headers/stdarg.cpp | 28 +-
clang/test/Modules/codegen-extern-template.cpp | 2 +-
clang/test/Modules/codegen.test | 2 +-
clang/test/Modules/cxx-irgen.cpp | 2 +-
clang/test/Modules/initializers.cpp | 4 +-
clang/test/Modules/templates.mm | 8 +-
clang/test/OpenMP/allocate_codegen.cpp | 2 +-
clang/test/OpenMP/allocate_codegen_attr.cpp | 2 +-
clang/test/OpenMP/assumes_include_nvptx.cpp | 6 +-
clang/test/OpenMP/atomic_capture_codegen.cpp | 28 +-
clang/test/OpenMP/atomic_codegen.cpp | 8 +-
clang/test/OpenMP/atomic_read_codegen.c | 14 +-
clang/test/OpenMP/atomic_update_codegen.cpp | 28 +-
clang/test/OpenMP/atomic_write_codegen.c | 18 +-
clang/test/OpenMP/cancel_codegen.cpp | 104 +-
clang/test/OpenMP/cancellation_point_codegen.cpp | 28 +-
clang/test/OpenMP/debug-info-complex-byval.cpp | 49 +-
clang/test/OpenMP/debug-info-openmp-array.cpp | 6 +-
clang/test/OpenMP/declare_mapper_codegen.cpp | 20 +-
clang/test/OpenMP/declare_reduction_codegen.c | 48 +-
clang/test/OpenMP/declare_reduction_codegen.cpp | 46 +-
.../declare_reduction_codegen_in_templates.cpp | 2 +-
clang/test/OpenMP/declare_target_codegen.cpp | 4 +-
.../declare_target_codegen_globalization.cpp | 12 +-
clang/test/OpenMP/declare_target_link_codegen.cpp | 4 +-
clang/test/OpenMP/declare_variant_mixed_codegen.c | 12 +-
clang/test/OpenMP/distribute_codegen.cpp | 304 +-
.../OpenMP/distribute_firstprivate_codegen.cpp | 329 +-
.../test/OpenMP/distribute_lastprivate_codegen.cpp | 361 ++-
.../OpenMP/distribute_parallel_for_codegen.cpp | 576 ++--
...istribute_parallel_for_firstprivate_codegen.cpp | 385 ++-
.../OpenMP/distribute_parallel_for_if_codegen.cpp | 320 +-
...distribute_parallel_for_lastprivate_codegen.cpp | 449 ++-
...distribute_parallel_for_num_threads_codegen.cpp | 481 ++-
.../distribute_parallel_for_private_codegen.cpp | 425 ++-
.../distribute_parallel_for_proc_bind_codegen.cpp | 29 +-
...tribute_parallel_for_reduction_task_codegen.cpp | 44 +-
.../distribute_parallel_for_simd_codegen.cpp | 592 ++--
...bute_parallel_for_simd_firstprivate_codegen.cpp | 1362 ++++-----
.../distribute_parallel_for_simd_if_codegen.cpp | 3192 ++++++++++----------
...ibute_parallel_for_simd_lastprivate_codegen.cpp | 1336 ++++----
...ibute_parallel_for_simd_num_threads_codegen.cpp | 2640 ++++++++--------
...istribute_parallel_for_simd_private_codegen.cpp | 1288 ++++----
...tribute_parallel_for_simd_proc_bind_codegen.cpp | 236 +-
clang/test/OpenMP/distribute_private_codegen.cpp | 345 ++-
clang/test/OpenMP/distribute_simd_codegen.cpp | 512 ++--
.../distribute_simd_firstprivate_codegen.cpp | 944 +++---
.../OpenMP/distribute_simd_lastprivate_codegen.cpp | 1008 +++----
.../OpenMP/distribute_simd_private_codegen.cpp | 1056 +++----
.../OpenMP/distribute_simd_reduction_codegen.cpp | 272 +-
clang/test/OpenMP/for_codegen.cpp | 16 +-
clang/test/OpenMP/for_firstprivate_codegen.cpp | 313 +-
clang/test/OpenMP/for_lastprivate_codegen.cpp | 601 ++--
clang/test/OpenMP/for_linear_codegen.cpp | 165 +-
clang/test/OpenMP/for_private_codegen.cpp | 177 +-
clang/test/OpenMP/for_reduction_codegen.cpp | 760 ++---
clang/test/OpenMP/for_reduction_codegen_UDR.cpp | 936 +++---
clang/test/OpenMP/for_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/for_scan_codegen.cpp | 2 +-
clang/test/OpenMP/for_simd_codegen.cpp | 6 +-
clang/test/OpenMP/for_simd_scan_codegen.cpp | 2 +-
clang/test/OpenMP/function-attr.cpp | 8 +-
clang/test/OpenMP/irbuilder_for_iterator.cpp | 24 +-
clang/test/OpenMP/irbuilder_for_rangefor.cpp | 28 +-
clang/test/OpenMP/irbuilder_for_unsigned.c | 6 +-
...builder_unroll_partial_heuristic_constant_for.c | 2 +-
...builder_unroll_partial_heuristic_for_collapse.c | 380 ++-
...rbuilder_unroll_partial_heuristic_runtime_for.c | 2 +-
clang/test/OpenMP/master_taskloop_codegen.cpp | 10 +-
.../master_taskloop_firstprivate_codegen.cpp | 22 +-
.../master_taskloop_in_reduction_codegen.cpp | 12 +-
.../OpenMP/master_taskloop_lastprivate_codegen.cpp | 22 +-
.../OpenMP/master_taskloop_private_codegen.cpp | 22 +-
.../OpenMP/master_taskloop_reduction_codegen.cpp | 22 +-
clang/test/OpenMP/master_taskloop_simd_codegen.cpp | 8 +-
.../master_taskloop_simd_firstprivate_codegen.cpp | 22 +-
.../master_taskloop_simd_in_reduction_codegen.cpp | 12 +-
.../master_taskloop_simd_lastprivate_codegen.cpp | 22 +-
.../master_taskloop_simd_private_codegen.cpp | 22 +-
.../master_taskloop_simd_reduction_codegen.cpp | 22 +-
clang/test/OpenMP/nvptx_allocate_codegen.cpp | 8 +-
clang/test/OpenMP/nvptx_data_sharing.cpp | 8 +-
.../nvptx_declare_target_var_ctor_dtor_codegen.cpp | 28 +-
.../OpenMP/nvptx_declare_variant_name_mangling.cpp | 4 +-
...tx_distribute_parallel_generic_mode_codegen.cpp | 48 +-
clang/test/OpenMP/nvptx_lambda_capturing.cpp | 122 +-
.../OpenMP/nvptx_multi_target_parallel_codegen.cpp | 18 +-
.../test/OpenMP/nvptx_nested_parallel_codegen.cpp | 72 +-
clang/test/OpenMP/nvptx_parallel_codegen.cpp | 52 +-
clang/test/OpenMP/nvptx_parallel_for_codegen.cpp | 6 +-
clang/test/OpenMP/nvptx_target_codegen.cpp | 10 +-
.../OpenMP/nvptx_target_firstprivate_codegen.cpp | 8 +-
.../test/OpenMP/nvptx_target_parallel_codegen.cpp | 48 +-
.../nvptx_target_parallel_num_threads_codegen.cpp | 48 +-
.../nvptx_target_parallel_reduction_codegen.cpp | 18 +-
...get_parallel_reduction_codegen_tbaa_PR46146.cpp | 10 +-
clang/test/OpenMP/nvptx_target_printf_codegen.c | 4 +-
clang/test/OpenMP/nvptx_target_teams_codegen.cpp | 48 +-
.../nvptx_target_teams_distribute_codegen.cpp | 18 +-
...arget_teams_distribute_parallel_for_codegen.cpp | 144 +-
...istribute_parallel_for_generic_mode_codegen.cpp | 72 +-
..._teams_distribute_parallel_for_simd_codegen.cpp | 72 +-
.../nvptx_target_teams_distribute_simd_codegen.cpp | 22 +-
clang/test/OpenMP/nvptx_teams_codegen.cpp | 32 +-
.../test/OpenMP/nvptx_teams_reduction_codegen.cpp | 162 +-
.../test/OpenMP/nvptx_unsupported_type_codegen.cpp | 4 +-
clang/test/OpenMP/openmp_offload_codegen.cpp | 2 +-
clang/test/OpenMP/openmp_win_codegen.cpp | 7 +-
clang/test/OpenMP/ordered_codegen.cpp | 76 +-
clang/test/OpenMP/parallel_codegen.cpp | 100 +-
clang/test/OpenMP/parallel_copyin_codegen.cpp | 613 ++--
.../test/OpenMP/parallel_firstprivate_codegen.cpp | 44 +-
clang/test/OpenMP/parallel_for_codegen.cpp | 224 +-
.../parallel_for_lastprivate_conditional.cpp | 17 +-
clang/test/OpenMP/parallel_for_linear_codegen.cpp | 93 +-
.../OpenMP/parallel_for_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/parallel_for_scan_codegen.cpp | 2 +-
.../OpenMP/parallel_for_simd_aligned_codegen.cpp | 72 +-
clang/test/OpenMP/parallel_for_simd_codegen.cpp | 6 +-
.../test/OpenMP/parallel_for_simd_scan_codegen.cpp | 2 +-
clang/test/OpenMP/parallel_if_codegen.cpp | 100 +-
clang/test/OpenMP/parallel_if_codegen_PR51349.cpp | 2 +-
clang/test/OpenMP/parallel_master_codegen.cpp | 63 +-
.../parallel_master_reduction_task_codegen.cpp | 36 +-
.../OpenMP/parallel_master_taskloop_codegen.cpp | 60 +-
...rallel_master_taskloop_firstprivate_codegen.cpp | 20 +-
...arallel_master_taskloop_lastprivate_codegen.cpp | 282 +-
.../parallel_master_taskloop_private_codegen.cpp | 20 +-
.../parallel_master_taskloop_reduction_codegen.cpp | 22 +-
.../parallel_master_taskloop_simd_codegen.cpp | 160 +-
...l_master_taskloop_simd_firstprivate_codegen.cpp | 20 +-
...el_master_taskloop_simd_lastprivate_codegen.cpp | 470 +--
...rallel_master_taskloop_simd_private_codegen.cpp | 20 +-
...llel_master_taskloop_simd_reduction_codegen.cpp | 22 +-
clang/test/OpenMP/parallel_num_threads_codegen.cpp | 4 +-
clang/test/OpenMP/parallel_private_codegen.cpp | 261 +-
clang/test/OpenMP/parallel_reduction_codegen.cpp | 501 ++-
.../OpenMP/parallel_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/parallel_sections_codegen.cpp | 13 +-
.../parallel_sections_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/reduction_compound_op.cpp | 12 +-
.../test/OpenMP/sections_firstprivate_codegen.cpp | 321 +-
clang/test/OpenMP/sections_lastprivate_codegen.cpp | 433 ++-
clang/test/OpenMP/sections_private_codegen.cpp | 189 +-
clang/test/OpenMP/sections_reduction_codegen.cpp | 353 ++-
.../OpenMP/sections_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/simd_codegen.cpp | 8 +-
clang/test/OpenMP/single_codegen.cpp | 597 ++--
clang/test/OpenMP/single_firstprivate_codegen.cpp | 321 +-
clang/test/OpenMP/single_private_codegen.cpp | 189 +-
clang/test/OpenMP/target_codegen.cpp | 12 +-
.../test/OpenMP/target_codegen_global_capture.cpp | 104 +-
clang/test/OpenMP/target_defaultmap_codegen_01.cpp | 676 ++---
clang/test/OpenMP/target_depend_codegen.cpp | 14 +-
clang/test/OpenMP/target_enter_data_codegen.cpp | 2 +-
.../OpenMP/target_enter_data_depend_codegen.cpp | 8 +-
clang/test/OpenMP/target_exit_data_codegen.cpp | 2 +-
.../OpenMP/target_exit_data_depend_codegen.cpp | 8 +-
clang/test/OpenMP/target_firstprivate_codegen.cpp | 12 +-
clang/test/OpenMP/target_map_codegen_00.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_01.cpp | 4 +-
clang/test/OpenMP/target_map_codegen_02.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_03.cpp | 96 +-
clang/test/OpenMP/target_map_codegen_04.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_05.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_06.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_07.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_11.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_12.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_13.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_14.cpp | 4 +-
clang/test/OpenMP/target_map_codegen_15.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_17.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_24.cpp | 2 +-
clang/test/OpenMP/target_map_names.cpp | 2 +-
clang/test/OpenMP/target_map_names_attr.cpp | 2 +-
clang/test/OpenMP/target_parallel_codegen.cpp | 608 ++--
.../test/OpenMP/target_parallel_debug_codegen.cpp | 24 +-
.../test/OpenMP/target_parallel_depend_codegen.cpp | 12 +-
clang/test/OpenMP/target_parallel_for_codegen.cpp | 672 ++---
.../OpenMP/target_parallel_for_debug_codegen.cpp | 24 +-
.../OpenMP/target_parallel_for_depend_codegen.cpp | 12 +-
.../target_parallel_for_reduction_task_codegen.cpp | 40 +-
.../OpenMP/target_parallel_for_simd_codegen.cpp | 1008 +++----
.../target_parallel_for_simd_depend_codegen.cpp | 12 +-
clang/test/OpenMP/target_parallel_if_codegen.cpp | 464 +--
.../OpenMP/target_parallel_num_threads_codegen.cpp | 464 +--
.../target_parallel_reduction_task_codegen.cpp | 40 +-
clang/test/OpenMP/target_private_codegen.cpp | 4 +-
clang/test/OpenMP/target_reduction_codegen.cpp | 2 +-
clang/test/OpenMP/target_simd_codegen.cpp | 6 +-
clang/test/OpenMP/target_simd_depend_codegen.cpp | 12 +-
clang/test/OpenMP/target_teams_codegen.cpp | 928 +++---
clang/test/OpenMP/target_teams_depend_codegen.cpp | 12 +-
.../OpenMP/target_teams_distribute_codegen.cpp | 656 ++--
.../target_teams_distribute_collapse_codegen.cpp | 89 +-
.../target_teams_distribute_depend_codegen.cpp | 12 +-
...rget_teams_distribute_dist_schedule_codegen.cpp | 184 +-
...arget_teams_distribute_firstprivate_codegen.cpp | 573 ++--
...target_teams_distribute_lastprivate_codegen.cpp | 361 ++-
...arget_teams_distribute_parallel_for_codegen.cpp | 118 +-
</cut>
3 years, 7 months
- 1
- 0
[TCWG CI] 464.h264ref slowed down by 6% after llvm: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default
by ci_notify＠linaro.org
After llvm commit aacfbb953eb705af2ecfeb95a6262818fa85dd92
Author: hyeongyukim <gusrb406(a)snu.ac.kr>
[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 6% from 10889 to 11584 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O2 -flto
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2_LTO
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-aacfbb953eb705af2ecfeb95a6262818fa85dd92
cd investigate-llvm-aacfbb953eb705af2ecfeb95a6262818fa85dd92
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach aacfbb953eb705af2ecfeb95a6262818fa85dd92
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach b5aef90d4656c5188759d03e2c5c3dc3d8bb398b
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit aacfbb953eb705af2ecfeb95a6262818fa85dd92
Author: hyeongyukim <gusrb406(a)snu.ac.kr>
Date: Fri Oct 15 19:26:07 2021 +0900
[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default
Turning on `enable_noundef_analysis` flag allows better codegen by removing freeze instructions.
I modified clang by renaming `enable_noundef_analysis` flag to `disable-noundef-analysis` and turning it off by default.
Test updates are made as a separate patch: D108453
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D105169
[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default (2)
This patch updates test files after D105169.
Autogenerated test codes are changed by `utils/update_cc_test_checks.py,` and non-autogenerated test codes are changed as follows:
(1) I wrote a python script that (partially) updates the tests using regex: {F18594904} The script is not perfect, but I believe it gives hints about which patterns are updated to have `noundef` attached.
(2) The remaining tests are updated manually.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D108453
Resolve lit failures in clang after 8ca4b3e's land
Fix lit test failures in clang-ppc* and clang-x64-windows-msvc
Fix missing failures in clang-ppc64be* and retry fixing clang-x64-windows-msvc
Fix internal_clone(aarch64) inline assembly
---
clang/include/clang/Basic/CodeGenOptions.def | 2 +-
clang/include/clang/Driver/Options.td | 6 +-
clang/lib/CodeGen/CGCall.cpp | 4 +-
clang/test/CXX/except/except.spec/p14-ir.cpp | 4 +-
.../expr.prim/expr.prim.lambda/blocks-irgen.mm | 4 +-
clang/test/CodeGen/2005-01-02-ConstantInits.c | 10 +-
clang/test/CodeGen/2006-05-19-SingleEltReturn.c | 2 +-
clang/test/CodeGen/2007-06-18-SextAttrAggregate.c | 2 +-
.../test/CodeGen/2009-02-13-zerosize-union-field.c | 2 +-
clang/test/CodeGen/2009-05-04-EnumInreg.c | 2 +-
clang/test/CodeGen/64bit-swiftcall.c | 8 +-
clang/test/CodeGen/RISCV/riscv-inline-asm.c | 2 +-
clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c | 8 +-
.../test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c | 8 +-
.../RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c | 48 +-
clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c | 24 +-
clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c | 6 +-
.../test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c | 16 +-
clang/test/CodeGen/RISCV/riscv64-lp64-abi.c | 6 +-
clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c | 4 +-
.../CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c | 58 +-
clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c | 12 +-
clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c | 16 +-
clang/test/CodeGen/SystemZ/systemz-abi-vector.c | 18 +-
clang/test/CodeGen/SystemZ/systemz-abi.c | 22 +-
clang/test/CodeGen/SystemZ/systemz-inline-asm.c | 24 +-
clang/test/CodeGen/WebAssembly/wasm-arguments.c | 38 +-
.../test/CodeGen/WebAssembly/wasm-main_argc_argv.c | 2 +-
clang/test/CodeGen/X86/avx-union.c | 6 +-
clang/test/CodeGen/X86/avx512fp16-complex-abi.c | 2 +-
clang/test/CodeGen/X86/ms-x86-intrinsics.c | 32 +-
clang/test/CodeGen/X86/strictfp_builtins.c | 8 +-
clang/test/CodeGen/X86/x86-atomic-long_double.c | 36 +-
.../CodeGen/X86/x86-inline-asm-min-vector-width.c | 12 +-
clang/test/CodeGen/X86/x86-long-double.cpp | 6 +-
clang/test/CodeGen/X86/x86-soft-float.c | 4 +-
clang/test/CodeGen/X86/x86-vec-i128.c | 22 +-
clang/test/CodeGen/X86/x86_32-arguments-darwin.c | 62 +-
clang/test/CodeGen/X86/x86_32-arguments-iamcu.c | 24 +-
clang/test/CodeGen/X86/x86_32-arguments-linux.c | 30 +-
clang/test/CodeGen/X86/x86_32-arguments-nommx.c | 4 +-
clang/test/CodeGen/X86/x86_32-arguments-realign.c | 2 +-
clang/test/CodeGen/X86/x86_32-arguments-win32.c | 12 +-
clang/test/CodeGen/X86/x86_64-arguments-nacl.c | 6 +-
clang/test/CodeGen/X86/x86_64-arguments-win32.c | 12 +-
clang/test/CodeGen/X86/x86_64-arguments.c | 82 +-
clang/test/CodeGen/X86/x86_64-longdouble.c | 36 +-
clang/test/CodeGen/aapcs-align.cpp | 56 +-
clang/test/CodeGen/aapcs64-align.cpp | 34 +-
clang/test/CodeGen/aarch64-args.cpp | 18 +-
clang/test/CodeGen/aarch64-byval-temp.c | 8 +-
clang/test/CodeGen/aarch64-neon-3v.c | 160 +-
clang/test/CodeGen/aarch64-neon-across.c | 88 +-
clang/test/CodeGen/aarch64-neon-dot-product.c | 24 +-
clang/test/CodeGen/aarch64-neon-extract.c | 48 +-
clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c | 42 +-
clang/test/CodeGen/aarch64-neon-fma.c | 44 +-
clang/test/CodeGen/aarch64-neon-ldst-one.c | 540 ++--
clang/test/CodeGen/aarch64-neon-scalar-copy.c | 48 +-
.../CodeGen/aarch64-neon-scalar-x-indexed-elem.c | 80 +-
clang/test/CodeGen/aarch64-neon-tbl.c | 144 +-
clang/test/CodeGen/aarch64-neon-vcombine.c | 28 +-
clang/test/CodeGen/aarch64-neon-vget-hilo.c | 56 +-
clang/test/CodeGen/aarch64-neon-vget.c | 96 +-
clang/test/CodeGen/aarch64-poly128.c | 62 +-
clang/test/CodeGen/aarch64-poly64.c | 96 +-
clang/test/CodeGen/aarch64-strictfp-builtins.c | 8 +-
...4-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c | 16 +-
...sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp | 8 +-
clang/test/CodeGen/aarch64-varargs.c | 2 +-
clang/test/CodeGen/address-space-field1.c | 2 +-
clang/test/CodeGen/address-space.c | 2 +-
clang/test/CodeGen/aix-alignment.c | 8 +-
clang/test/CodeGen/aix-altivec.c | 10 +-
clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp | 12 +-
clang/test/CodeGen/aix-return.c | 16 +-
clang/test/CodeGen/aix-struct-arg.c | 44 +-
clang/test/CodeGen/aix-vaargs.c | 4 +-
clang/test/CodeGen/alias.c | 12 +-
clang/test/CodeGen/align_value.cpp | 63 +-
clang/test/CodeGen/alloc-align-attr.c | 46 +-
clang/test/CodeGen/alloc-fns-alignment.c | 2 +-
clang/test/CodeGen/alloc-size-fnptr.c | 12 +-
clang/test/CodeGen/arc/arguments.c | 26 +-
clang/test/CodeGen/arithmetic-fence-builtin.c | 10 +-
clang/test/CodeGen/arm-aapcs-vfp.c | 24 +-
clang/test/CodeGen/arm-abi-vector.c | 48 +-
clang/test/CodeGen/arm-arguments.c | 10 +-
clang/test/CodeGen/arm-bf16-params-returns.c | 10 +-
clang/test/CodeGen/arm-byval-align.c | 2 +-
clang/test/CodeGen/arm-cmse-attr.c | 4 +-
clang/test/CodeGen/arm-cmse-call.c | 4 +-
clang/test/CodeGen/arm-float-helpers.c | 76 +-
clang/test/CodeGen/arm-fp16-arguments.c | 12 +-
clang/test/CodeGen/arm-homogenous.c | 2 +-
clang/test/CodeGen/arm-mangle-bf16.cpp | 2 +-
clang/test/CodeGen/arm-neon-directed-rounding.c | 30 +-
clang/test/CodeGen/arm-neon-dot-product.c | 16 +-
clang/test/CodeGen/arm-neon-fma.c | 8 +-
clang/test/CodeGen/arm-neon-numeric-maxmin.c | 8 +-
clang/test/CodeGen/arm-neon-vcvtX.c | 32 +-
clang/test/CodeGen/arm-swiftcall.c | 6 +-
clang/test/CodeGen/arm-varargs.c | 2 +-
clang/test/CodeGen/arm-vector-arguments.c | 10 +-
clang/test/CodeGen/arm-vfp16-arguments.c | 12 +-
clang/test/CodeGen/arm64-aapcs-arguments.c | 12 +-
clang/test/CodeGen/arm64-abi-vector.c | 42 +-
clang/test/CodeGen/arm64-arguments.c | 96 +-
clang/test/CodeGen/arm64-microsoft-arguments.cpp | 6 +-
clang/test/CodeGen/arm64_32.c | 2 +-
clang/test/CodeGen/arm64_vcopy.c | 20 +-
clang/test/CodeGen/arm64_vdupq_n_f64.c | 12 +-
clang/test/CodeGen/armv7k-abi.c | 6 +-
clang/test/CodeGen/asm-label.c | 12 +-
.../assume-aligned-and-alloc-align-attributes.c | 12 +-
clang/test/CodeGen/atomic-arm64.c | 2 +-
clang/test/CodeGen/atomic-ops-libcall.c | 34 +-
clang/test/CodeGen/atomic-ops.c | 44 +-
clang/test/CodeGen/atomic_ops.c | 10 +-
clang/test/CodeGen/atomics-inlining.c | 52 +-
clang/test/CodeGen/attr-func-def.c | 4 +-
clang/test/CodeGen/attr-naked.c | 2 +-
clang/test/CodeGen/attr-no-tail.c | 8 +-
clang/test/CodeGen/attr-nomerge.cpp | 20 +-
clang/test/CodeGen/attr-noundef.cpp | 4 +-
clang/test/CodeGen/attr-target-mv-func-ptrs.c | 4 +-
clang/test/CodeGen/attr-target-mv-va-args.c | 24 +-
clang/test/CodeGen/attr-target-mv.c | 28 +-
clang/test/CodeGen/attr-x86-interrupt.c | 16 +-
clang/test/CodeGen/attributes.c | 2 +-
clang/test/CodeGen/available-externally-hidden.cpp | 2 +-
clang/test/CodeGen/available-externally-suppress.c | 2 +-
clang/test/CodeGen/avr/struct.c | 4 +-
clang/test/CodeGen/big-atomic-ops.c | 30 +-
clang/test/CodeGen/bittest-intrin.c | 8 +-
clang/test/CodeGen/blocks.c | 6 +-
clang/test/CodeGen/bool-convert.c | 2 +-
clang/test/CodeGen/builtin-align-array.c | 8 +-
clang/test/CodeGen/builtin-align.c | 24 +-
clang/test/CodeGen/builtin-assume-aligned.c | 31 +-
clang/test/CodeGen/builtin-attributes.c | 20 +-
clang/test/CodeGen/builtin-memfns.c | 4 +-
clang/test/CodeGen/builtin-sqrt.c | 2 +-
clang/test/CodeGen/builtins-arm.c | 24 +-
clang/test/CodeGen/builtins-memcpy-inline.c | 8 +-
clang/test/CodeGen/builtins-ms.c | 4 +-
clang/test/CodeGen/builtins-multiprecision.c | 4 +-
clang/test/CodeGen/builtins-overflow.c | 12 +-
clang/test/CodeGen/builtins-ppc-xlcompat-macros.c | 4 +-
clang/test/CodeGen/builtins.c | 44 +-
clang/test/CodeGen/c-strings.c | 2 +-
clang/test/CodeGen/c11atomics-ios.c | 8 +-
clang/test/CodeGen/c11atomics.c | 52 +-
clang/test/CodeGen/calling-conv-ignored.c | 32 +-
...-assumption-attribute-align_value-on-lvalue.cpp | 2 +-
...ssumption-attribute-align_value-on-paramvar.cpp | 4 +-
...-attribute-alloc_align-on-function-variable.cpp | 6 +-
...ssumption-attribute-alloc_align-on-function.cpp | 8 +-
...ibute-assume_aligned-on-function-two-params.cpp | 6 +-
...mption-attribute-assume_aligned-on-function.cpp | 8 +-
...uiltin_assume_aligned-three-params-variable.cpp | 2 +-
...umption-builtin_assume_aligned-three-params.cpp | 2 +-
...ssumption-builtin_assume_aligned-two-params.cpp | 2 +-
.../CodeGen/catch-alignment-assumption-openmp.cpp | 2 +-
.../CodeGen/catch-implicit-integer-sign-changes.c | 18 +-
...icit-signed-integer-truncation-or-sign-change.c | 10 +-
...tr-and-nonzero-offset-when-nullptr-is-defined.c | 2 +-
.../CodeGen/catch-nullptr-and-nonzero-offset.c | 14 +-
.../test/CodeGen/catch-pointer-overflow-volatile.c | 2 +-
clang/test/CodeGen/catch-pointer-overflow.c | 16 +-
clang/test/CodeGen/cfi-check-fail.c | 2 +-
clang/test/CodeGen/cfi-check-fail2.c | 2 +-
clang/test/CodeGen/cmse-clear-arg.c | 2 +-
clang/test/CodeGen/complex-builtins.c | 228 +-
clang/test/CodeGen/complex-indirect.c | 2 +-
clang/test/CodeGen/complex-libcalls.c | 228 +-
clang/test/CodeGen/complex-math.c | 12 +-
clang/test/CodeGen/complex-strictfp.c | 42 +-
clang/test/CodeGen/constructor-attribute.c | 2 +-
clang/test/CodeGen/debug-info-block-vars.c | 2 +-
clang/test/CodeGen/debug-info-pseudo-probe.cpp | 4 +-
clang/test/CodeGen/decl.c | 2 +-
clang/test/CodeGen/default-address-space.c | 4 +-
clang/test/CodeGen/exceptions-seh-finally.c | 14 +-
clang/test/CodeGen/exceptions-seh-leave.c | 30 +-
clang/test/CodeGen/exceptions-seh-nested-finally.c | 4 +-
clang/test/CodeGen/exceptions-seh.c | 26 +-
clang/test/CodeGen/exceptions.c | 2 +-
clang/test/CodeGen/ext-int-cc.c | 58 +-
clang/test/CodeGen/extend-arg-64.c | 2 +-
clang/test/CodeGen/fp-function-attrs.cpp | 6 +-
clang/test/CodeGen/fp-options-to-fast-math-flags.c | 18 +-
clang/test/CodeGen/fpconstrained-cmp-double.c | 24 +-
clang/test/CodeGen/fpconstrained-cmp-float.c | 24 +-
clang/test/CodeGen/function-attributes.c | 20 +-
clang/test/CodeGen/functions.c | 4 +-
clang/test/CodeGen/hexagon-hvx-abi.c | 8 +-
clang/test/CodeGen/incomplete-function-type-2.c | 2 +-
clang/test/CodeGen/indirect-noundef.cpp | 2 +-
clang/test/CodeGen/inline.c | 4 +-
clang/test/CodeGen/lanai-arguments.c | 12 +-
clang/test/CodeGen/lanai-regparm.c | 12 +-
clang/test/CodeGen/libcall-declarations.c | 636 ++--
clang/test/CodeGen/libcalls.c | 54 +-
clang/test/CodeGen/long_double_fp128.cpp | 14 +-
clang/test/CodeGen/malign-double-x86-nacl.c | 6 +-
clang/test/CodeGen/mangle-blocks.c | 6 +-
clang/test/CodeGen/mangle-windows.c | 2 +-
clang/test/CodeGen/math-builtins-long.c | 386 +--
clang/test/CodeGen/math-builtins.c | 648 ++--
clang/test/CodeGen/math-libcalls.c | 474 +--
clang/test/CodeGen/matrix-cast.c | 26 +-
clang/test/CodeGen/matrix-type-builtins.c | 4 +-
.../test/CodeGen/matrix-type-operators-fast-math.c | 12 +-
clang/test/CodeGen/matrix-type-operators.c | 84 +-
clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | 2 +-
clang/test/CodeGen/memcpy-inline-builtin.c | 2 +-
clang/test/CodeGen/microsoft-call-conv-x64.c | 2 +-
clang/test/CodeGen/microsoft-call-conv.c | 2 +-
clang/test/CodeGen/mingw-long-double.c | 12 +-
clang/test/CodeGen/mips-unsigned-ext-var.c | 6 +-
clang/test/CodeGen/mips-unsigned-extend.c | 6 +-
clang/test/CodeGen/mips-vector-arg.c | 16 +-
clang/test/CodeGen/mips-zero-sized-struct.c | 6 +-
clang/test/CodeGen/mips64-padding-arg.c | 24 +-
clang/test/CodeGen/mrtd.c | 6 +-
clang/test/CodeGen/ms-inline-asm.c | 2 +-
clang/test/CodeGen/ms-intrinsics-cpuid.c | 4 +-
clang/test/CodeGen/ms-intrinsics-other.c | 2 +-
clang/test/CodeGen/ms-mixed-ptr-sizes.c | 20 +-
clang/test/CodeGen/ms_abi.c | 4 +-
clang/test/CodeGen/ms_abi_aarch64.c | 4 +-
clang/test/CodeGen/named_reg_global.c | 2 +-
clang/test/CodeGen/no-bitfield-type-align.c | 2 +-
clang/test/CodeGen/no-builtin.cpp | 12 +-
clang/test/CodeGen/no-prototype.c | 2 +-
clang/test/CodeGen/noduplicate-cxx11-test.cpp | 2 +-
.../CodeGen/non-power-of-2-alignment-assumptions.c | 10 +-
clang/test/CodeGen/nonnull.c | 28 +-
clang/test/CodeGen/nrvo-tracking.cpp | 2 +-
clang/test/CodeGen/nvptx-abi.c | 10 +-
clang/test/CodeGen/object-size.c | 4 +-
clang/test/CodeGen/padding-init.c | 6 +-
clang/test/CodeGen/pass-by-value-noalias.c | 4 +-
clang/test/CodeGen/pass-object-size.c | 114 +-
clang/test/CodeGen/pch-dllexport.cpp | 4 +-
clang/test/CodeGen/powerpc-c99complex.c | 14 +-
clang/test/CodeGen/ppc-emmintrin.c | 750 ++---
clang/test/CodeGen/ppc-mm-malloc-le.c | 8 +-
clang/test/CodeGen/ppc-mm-malloc.c | 8 +-
clang/test/CodeGen/ppc-mmintrin.c | 124 +-
clang/test/CodeGen/ppc-pmmintrin.c | 177 +-
clang/test/CodeGen/ppc-signbit.c | 2 +-
clang/test/CodeGen/ppc-smmintrin.c | 32 +-
clang/test/CodeGen/ppc-tmmintrin.c | 290 +-
clang/test/CodeGen/ppc-xmmintrin.c | 400 +--
clang/test/CodeGen/ppc64-align-struct.c | 26 +-
clang/test/CodeGen/ppc64-complex-parms.c | 38 +-
clang/test/CodeGen/ppc64-complex-return.c | 20 +-
clang/test/CodeGen/ppc64-extend.c | 4 +-
clang/test/CodeGen/ppc64-inline-asm.c | 14 +-
clang/test/CodeGen/ppc64-long-double.cpp | 6 +-
clang/test/CodeGen/ppc64-soft-float.c | 6 +-
clang/test/CodeGen/ppc64-vector.c | 10 +-
clang/test/CodeGen/ppc64le-aggregates.c | 8 +-
clang/test/CodeGen/ppc64le-f128Aggregates.c | 4 +-
clang/test/CodeGen/ppc64le-varargs-f128.c | 12 +-
clang/test/CodeGen/pr25786.c | 4 +-
clang/test/CodeGen/pr5406.c | 2 +-
clang/test/CodeGen/pr9614.c | 4 +-
clang/test/CodeGen/pragma-weak.c | 2 +-
clang/test/CodeGen/ps4-dllimport-dllexport.c | 2 +-
clang/test/CodeGen/regcall.c | 100 +-
clang/test/CodeGen/regparm-flag.c | 12 +-
clang/test/CodeGen/regparm-struct.c | 36 +-
clang/test/CodeGen/regparm.c | 6 +-
clang/test/CodeGen/renderscript.c | 14 +-
clang/test/CodeGen/restrict.c | 10 +-
.../sanitize-thread-no-checking-at-run-time.m | 2 +-
clang/test/CodeGen/sparc-arguments.c | 4 +-
clang/test/CodeGen/sparcv8-abi.c | 6 +-
clang/test/CodeGen/sparcv8-inline-asm.c | 2 +-
clang/test/CodeGen/sparcv9-abi.c | 16 +-
clang/test/CodeGen/spir-half-type.cpp | 2 +-
clang/test/CodeGen/stack-protector.c | 4 +-
clang/test/CodeGen/stdcall-fastcall.c | 24 +-
clang/test/CodeGen/strictfp_builtins.c | 26 +-
clang/test/CodeGen/swift-async-call-conv.c | 22 +-
clang/test/CodeGen/switch-dce.c | 4 +-
clang/test/CodeGen/sysv_abi.c | 8 +-
clang/test/CodeGen/temporary-lifetime.cpp | 4 +-
clang/test/CodeGen/transparent-union-redecl.c | 8 +-
clang/test/CodeGen/transparent-union.c | 8 +-
clang/test/CodeGen/ubsan-function.cpp | 2 +-
.../CodeGen/unique-internal-linkage-names-dwarf.c | 4 +-
.../unique-internal-linkage-names-dwarf.cpp | 12 +-
.../test/CodeGen/unique-internal-linkage-names.cpp | 16 +-
clang/test/CodeGen/variadic-null-win64.c | 12 +-
clang/test/CodeGen/ve-abi.c | 34 +-
clang/test/CodeGen/vectorcall.c | 86 +-
clang/test/CodeGen/vla.c | 22 +-
clang/test/CodeGen/win64-i128.c | 4 +-
clang/test/CodeGen/windows-itanium.c | 2 +-
.../CodeGen/windows-on-arm-dllimport-dllexport.c | 2 +-
.../CodeGen/windows-seh-EHa-CppCatchDotDotDot.cpp | 2 +-
.../test/CodeGen/windows-seh-EHa-CppCondiTemps.cpp | 18 +-
clang/test/CodeGen/windows-seh-EHa-CppDtors01.cpp | 2 +-
.../test/CodeGen/windows-seh-EHa-TryInFinally.cpp | 4 +-
clang/test/CodeGen/windows-seh-abnormal-exits.c | 2 +-
clang/test/CodeGen/windows-swiftcall.c | 22 +-
clang/test/CodeGen/x86_32-align-linux.c | 6 +-
clang/test/CodeGen/xcore-abi.c | 14 +-
clang/test/CodeGen/xray-log-args.cpp | 4 +-
clang/test/CodeGenCUDA/address-spaces.cu | 2 +-
.../CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu | 10 +-
clang/test/CodeGenCUDA/builtins-amdgcn.cu | 2 +-
clang/test/CodeGenCUDA/cuda-builtin-vars.cu | 2 +-
clang/test/CodeGenCUDA/kernel-args-alignment.cu | 2 +-
clang/test/CodeGenCUDA/kernel-args.cu | 8 +-
clang/test/CodeGenCUDA/kernel-stub-name.cu | 4 +-
clang/test/CodeGenCUDA/lambda.cu | 8 +-
clang/test/CodeGenCUDA/redux-builtins.cu | 2 +-
clang/test/CodeGenCUDA/surface.cu | 4 +-
clang/test/CodeGenCUDA/texture.cu | 6 +-
clang/test/CodeGenCUDA/unnamed-types.cu | 8 +-
clang/test/CodeGenCUDA/usual-deallocators.cu | 36 +-
clang/test/CodeGenCUDA/vtbl.cu | 2 +-
.../CodeGenCXX/2009-05-04-PureConstNounwind.cpp | 10 +-
.../test/CodeGenCXX/2011-12-19-init-list-ctor.cpp | 6 +-
.../diamond-virtual-inheritance.cpp | 2 +-
.../CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp | 8 +-
.../RelativeVTablesABI/member-function-pointer.cpp | 2 +-
.../RelativeVTablesABI/multiple-inheritance.cpp | 2 +-
.../parent-and-child-in-comdats.cpp | 2 +-
.../CodeGenCXX/RelativeVTablesABI/type-info.cpp | 2 +-
.../CodeGenCXX/RelativeVTablesABI/vbase-offset.cpp | 2 +-
.../RelativeVTablesABI/virtual-function-call.cpp | 2 +-
clang/test/CodeGenCXX/address-space-cast.cpp | 14 +-
clang/test/CodeGenCXX/address-space-ref.cpp | 8 +-
clang/test/CodeGenCXX/aix-alignment.cpp | 6 +-
.../aix-static-init-temp-spec-and-inline-var.cpp | 14 +-
clang/test/CodeGenCXX/aix-static-init.cpp | 4 +-
.../test/CodeGenCXX/align-avx-complete-objects.cpp | 4 +-
clang/test/CodeGenCXX/alignment.cpp | 20 +-
clang/test/CodeGenCXX/alloc-size.cpp | 16 +-
.../test/CodeGenCXX/amdgcn-automatic-variable.cpp | 10 +-
clang/test/CodeGenCXX/amdgcn-func-arg.cpp | 24 +-
clang/test/CodeGenCXX/amdgcn_declspec_get.cpp | 2 +-
clang/test/CodeGenCXX/anonymous-namespaces.cpp | 4 +-
.../test/CodeGenCXX/apple-kext-indirect-call-2.cpp | 8 +-
clang/test/CodeGenCXX/apple-kext-linkage.cpp | 4 +-
clang/test/CodeGenCXX/arm-cc.cpp | 4 +-
clang/test/CodeGenCXX/arm-swiftcall.cpp | 2 +-
clang/test/CodeGenCXX/arm.cpp | 4 +-
clang/test/CodeGenCXX/arm64-constructor-return.cpp | 4 +-
clang/test/CodeGenCXX/arm64-darwinpcs.cpp | 4 +-
clang/test/CodeGenCXX/atomic-dllexport.cpp | 4 +-
clang/test/CodeGenCXX/atomic-inline.cpp | 2 +-
clang/test/CodeGenCXX/atomicinit.cpp | 8 +-
.../CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp | 28 +-
clang/test/CodeGenCXX/attr-disable-tail-calls.cpp | 12 +-
clang/test/CodeGenCXX/attr-musttail.cpp | 40 +-
clang/test/CodeGenCXX/attr-notail.cpp | 10 +-
clang/test/CodeGenCXX/attr-target-mv-diff-ns.cpp | 42 +-
clang/test/CodeGenCXX/attr-target-mv-func-ptrs.cpp | 6 +-
clang/test/CodeGenCXX/attr-target-mv-inalloca.cpp | 16 +-
.../CodeGenCXX/attr-target-mv-member-funcs.cpp | 96 +-
.../CodeGenCXX/attr-target-mv-out-of-line-defs.cpp | 22 +-
clang/test/CodeGenCXX/attr-target-mv-overloads.cpp | 36 +-
...used-member-function-implicit-instantiation.cpp | 2 +-
clang/test/CodeGenCXX/attr-x86-interrupt.cpp | 24 +-
clang/test/CodeGenCXX/blocks-cxx11.cpp | 16 +-
clang/test/CodeGenCXX/blocks.cpp | 4 +-
clang/test/CodeGenCXX/builtin-calling-conv.cpp | 18 +-
.../CodeGenCXX/builtin-is-constant-evaluated.cpp | 8 +-
.../CodeGenCXX/builtin-operator-new-delete.cpp | 20 +-
clang/test/CodeGenCXX/builtin-source-location.cpp | 20 +-
clang/test/CodeGenCXX/builtin_FUNCTION.cpp | 6 +-
clang/test/CodeGenCXX/builtin_LINE.cpp | 24 +-
clang/test/CodeGenCXX/builtins.cpp | 4 +-
clang/test/CodeGenCXX/call-with-static-chain.cpp | 16 +-
clang/test/CodeGenCXX/catch-undef-behavior.cpp | 10 +-
clang/test/CodeGenCXX/cfi-cast.cpp | 4 +-
clang/test/CodeGenCXX/cfi-multiple-inheritance.cpp | 2 +-
.../test/CodeGenCXX/cfi-vcall-check-after-args.cpp | 2 +-
clang/test/CodeGenCXX/clang-sections.cpp | 2 +-
clang/test/CodeGenCXX/compound-literals.cpp | 6 +-
clang/test/CodeGenCXX/condition.cpp | 30 +-
clang/test/CodeGenCXX/conditional-gnu-ext.cpp | 14 +-
clang/test/CodeGenCXX/conditional-temporaries.cpp | 44 +-
clang/test/CodeGenCXX/const-init-cxx11.cpp | 16 +-
.../constructor-destructor-return-this.cpp | 100 +-
clang/test/CodeGenCXX/constructor-direct-call.cpp | 14 +-
clang/test/CodeGenCXX/constructor-init.cpp | 10 +-
clang/test/CodeGenCXX/constructors.cpp | 24 +-
clang/test/CodeGenCXX/convert-to-fptr.cpp | 4 +-
clang/test/CodeGenCXX/copy-assign-synthesis-1.cpp | 2 +-
clang/test/CodeGenCXX/copy-constructor-elim-2.cpp | 2 +-
.../CodeGenCXX/copy-constructor-synthesis-2.cpp | 2 +-
.../test/CodeGenCXX/copy-constructor-synthesis.cpp | 6 +-
clang/test/CodeGenCXX/copy-elision.cpp | 2 +-
clang/test/CodeGenCXX/copy-initialization.cpp | 2 +-
clang/test/CodeGenCXX/cxx-abi-switch.cpp | 4 +-
clang/test/CodeGenCXX/cxx0x-delegating-ctors.cpp | 2 +-
.../CodeGenCXX/cxx0x-initializer-constructors.cpp | 14 +-
.../CodeGenCXX/cxx0x-initializer-references.cpp | 4 +-
.../CodeGenCXX/cxx11-initializer-aggregate.cpp | 4 +-
.../CodeGenCXX/cxx11-initializer-array-new.cpp | 30 +-
.../CodeGenCXX/cxx11-thread-local-reference.cpp | 6 +-
.../CodeGenCXX/cxx11-thread-local-visibility.cpp | 8 +-
clang/test/CodeGenCXX/cxx11-thread-local.cpp | 38 +-
.../test/CodeGenCXX/cxx11-user-defined-literal.cpp | 20 +-
clang/test/CodeGenCXX/cxx1y-init-captures.cpp | 12 +-
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clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp | 48 +-
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clang/test/CodeGenCXX/cxx1y-variable-template.cpp | 2 +-
clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp | 68 +-
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clang/test/CodeGenCXX/dllimport-members.cpp | 12 +-
clang/test/CodeGenCXX/dllimport-runtime-fns.cpp | 6 +-
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clang/test/CodeGenCXX/ext-int.cpp | 16 +-
clang/test/CodeGenCXX/fastcall.cpp | 2 +-
clang/test/CodeGenCXX/float128-declarations.cpp | 20 +-
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clang/test/CodeGenCXX/inalloca-overaligned.cpp | 38 +-
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clang/test/CodeGenCXX/inalloca-vector.cpp | 40 +-
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clang/test/CodeGenCXX/microsoft-abi-methods.cpp | 10 +-
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clang/test/CodeGenCXX/split-stacks.cpp | 12 +-
clang/test/CodeGenCXX/stack-reuse-miscompile.cpp | 8 +-
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clang/test/CodeGenCXX/tls-init-funcs.cpp | 10 +-
clang/test/CodeGenCXX/trivial_abi.cpp | 46 +-
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clang/test/CodeGenCXX/variadic-templates.cpp | 2 +-
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clang/test/CodeGenCXX/vtable-assume-load.cpp | 2 +-
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clang/test/CodeGenCoroutines/coro-alloc.cpp | 26 +-
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clang/test/CodeGenCoroutines/coro-promise-dtor.cpp | 2 +-
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.../test/CodeGenOpenCLCXX/addrspace-of-this.clcpp | 32 +-
.../CodeGenOpenCLCXX/addrspace-operators.clcpp | 4 +-
.../CodeGenOpenCLCXX/addrspace-references.clcpp | 2 +-
.../CodeGenOpenCLCXX/addrspace-with-class.clcpp | 22 +-
.../CodeGenOpenCLCXX/template-address-spaces.clcpp | 6 +-
.../test/CodeGenSYCL/address-space-conversions.cpp | 52 +-
clang/test/CodeGenSYCL/address-space-mangling.cpp | 16 +-
clang/test/CodeGenSYCL/unique_stable_name.cpp | 40 +-
clang/test/Headers/ms-arm64-intrin.cpp | 6 +-
clang/test/Headers/stdarg.cpp | 28 +-
clang/test/Modules/codegen-extern-template.cpp | 2 +-
clang/test/Modules/codegen.test | 2 +-
clang/test/Modules/cxx-irgen.cpp | 2 +-
clang/test/Modules/initializers.cpp | 4 +-
clang/test/Modules/templates.mm | 8 +-
clang/test/OpenMP/allocate_codegen.cpp | 2 +-
clang/test/OpenMP/allocate_codegen_attr.cpp | 2 +-
clang/test/OpenMP/assumes_include_nvptx.cpp | 6 +-
clang/test/OpenMP/atomic_capture_codegen.cpp | 28 +-
clang/test/OpenMP/atomic_codegen.cpp | 8 +-
clang/test/OpenMP/atomic_read_codegen.c | 14 +-
clang/test/OpenMP/atomic_update_codegen.cpp | 28 +-
clang/test/OpenMP/atomic_write_codegen.c | 18 +-
clang/test/OpenMP/cancel_codegen.cpp | 104 +-
clang/test/OpenMP/cancellation_point_codegen.cpp | 28 +-
clang/test/OpenMP/debug-info-complex-byval.cpp | 49 +-
clang/test/OpenMP/debug-info-openmp-array.cpp | 6 +-
clang/test/OpenMP/declare_mapper_codegen.cpp | 20 +-
clang/test/OpenMP/declare_reduction_codegen.c | 48 +-
clang/test/OpenMP/declare_reduction_codegen.cpp | 46 +-
.../declare_reduction_codegen_in_templates.cpp | 2 +-
clang/test/OpenMP/declare_target_codegen.cpp | 4 +-
.../declare_target_codegen_globalization.cpp | 12 +-
clang/test/OpenMP/declare_target_link_codegen.cpp | 4 +-
clang/test/OpenMP/declare_variant_mixed_codegen.c | 12 +-
clang/test/OpenMP/distribute_codegen.cpp | 304 +-
.../OpenMP/distribute_firstprivate_codegen.cpp | 329 +-
.../test/OpenMP/distribute_lastprivate_codegen.cpp | 361 ++-
.../OpenMP/distribute_parallel_for_codegen.cpp | 576 ++--
...istribute_parallel_for_firstprivate_codegen.cpp | 385 ++-
.../OpenMP/distribute_parallel_for_if_codegen.cpp | 320 +-
...distribute_parallel_for_lastprivate_codegen.cpp | 449 ++-
...distribute_parallel_for_num_threads_codegen.cpp | 481 ++-
.../distribute_parallel_for_private_codegen.cpp | 425 ++-
.../distribute_parallel_for_proc_bind_codegen.cpp | 29 +-
...tribute_parallel_for_reduction_task_codegen.cpp | 44 +-
.../distribute_parallel_for_simd_codegen.cpp | 592 ++--
...bute_parallel_for_simd_firstprivate_codegen.cpp | 1362 ++++-----
.../distribute_parallel_for_simd_if_codegen.cpp | 3192 ++++++++++----------
...ibute_parallel_for_simd_lastprivate_codegen.cpp | 1336 ++++----
...ibute_parallel_for_simd_num_threads_codegen.cpp | 2640 ++++++++--------
...istribute_parallel_for_simd_private_codegen.cpp | 1288 ++++----
...tribute_parallel_for_simd_proc_bind_codegen.cpp | 236 +-
clang/test/OpenMP/distribute_private_codegen.cpp | 345 ++-
clang/test/OpenMP/distribute_simd_codegen.cpp | 512 ++--
.../distribute_simd_firstprivate_codegen.cpp | 944 +++---
.../OpenMP/distribute_simd_lastprivate_codegen.cpp | 1008 +++----
.../OpenMP/distribute_simd_private_codegen.cpp | 1056 +++----
.../OpenMP/distribute_simd_reduction_codegen.cpp | 272 +-
clang/test/OpenMP/for_codegen.cpp | 16 +-
clang/test/OpenMP/for_firstprivate_codegen.cpp | 313 +-
clang/test/OpenMP/for_lastprivate_codegen.cpp | 601 ++--
clang/test/OpenMP/for_linear_codegen.cpp | 165 +-
clang/test/OpenMP/for_private_codegen.cpp | 177 +-
clang/test/OpenMP/for_reduction_codegen.cpp | 760 ++---
clang/test/OpenMP/for_reduction_codegen_UDR.cpp | 936 +++---
clang/test/OpenMP/for_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/for_scan_codegen.cpp | 2 +-
clang/test/OpenMP/for_simd_codegen.cpp | 6 +-
clang/test/OpenMP/for_simd_scan_codegen.cpp | 2 +-
clang/test/OpenMP/function-attr.cpp | 8 +-
clang/test/OpenMP/irbuilder_for_iterator.cpp | 24 +-
clang/test/OpenMP/irbuilder_for_rangefor.cpp | 28 +-
clang/test/OpenMP/irbuilder_for_unsigned.c | 6 +-
...builder_unroll_partial_heuristic_constant_for.c | 2 +-
...builder_unroll_partial_heuristic_for_collapse.c | 380 ++-
...rbuilder_unroll_partial_heuristic_runtime_for.c | 2 +-
clang/test/OpenMP/master_taskloop_codegen.cpp | 10 +-
.../master_taskloop_firstprivate_codegen.cpp | 22 +-
.../master_taskloop_in_reduction_codegen.cpp | 12 +-
.../OpenMP/master_taskloop_lastprivate_codegen.cpp | 22 +-
.../OpenMP/master_taskloop_private_codegen.cpp | 22 +-
.../OpenMP/master_taskloop_reduction_codegen.cpp | 22 +-
clang/test/OpenMP/master_taskloop_simd_codegen.cpp | 8 +-
.../master_taskloop_simd_firstprivate_codegen.cpp | 22 +-
.../master_taskloop_simd_in_reduction_codegen.cpp | 12 +-
.../master_taskloop_simd_lastprivate_codegen.cpp | 22 +-
.../master_taskloop_simd_private_codegen.cpp | 22 +-
.../master_taskloop_simd_reduction_codegen.cpp | 22 +-
clang/test/OpenMP/nvptx_allocate_codegen.cpp | 8 +-
clang/test/OpenMP/nvptx_data_sharing.cpp | 8 +-
.../nvptx_declare_target_var_ctor_dtor_codegen.cpp | 28 +-
.../OpenMP/nvptx_declare_variant_name_mangling.cpp | 4 +-
...tx_distribute_parallel_generic_mode_codegen.cpp | 48 +-
clang/test/OpenMP/nvptx_lambda_capturing.cpp | 122 +-
.../OpenMP/nvptx_multi_target_parallel_codegen.cpp | 18 +-
.../test/OpenMP/nvptx_nested_parallel_codegen.cpp | 72 +-
clang/test/OpenMP/nvptx_parallel_codegen.cpp | 52 +-
clang/test/OpenMP/nvptx_parallel_for_codegen.cpp | 6 +-
clang/test/OpenMP/nvptx_target_codegen.cpp | 10 +-
.../OpenMP/nvptx_target_firstprivate_codegen.cpp | 8 +-
.../test/OpenMP/nvptx_target_parallel_codegen.cpp | 48 +-
.../nvptx_target_parallel_num_threads_codegen.cpp | 48 +-
.../nvptx_target_parallel_reduction_codegen.cpp | 18 +-
...get_parallel_reduction_codegen_tbaa_PR46146.cpp | 10 +-
clang/test/OpenMP/nvptx_target_printf_codegen.c | 4 +-
clang/test/OpenMP/nvptx_target_teams_codegen.cpp | 48 +-
.../nvptx_target_teams_distribute_codegen.cpp | 18 +-
...arget_teams_distribute_parallel_for_codegen.cpp | 144 +-
...istribute_parallel_for_generic_mode_codegen.cpp | 72 +-
..._teams_distribute_parallel_for_simd_codegen.cpp | 72 +-
.../nvptx_target_teams_distribute_simd_codegen.cpp | 22 +-
clang/test/OpenMP/nvptx_teams_codegen.cpp | 32 +-
.../test/OpenMP/nvptx_teams_reduction_codegen.cpp | 162 +-
.../test/OpenMP/nvptx_unsupported_type_codegen.cpp | 4 +-
clang/test/OpenMP/openmp_offload_codegen.cpp | 2 +-
clang/test/OpenMP/openmp_win_codegen.cpp | 7 +-
clang/test/OpenMP/ordered_codegen.cpp | 76 +-
clang/test/OpenMP/parallel_codegen.cpp | 100 +-
clang/test/OpenMP/parallel_copyin_codegen.cpp | 613 ++--
.../test/OpenMP/parallel_firstprivate_codegen.cpp | 44 +-
clang/test/OpenMP/parallel_for_codegen.cpp | 224 +-
.../parallel_for_lastprivate_conditional.cpp | 17 +-
clang/test/OpenMP/parallel_for_linear_codegen.cpp | 93 +-
.../OpenMP/parallel_for_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/parallel_for_scan_codegen.cpp | 2 +-
.../OpenMP/parallel_for_simd_aligned_codegen.cpp | 72 +-
clang/test/OpenMP/parallel_for_simd_codegen.cpp | 6 +-
.../test/OpenMP/parallel_for_simd_scan_codegen.cpp | 2 +-
clang/test/OpenMP/parallel_if_codegen.cpp | 100 +-
clang/test/OpenMP/parallel_if_codegen_PR51349.cpp | 2 +-
clang/test/OpenMP/parallel_master_codegen.cpp | 63 +-
.../parallel_master_reduction_task_codegen.cpp | 36 +-
.../OpenMP/parallel_master_taskloop_codegen.cpp | 60 +-
...rallel_master_taskloop_firstprivate_codegen.cpp | 20 +-
...arallel_master_taskloop_lastprivate_codegen.cpp | 282 +-
.../parallel_master_taskloop_private_codegen.cpp | 20 +-
.../parallel_master_taskloop_reduction_codegen.cpp | 22 +-
.../parallel_master_taskloop_simd_codegen.cpp | 160 +-
...l_master_taskloop_simd_firstprivate_codegen.cpp | 20 +-
...el_master_taskloop_simd_lastprivate_codegen.cpp | 470 +--
...rallel_master_taskloop_simd_private_codegen.cpp | 20 +-
...llel_master_taskloop_simd_reduction_codegen.cpp | 22 +-
clang/test/OpenMP/parallel_num_threads_codegen.cpp | 4 +-
clang/test/OpenMP/parallel_private_codegen.cpp | 261 +-
clang/test/OpenMP/parallel_reduction_codegen.cpp | 501 ++-
.../OpenMP/parallel_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/parallel_sections_codegen.cpp | 13 +-
.../parallel_sections_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/reduction_compound_op.cpp | 12 +-
.../test/OpenMP/sections_firstprivate_codegen.cpp | 321 +-
clang/test/OpenMP/sections_lastprivate_codegen.cpp | 433 ++-
clang/test/OpenMP/sections_private_codegen.cpp | 189 +-
clang/test/OpenMP/sections_reduction_codegen.cpp | 353 ++-
.../OpenMP/sections_reduction_task_codegen.cpp | 36 +-
clang/test/OpenMP/simd_codegen.cpp | 8 +-
clang/test/OpenMP/single_codegen.cpp | 597 ++--
clang/test/OpenMP/single_firstprivate_codegen.cpp | 321 +-
clang/test/OpenMP/single_private_codegen.cpp | 189 +-
clang/test/OpenMP/target_codegen.cpp | 12 +-
.../test/OpenMP/target_codegen_global_capture.cpp | 104 +-
clang/test/OpenMP/target_defaultmap_codegen_01.cpp | 676 ++---
clang/test/OpenMP/target_depend_codegen.cpp | 14 +-
clang/test/OpenMP/target_enter_data_codegen.cpp | 2 +-
.../OpenMP/target_enter_data_depend_codegen.cpp | 8 +-
clang/test/OpenMP/target_exit_data_codegen.cpp | 2 +-
.../OpenMP/target_exit_data_depend_codegen.cpp | 8 +-
clang/test/OpenMP/target_firstprivate_codegen.cpp | 12 +-
clang/test/OpenMP/target_map_codegen_00.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_01.cpp | 4 +-
clang/test/OpenMP/target_map_codegen_02.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_03.cpp | 96 +-
clang/test/OpenMP/target_map_codegen_04.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_05.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_06.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_07.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_11.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_12.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_13.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_14.cpp | 4 +-
clang/test/OpenMP/target_map_codegen_15.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_17.cpp | 2 +-
clang/test/OpenMP/target_map_codegen_24.cpp | 2 +-
clang/test/OpenMP/target_map_names.cpp | 2 +-
clang/test/OpenMP/target_map_names_attr.cpp | 2 +-
clang/test/OpenMP/target_parallel_codegen.cpp | 608 ++--
.../test/OpenMP/target_parallel_debug_codegen.cpp | 24 +-
.../test/OpenMP/target_parallel_depend_codegen.cpp | 12 +-
clang/test/OpenMP/target_parallel_for_codegen.cpp | 672 ++---
.../OpenMP/target_parallel_for_debug_codegen.cpp | 24 +-
</cut>
3 years, 7 months
- 1
- 0
[TCWG CI] 464.h264ref slowed down by 7% after llvm: [PassManager] `buildModuleOptimizationPipeline()`: schedule `LoopDeletion` pass run before vectorization passes
by ci_notify＠linaro.org
After llvm commit 9c2469c1ddb34517de8dafd83d1940deada3fc22
Author: Roman Lebedev <lebedev.ri(a)gmail.com>
[PassManager] `buildModuleOptimizationPipeline()`: schedule `LoopDeletion` pass run before vectorization passes
the following benchmarks slowed down by more than 2%:
- 464.h264ref slowed down by 7% from 10836 to 11596 perf samples
- 464.h264ref:[.] FastFullPelBlockMotionSearch slowed down by 46% from 1525 to 2231 perf samples
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: aarch64-linux-gnu
- Compiler flags: -O3
- Hardware: NVidia TX1 4x Cortex-A57
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-9c2469c1ddb34517de8dafd83d1940deada3fc22
cd investigate-llvm-9c2469c1ddb34517de8dafd83d1940deada3fc22
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 9c2469c1ddb34517de8dafd83d1940deada3fc22
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 4bef0304e153c757c9f42c2001d4c56e8f99929e
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit 9c2469c1ddb34517de8dafd83d1940deada3fc22
Author: Roman Lebedev <lebedev.ri(a)gmail.com>
Date: Wed Nov 3 19:23:25 2021 +0300
[PassManager] `buildModuleOptimizationPipeline()`: schedule `LoopDeletion` pass run before vectorization passes
Test thanks to Michael Kuklinski from `#llvm`: https://godbolt.org/z/bdrah5Goo
originally inspired by Daniel Lemire's https://lemire.me/blog/2021/10/26/in-c-is-empty-faster-than-comparing-the-s…
We manage to deduce that the answer does not require looping,
but we do that after the last `LoopDeletion` pass run,
so we end up being stuck with a dead loop.
Now, as with all things SCEV, this has
a very expected ~`+0.12%` compile time performance regression:
https://llvm-compile-time-tracker.com/compare.php?from=0ae7bf124a9bca76dd9a…
(for comparison, doing that in function simplification pipeline
would have been ~`+0.5` compile time performance regression, D112840)
Looking at the transformation stats over vanilla test-suite, i think it's rather expected:
```
| statistic name | baseline | proposed | Δ | % | |%| |
|--------------------------------------------------|----------:|----------:|------:|-------:|-------:|
| scalar-evolution.NumBruteForceTripCountsComputed | 789 | 888 | 99 | 12.55% | 12.55% |
| scalar-evolution.NumTripCountsNotComputed | 105592 | 117900 | 12308 | 11.66% | 11.66% |
| loop-delete.NumBackedgesBroken | 542 | 559 | 17 | 3.14% | 3.14% |
| regalloc.numExtends | 81 | 79 | -2 | -2.47% | 2.47% |
| indvars.NumFoldedUser | 408 | 400 | -8 | -1.96% | 1.96% |
| indvars.NumElimCmp | 3831 | 3758 | -73 | -1.91% | 1.91% |
| scalar-evolution.NumTripCountsComputed | 299759 | 304278 | 4519 | 1.51% | 1.51% |
| loop-delete.NumDeleted | 8055 | 8128 | 73 | 0.91% | 0.91% |
| machine-cse.NumCommutes | 111 | 110 | -1 | -0.90% | 0.90% |
| globaldce.NumFunctions | 1187 | 1192 | 5 | 0.42% | 0.42% |
| codegenprepare.NumSelectsExpanded | 277 | 278 | 1 | 0.36% | 0.36% |
| loop-unroll.NumRuntimeUnrolled | 13841 | 13791 | -50 | -0.36% | 0.36% |
| machinelicm.NumPostRAHoisted | 1168 | 1172 | 4 | 0.34% | 0.34% |
| phi-node-elimination.NumCriticalEdgesSplit | 83054 | 82879 | -175 | -0.21% | 0.21% |
| machine-cse.NumPREs | 3085 | 3079 | -6 | -0.19% | 0.19% |
| branch-folder.NumBranchOpts | 108122 | 107942 | -180 | -0.17% | 0.17% |
| loop-unroll.NumUnrolled | 40136 | 40067 | -69 | -0.17% | 0.17% |
| branch-folder.NumDeadBlocks | 130818 | 130607 | -211 | -0.16% | 0.16% |
| codegenprepare.NumBlocksElim | 92856 | 92714 | -142 | -0.15% | 0.15% |
| instsimplify.NumSimplified | 103263 | 103129 | -134 | -0.13% | 0.13% |
| instcombine.NumConstProp | 26070 | 26102 | 32 | 0.12% | 0.12% |
| instsimplify.NumExpand | 1716 | 1718 | 2 | 0.12% | 0.12% |
| loop-unroll.NumCompletelyUnrolled | 9236 | 9225 | -11 | -0.12% | 0.12% |
| branch-folder.NumHoist | 2773 | 2770 | -3 | -0.11% | 0.11% |
| regalloc.NumReloadsRemoved | 10822 | 10834 | 12 | 0.11% | 0.11% |
| regalloc.NumSnippets | 11394 | 11406 | 12 | 0.11% | 0.11% |
| machine-cse.NumCrossBBCSEs | 1052 | 1053 | 1 | 0.10% | 0.10% |
| machinelicm.NumCSEed | 99887 | 99784 | -103 | -0.10% | 0.10% |
| branch-folder.NumTailMerge | 72501 | 72435 | -66 | -0.09% | 0.09% |
| codegenprepare.NumExtUses | 22007 | 21987 | -20 | -0.09% | 0.09% |
| local.NumRemoved | 68232 | 68294 | 62 | 0.09% | 0.09% |
| loop-vectorize.LoopsAnalyzed | 75483 | 75413 | -70 | -0.09% | 0.09% |
```
Note that i'm only changing current PM, and not touching obsolete PM.
This is an alternative to the function simplification pipeline variant
of the same change, D112840. It has both less compile time impact
(since the additional number of SCEV trip count calculations
is way lass less than with the D112840), and it is
much more powerful/impactful (almost 2x more loops deleted).
I have checked, and doing this after loop rotation
is favorable (more loops deleted).
Reviewed By: mkazantsev
Differential Revision: https://reviews.llvm.org/D112851
---
llvm/lib/Passes/PassBuilderPipelines.cpp | 9 +++-
llvm/test/Other/new-pm-defaults.ll | 1 +
llvm/test/Other/new-pm-thinlto-defaults.ll | 1 +
.../Other/new-pm-thinlto-postlink-pgo-defaults.ll | 1 +
.../new-pm-thinlto-postlink-samplepgo-defaults.ll | 1 +
...letion-of-loops-that-became-side-effect-free.ll | 49 ++++------------------
6 files changed, 18 insertions(+), 44 deletions(-)
diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp
index 2009a687ae7d..f0f7803ed3ae 100644
--- a/llvm/lib/Passes/PassBuilderPipelines.cpp
+++ b/llvm/lib/Passes/PassBuilderPipelines.cpp
@@ -1093,11 +1093,16 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level,
for (auto &C : VectorizerStartEPCallbacks)
C(OptimizePM, Level);
+ LoopPassManager LPM;
// First rotate loops that may have been un-rotated by prior passes.
// Disable header duplication at -Oz.
+ LPM.addPass(LoopRotatePass(Level != OptimizationLevel::Oz, LTOPreLink));
+ // Some loops may have become dead by now. Try to delete them.
+ // FIXME: see disscussion in https://reviews.llvm.org/D112851
+ // this may need to be revisited once GVN is more powerful.
+ LPM.addPass(LoopDeletionPass());
OptimizePM.addPass(createFunctionToLoopPassAdaptor(
- LoopRotatePass(Level != OptimizationLevel::Oz, LTOPreLink),
- /*UseMemorySSA=*/false, /*UseBlockFrequencyInfo=*/false));
+ std::move(LPM), /*UseMemorySSA=*/false, /*UseBlockFrequencyInfo=*/false));
// Distribute loops to allow partial vectorization. I.e. isolate dependences
// into separate loop that would otherwise inhibit vectorization. This is
diff --git a/llvm/test/Other/new-pm-defaults.ll b/llvm/test/Other/new-pm-defaults.ll
index 5067b6fbdd18..b9f90dad8224 100644
--- a/llvm/test/Other/new-pm-defaults.ll
+++ b/llvm/test/Other/new-pm-defaults.ll
@@ -216,6 +216,7 @@
; CHECK-O-NEXT: Running pass: LoopSimplifyPass
; CHECK-O-NEXT: Running pass: LCSSAPass
; CHECK-O-NEXT: Running pass: LoopRotatePass
+; CHECK-O-NEXT: Running pass: LoopDeletionPass
; CHECK-O-NEXT: Running pass: LoopDistributePass
; CHECK-O-NEXT: Running pass: InjectTLIMappings
; CHECK-O-NEXT: Running pass: LoopVectorizePass
diff --git a/llvm/test/Other/new-pm-thinlto-defaults.ll b/llvm/test/Other/new-pm-thinlto-defaults.ll
index 1f52fe47ae73..7836de5c6cce 100644
--- a/llvm/test/Other/new-pm-thinlto-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-defaults.ll
@@ -196,6 +196,7 @@
; CHECK-POSTLINK-O-NEXT: Running pass: LoopSimplifyPass
; CHECK-POSTLINK-O-NEXT: Running pass: LCSSAPass
; CHECK-POSTLINK-O-NEXT: Running pass: LoopRotatePass
+; CHECK-POSTLINK-O-NEXT: Running pass: LoopDeletionPass
; CHECK-POSTLINK-O-NEXT: Running pass: LoopDistributePass
; CHECK-POSTLINK-O-NEXT: Running pass: InjectTLIMappings
; CHECK-POSTLINK-O-NEXT: Running pass: LoopVectorizePass
diff --git a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
index 3a80efba3c56..e66e8672358c 100644
--- a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
@@ -167,6 +167,7 @@
; CHECK-O-NEXT: Running pass: LoopSimplifyPass on foo
; CHECK-O-NEXT: Running pass: LCSSAPass on foo
; CHECK-O-NEXT: Running pass: LoopRotatePass
+; CHECK-O-NEXT: Running pass: LoopDeletionPass
; CHECK-O-NEXT: Running pass: LoopDistributePass
; CHECK-O-NEXT: Running pass: InjectTLIMappings
; CHECK-O-NEXT: Running pass: LoopVectorizePass
diff --git a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
index 2e822b21f8a1..410841124c8e 100644
--- a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
+++ b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
@@ -179,6 +179,7 @@
; CHECK-O-NEXT: Running pass: LoopSimplifyPass
; CHECK-O-NEXT: Running pass: LCSSAPass
; CHECK-O-NEXT: Running pass: LoopRotatePass
+; CHECK-O-NEXT: Running pass: LoopDeletionPass
; CHECK-O-NEXT: Running pass: LoopDistributePass
; CHECK-O-NEXT: Running pass: InjectTLIMappings
; CHECK-O-NEXT: Running pass: LoopVectorizePass
diff --git a/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll b/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll
index ec8db3cceeb1..99a52acd3b2b 100644
--- a/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll
+++ b/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll
@@ -11,17 +11,8 @@
define dso_local zeroext i1 @is_not_empty_variant1(%struct.node* %p) {
; ALL-LABEL: @is_not_empty_variant1(
; ALL-NEXT: entry:
-; ALL-NEXT: [[TOBOOL_NOT3_I:%.*]] = icmp eq %struct.node* [[P:%.*]], null
-; ALL-NEXT: br i1 [[TOBOOL_NOT3_I]], label [[COUNT_NODES_VARIANT1_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
-; ALL: while.body.i:
-; ALL-NEXT: [[P_ADDR_04_I:%.*]] = phi %struct.node* [ [[TMP0:%.*]], [[WHILE_BODY_I]] ], [ [[P]], [[ENTRY:%.*]] ]
-; ALL-NEXT: [[NEXT_I:%.*]] = getelementptr inbounds [[STRUCT_NODE:%.*]], %struct.node* [[P_ADDR_04_I]], i64 0, i32 0
-; ALL-NEXT: [[TMP0]] = load %struct.node*, %struct.node** [[NEXT_I]], align 8
-; ALL-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq %struct.node* [[TMP0]], null
-; ALL-NEXT: br i1 [[TOBOOL_NOT_I]], label [[COUNT_NODES_VARIANT1_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP0:![0-9]+]]
-; ALL: count_nodes_variant1.exit:
-; ALL-NEXT: [[TMP1:%.*]] = xor i1 [[TOBOOL_NOT3_I]], true
-; ALL-NEXT: ret i1 [[TMP1]]
+; ALL-NEXT: [[TOBOOL_NOT3_I:%.*]] = icmp ne %struct.node* [[P:%.*]], null
+; ALL-NEXT: ret i1 [[TOBOOL_NOT3_I]]
;
entry:
%p.addr = alloca %struct.node*, align 8
@@ -113,39 +104,13 @@ while.end:
define dso_local zeroext i1 @is_not_empty_variant3(%struct.node* %p) {
; O3-LABEL: @is_not_empty_variant3(
; O3-NEXT: entry:
-; O3-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp eq %struct.node* [[P:%.*]], null
-; O3-NEXT: br i1 [[TOBOOL_NOT4_I]], label [[COUNT_NODES_VARIANT3_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
-; O3: while.body.i:
-; O3-NEXT: [[SIZE_06_I:%.*]] = phi i64 [ [[INC_I:%.*]], [[WHILE_BODY_I]] ], [ 0, [[ENTRY:%.*]] ]
-; O3-NEXT: [[P_ADDR_05_I:%.*]] = phi %struct.node* [ [[TMP0:%.*]], [[WHILE_BODY_I]] ], [ [[P]], [[ENTRY]] ]
-; O3-NEXT: [[CMP_I:%.*]] = icmp ne i64 [[SIZE_06_I]], -1
-; O3-NEXT: tail call void @llvm.assume(i1 [[CMP_I]]) #[[ATTR3:[0-9]+]]
-; O3-NEXT: [[NEXT_I:%.*]] = getelementptr inbounds [[STRUCT_NODE:%.*]], %struct.node* [[P_ADDR_05_I]], i64 0, i32 0
-; O3-NEXT: [[TMP0]] = load %struct.node*, %struct.node** [[NEXT_I]], align 8
-; O3-NEXT: [[INC_I]] = add nuw i64 [[SIZE_06_I]], 1
-; O3-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq %struct.node* [[TMP0]], null
-; O3-NEXT: br i1 [[TOBOOL_NOT_I]], label [[COUNT_NODES_VARIANT3_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP2:![0-9]+]]
-; O3: count_nodes_variant3.exit:
-; O3-NEXT: [[TMP1:%.*]] = xor i1 [[TOBOOL_NOT4_I]], true
-; O3-NEXT: ret i1 [[TMP1]]
+; O3-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne %struct.node* [[P:%.*]], null
+; O3-NEXT: ret i1 [[TOBOOL_NOT4_I]]
;
; O2-LABEL: @is_not_empty_variant3(
; O2-NEXT: entry:
-; O2-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp eq %struct.node* [[P:%.*]], null
-; O2-NEXT: br i1 [[TOBOOL_NOT4_I]], label [[COUNT_NODES_VARIANT3_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
-; O2: while.body.i:
-; O2-NEXT: [[SIZE_06_I:%.*]] = phi i64 [ [[INC_I:%.*]], [[WHILE_BODY_I]] ], [ 0, [[ENTRY:%.*]] ]
-; O2-NEXT: [[P_ADDR_05_I:%.*]] = phi %struct.node* [ [[TMP0:%.*]], [[WHILE_BODY_I]] ], [ [[P]], [[ENTRY]] ]
-; O2-NEXT: [[CMP_I:%.*]] = icmp ne i64 [[SIZE_06_I]], -1
-; O2-NEXT: tail call void @llvm.assume(i1 [[CMP_I]]) #[[ATTR3:[0-9]+]]
-; O2-NEXT: [[NEXT_I:%.*]] = getelementptr inbounds [[STRUCT_NODE:%.*]], %struct.node* [[P_ADDR_05_I]], i64 0, i32 0
-; O2-NEXT: [[TMP0]] = load %struct.node*, %struct.node** [[NEXT_I]], align 8
-; O2-NEXT: [[INC_I]] = add nuw i64 [[SIZE_06_I]], 1
-; O2-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq %struct.node* [[TMP0]], null
-; O2-NEXT: br i1 [[TOBOOL_NOT_I]], label [[COUNT_NODES_VARIANT3_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP2:![0-9]+]]
-; O2: count_nodes_variant3.exit:
-; O2-NEXT: [[TMP1:%.*]] = xor i1 [[TOBOOL_NOT4_I]], true
-; O2-NEXT: ret i1 [[TMP1]]
+; O2-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne %struct.node* [[P:%.*]], null
+; O2-NEXT: ret i1 [[TOBOOL_NOT4_I]]
;
; O1-LABEL: @is_not_empty_variant3(
; O1-NEXT: entry:
@@ -160,7 +125,7 @@ define dso_local zeroext i1 @is_not_empty_variant3(%struct.node* %p) {
; O1-NEXT: [[TMP0]] = load %struct.node*, %struct.node** [[NEXT_I]], align 8
; O1-NEXT: [[INC_I]] = add i64 [[SIZE_06_I]], 1
; O1-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq %struct.node* [[TMP0]], null
-; O1-NEXT: br i1 [[TOBOOL_NOT_I]], label [[COUNT_NODES_VARIANT3_EXIT_LOOPEXIT:%.*]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP2:![0-9]+]]
+; O1-NEXT: br i1 [[TOBOOL_NOT_I]], label [[COUNT_NODES_VARIANT3_EXIT_LOOPEXIT:%.*]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP0:![0-9]+]]
; O1: count_nodes_variant3.exit.loopexit:
; O1-NEXT: [[PHI_CMP:%.*]] = icmp ne i64 [[INC_I]], 0
; O1-NEXT: br label [[COUNT_NODES_VARIANT3_EXIT]]
</cut>
3 years, 7 months
- 1
- 0
[ACTIVITY] week ending Nov. 7 2021
by Alex Bennée
VirtIO Initiative ([STR-9])
===========================
- various rust-vmm discussions
- [upstream rust-vmm sync meeting]
- how to deal with vhost-device/vm-virtio split: [proposal]
- synced with ARM on their interests
- got update on Fwd: FW: [App-services] Slides from the
hypervisor-less virtio status meeting Message-Id:
<CAHDbmO2G4hUyfxtaxwnbxsrMk+P41zbL-7VNe=Aa6DshxC-5zQ(a)mail.gmail.com>
[STR-9] <https://linaro.atlassian.net/browse/STR-9>
[upstream rust-vmm sync meeting]
<https://etherpad.opendev.org/p/rust-vmm-sync-2021&sa=D&source=calendar&ust=…>
[proposal] <https://github.com/rust-vmm/vhost-device/pull/57>
QEMU Upstream Work ([UM-2])
===========================
- did some bug triage and investigated [555] and [690] which might
intersect with earlier changes I made
- spent time on the PR from hell [PULL 00/30] testing, gdbstub and
semihosting Message-Id:
<20210115130828.23968-1-alex.bennee(a)linaro.org>
[UM-2] <https://linaro.atlassian.net/browse/UM-2>
[555] <https://gitlab.com/qemu-project/qemu/-/issues/555>
[690] <https://gitlab.com/qemu-project/qemu/-/issues/690>
Other
=====
- TSC report preparation for QEMU and Stratos
Completed Reviews [1/1]
=======================
[XEN PATCH v7 00/51] xen: Build system improvements, now with out-of-tree build!
Message-Id: <20210824105038.1257926-1-anthony.perard(a)citrix.com>
Absences
========
,----
| (save-excursion
| (goto-char (point-min))
| (when (re-search-forward "* Absences")
| (goto-char (match-beginning 0))
| (org-export-as 'ascii t nil t )))
`----
Current Review Queue
====================
TODO [PATCH v2 00/48] tcg: optimize redundant sign extensions
Message-Id: <20211007195456.1168070-1-richard.henderson(a)linaro.org>
================================================================================================================================
TODO [PATCH] cpu-models-x86.rst: Tidy up a couple of things
Message-Id: <20211015100718.17828-1-pbonzini(a)redhat.com>
===================================================================================================================
TODO [PATCH 00/16] fdt: Make OF_BOARD a boolean option
Message-Id: <20211013010120.96851-1-sjg(a)chromium.org>
===========================================================================================================
TODO [PATCH v4 00/41] linux-user: Streamline handling of SIGSEGV
Message-Id: <20211006172307.780893-1-richard.henderson(a)linaro.org>
==================================================================================================================================
--
Alex Bennée
3 years, 7 months
- 1
- 0
[ACTIVITY] report week ending 5 Nov
by Peter Maydell
Progress
* UM-2 [QEMU upstream maintainership]
+ worked through the big pile of email that had built up while
I was on holiday...
+ some long-delayed sysadmin tasks on my work machines now I have
an opportunity to go into the office and do things that would be
too risky with only remote access
+ triaged a bunch of Coverity issues
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
+ All work here has now gone upstream; closed!
-- PMM
3 years, 7 months
- 1
- 0
[TCWG CI] 401.bzip2 grew in size by 4% after llvm: Revert "Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when switch cover all possible values.""""
by ci_notify＠linaro.org
After llvm commit c93f93b2e3f28997f794265089fb8138dd5b5f13
Author: Jun Ma <JunMa(a)linux.alibaba.com>
Revert "Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when switch cover all possible values.""""
the following benchmarks grew in size by more than 1%:
- 401.bzip2 grew in size by 4% from 36134 to 37534 bytes
- 401.bzip2:[.] BZ2_decompress grew in size by 19% from 7256 to 8656 bytes
Below reproducer instructions can be used to re-build both "first_bad" and "last_good" cross-toolchains used in this bisection. Naturally, the scripts will fail when triggerring benchmarking jobs if you don't have access to Linaro TCWG CI.
For your convenience, we have uploaded tarballs with pre-processed source and assembly files at:
- First_bad save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Last_good save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
- Baseline save-temps: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Configuration:
- Benchmark: SPEC CPU2006
- Toolchain: Clang + Glibc + LLVM Linker
- Version: all components were built from their tip of trunk
- Target: arm-linux-gnueabihf
- Compiler flags: -Oz -mthumb
- Hardware: APM Mustang 8x X-Gene1
This benchmarking CI is work-in-progress, and we welcome feedback and suggestions at linaro-toolchain(a)lists.linaro.org . In our improvement plans is to add support for SPEC CPU2017 benchmarks and provide "perf report/annotate" data behind these reports.
THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT.
This commit has regressed these CI configurations:
- tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Oz
First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-…
Reproduce builds:
<cut>
mkdir investigate-llvm-c93f93b2e3f28997f794265089fb8138dd5b5f13
cd investigate-llvm-c93f93b2e3f28997f794265089fb8138dd5b5f13
# Fetch scripts
git clone https://git.linaro.org/toolchain/jenkins-scripts
# Fetch manifests and test.sh script
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_apm-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach c93f93b2e3f28997f794265089fb8138dd5b5f13
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach b4fb42300e39c99ac5bb9d02b304b713fabdec4d
../artifacts/test.sh
cd ..
</cut>
Full commit (up to 1000 lines):
<cut>
commit c93f93b2e3f28997f794265089fb8138dd5b5f13
Author: Jun Ma <JunMa(a)linux.alibaba.com>
Date: Tue Sep 28 09:44:00 2021 +0800
Revert "Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when switch cover all possible values.""""
This reverts commit 3a998c06a8e93989319238e12b56a731198cc1c2.
---
llvm/include/llvm/Transforms/Utils/Local.h | 5 ++++
.../Scalar/CorrelatedValuePropagation.cpp | 27 +++++++++++++++++++++-
llvm/lib/Transforms/Utils/Local.cpp | 20 ++++++++++++++++
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 20 ----------------
.../Transforms/CorrelatedValuePropagation/basic.ll | 11 +++++----
5 files changed, 57 insertions(+), 26 deletions(-)
diff --git a/llvm/include/llvm/Transforms/Utils/Local.h b/llvm/include/llvm/Transforms/Utils/Local.h
index 3c529abce85a..72cb606eb51a 100644
--- a/llvm/include/llvm/Transforms/Utils/Local.h
+++ b/llvm/include/llvm/Transforms/Utils/Local.h
@@ -55,6 +55,7 @@ class MDNode;
class MemorySSAUpdater;
class PHINode;
class StoreInst;
+class SwitchInst;
class TargetLibraryInfo;
class TargetTransformInfo;
@@ -237,6 +238,10 @@ CallInst *createCallMatchingInvoke(InvokeInst *II);
/// This function converts the specified invoek into a normall call.
void changeToCall(InvokeInst *II, DomTreeUpdater *DTU = nullptr);
+/// This function removes the default destination from the specified switch.
+void createUnreachableSwitchDefault(SwitchInst *Switch,
+ DomTreeUpdater *DTU = nullptr);
+
///===---------------------------------------------------------------------===//
/// Dbg Intrinsic utilities
///
diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
index 6dbd3da24059..4b8392db9628 100644
--- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
+++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
@@ -341,7 +341,13 @@ static bool processSwitch(SwitchInst *I, LazyValueInfo *LVI,
// ConstantFoldTerminator() as the underlying SwitchInst can be changed.
SwitchInstProfUpdateWrapper SI(*I);
- for (auto CI = SI->case_begin(), CE = SI->case_end(); CI != CE;) {
+ APInt Low =
+ APInt::getSignedMaxValue(Cond->getType()->getScalarSizeInBits());
+ APInt High =
+ APInt::getSignedMinValue(Cond->getType()->getScalarSizeInBits());
+
+ SwitchInst::CaseIt CI = SI->case_begin();
+ for (auto CE = SI->case_end(); CI != CE;) {
ConstantInt *Case = CI->getCaseValue();
LazyValueInfo::Tristate State =
LVI->getPredicateAt(CmpInst::ICMP_EQ, Cond, Case, I,
@@ -374,9 +380,28 @@ static bool processSwitch(SwitchInst *I, LazyValueInfo *LVI,
break;
}
+ // Get Lower/Upper bound from switch cases.
+ Low = APIntOps::smin(Case->getValue(), Low);
+ High = APIntOps::smax(Case->getValue(), High);
+
// Increment the case iterator since we didn't delete it.
++CI;
}
+
+ // Try to simplify default case as unreachable
+ if (CI == SI->case_end() && SI->getNumCases() != 0 &&
+ !isa<UnreachableInst>(SI->getDefaultDest()->getFirstNonPHIOrDbg())) {
+ const ConstantRange SIRange =
+ LVI->getConstantRange(SI->getCondition(), SI);
+
+ // If the numbered switch cases cover the entire range of the condition,
+ // then the default case is not reachable.
+ if (SIRange.getSignedMin() == Low && SIRange.getSignedMax() == High &&
+ SI->getNumCases() == High - Low + 1) {
+ createUnreachableSwitchDefault(SI, &DTU);
+ Changed = true;
+ }
+ }
}
if (Changed)
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 3e36f498523d..74ab37fadf36 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2190,6 +2190,26 @@ void llvm::changeToCall(InvokeInst *II, DomTreeUpdater *DTU) {
DTU->applyUpdates({{DominatorTree::Delete, BB, UnwindDestBB}});
}
+void llvm::createUnreachableSwitchDefault(SwitchInst *Switch,
+ DomTreeUpdater *DTU) {
+ LLVM_DEBUG(dbgs() << "SimplifyCFG: switch default is dead.\n");
+ auto *BB = Switch->getParent();
+ auto *OrigDefaultBlock = Switch->getDefaultDest();
+ OrigDefaultBlock->removePredecessor(BB);
+ BasicBlock *NewDefaultBlock = BasicBlock::Create(
+ BB->getContext(), BB->getName() + ".unreachabledefault", BB->getParent(),
+ OrigDefaultBlock);
+ new UnreachableInst(Switch->getContext(), NewDefaultBlock);
+ Switch->setDefaultDest(&*NewDefaultBlock);
+ if (DTU) {
+ SmallVector<DominatorTree::UpdateType, 2> Updates;
+ Updates.push_back({DominatorTree::Insert, BB, &*NewDefaultBlock});
+ if (!is_contained(successors(BB), OrigDefaultBlock))
+ Updates.push_back({DominatorTree::Delete, BB, &*OrigDefaultBlock});
+ DTU->applyUpdates(Updates);
+ }
+}
+
BasicBlock *llvm::changeToInvokeAndSplitBasicBlock(CallInst *CI,
BasicBlock *UnwindEdge,
DomTreeUpdater *DTU) {
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 7b49f47778e0..3eab293b433e 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -4782,26 +4782,6 @@ static bool CasesAreContiguous(SmallVectorImpl<ConstantInt *> &Cases) {
return true;
}
-static void createUnreachableSwitchDefault(SwitchInst *Switch,
- DomTreeUpdater *DTU) {
- LLVM_DEBUG(dbgs() << "SimplifyCFG: switch default is dead.\n");
- auto *BB = Switch->getParent();
- auto *OrigDefaultBlock = Switch->getDefaultDest();
- OrigDefaultBlock->removePredecessor(BB);
- BasicBlock *NewDefaultBlock = BasicBlock::Create(
- BB->getContext(), BB->getName() + ".unreachabledefault", BB->getParent(),
- OrigDefaultBlock);
- new UnreachableInst(Switch->getContext(), NewDefaultBlock);
- Switch->setDefaultDest(&*NewDefaultBlock);
- if (DTU) {
- SmallVector<DominatorTree::UpdateType, 2> Updates;
- Updates.push_back({DominatorTree::Insert, BB, &*NewDefaultBlock});
- if (!is_contained(successors(BB), OrigDefaultBlock))
- Updates.push_back({DominatorTree::Delete, BB, &*OrigDefaultBlock});
- DTU->applyUpdates(Updates);
- }
-}
-
/// Turn a switch with two reachable destinations into an integer range
/// comparison and branch.
bool SimplifyCFGOpt::TurnSwitchRangeIntoICmp(SwitchInst *SI,
diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll b/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
index 5abbcbc90e01..a620c8468d4d 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
@@ -382,7 +382,7 @@ define i32 @switch_range(i32 %cond) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[S:%.*]] = urem i32 [[COND:%.*]], 3
; CHECK-NEXT: [[S1:%.*]] = add nuw nsw i32 [[S]], 1
-; CHECK-NEXT: switch i32 [[S1]], label [[UNREACHABLE:%.*]] [
+; CHECK-NEXT: switch i32 [[S1]], label [[ENTRY_UNREACHABLEDEFAULT:%.*]] [
; CHECK-NEXT: i32 1, label [[EXIT1:%.*]]
; CHECK-NEXT: i32 2, label [[EXIT2:%.*]]
; CHECK-NEXT: i32 3, label [[EXIT1]]
@@ -391,6 +391,8 @@ define i32 @switch_range(i32 %cond) {
; CHECK-NEXT: ret i32 1
; CHECK: exit2:
; CHECK-NEXT: ret i32 2
+; CHECK: entry.unreachabledefault:
+; CHECK-NEXT: unreachable
; CHECK: unreachable:
; CHECK-NEXT: ret i32 0
;
@@ -453,10 +455,9 @@ define i8 @switch_defaultdest_multipleuse(i8 %t0) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[O:%.*]] = or i8 [[T0:%.*]], 1
; CHECK-NEXT: [[R:%.*]] = srem i8 1, [[O]]
-; CHECK-NEXT: switch i8 [[R]], label [[EXIT:%.*]] [
-; CHECK-NEXT: i8 0, label [[EXIT]]
-; CHECK-NEXT: i8 1, label [[EXIT]]
-; CHECK-NEXT: ]
+; CHECK-NEXT: br label [[EXIT:%.*]]
+; CHECK: entry.unreachabledefault:
+; CHECK-NEXT: unreachable
; CHECK: exit:
; CHECK-NEXT: ret i8 0
;
</cut>
3 years, 8 months
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