Successfully identified regression in *gcc* in CI configuration tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2. So far, this commit has regressed CI configurations:
- tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2
Culprit:
<cut>
commit d999d9b7e53b9a9cd2004a19e84c637e5e5013f5
Author: Patrick Palka <ppalka(a)redhat.com>
Date: Thu Jun 3 09:39:13 2021 -0400
c++: cv-qualified dependent name of alias tmpl [PR100592]
Here, the dependent template name in the return type of f() resolves to
an alias of int& after substitution, and we end up complaining about
qualifying this reference type with 'const' from cp_build_qualified_type
rather than just silently dropping the qualification as per [dcl.ref]/1.
The problem is ultimately that make_typename_type ignores the
tf_keep_type_decl flag when the dependent name is a template-id. This
in turn causes the TYPE_DECL check within tsubst <case TYPENAME_TYPE>
to fail, and so we end up not passing tf_ignore_bad_quals to
cp_build_qualified_type. This patch fixes this by making
make_typename_type respect the tf_keep_type_decl flag in this situation.
PR c++/100592
gcc/cp/ChangeLog:
* decl.c (make_typename_type): After calling
lookup_template_class, adjust the result to its TYPE_NAME and
then consider the tf_keep_type_decl flag.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/alias-decl-71.C: New test.
</cut>
Results regressed to (for first_bad == d999d9b7e53b9a9cd2004a19e84c637e5e5013f5)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer:
-5
# true:
0
# benchmark -O2 -- artifacts/build-d999d9b7e53b9a9cd2004a19e84c637e5e5013f5/results_id:
1
# 447.dealII,dealII_base.default regressed by 103
# 447.dealII,[.] _ZNK8MappingQILi3EE19transform_covariantEP6Ten regressed by 117
from (for last_good == 69f517ac20566a645ff41a9bfca535822205a538)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer:
-5
# true:
0
# benchmark -O2 -- artifacts/build-69f517ac20566a645ff41a9bfca535822205a538/results_id:
1
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa…
Results ID of last_good: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2/2208
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa…
Results ID of first_bad: tx1_64/tcwg_bmk_gnu_tx1/bisect-gnu-master-aarch64-spec2k6-O2/2248
Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa…
Configuration details:
Reproduce builds:
<cut>
mkdir investigate-gcc-d999d9b7e53b9a9cd2004a19e84c637e5e5013f5
cd investigate-gcc-d999d9b7e53b9a9cd2004a19e84c637e5e5013f5
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
mkdir -p ./bisect
rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach d999d9b7e53b9a9cd2004a19e84c637e5e5013f5
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 69f517ac20566a645ff41a9bfca535822205a538
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/…
Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa…
Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tx1-gnu-master-aa…
Full commit (up to 1000 lines):
<cut>
commit d999d9b7e53b9a9cd2004a19e84c637e5e5013f5
Author: Patrick Palka <ppalka(a)redhat.com>
Date: Thu Jun 3 09:39:13 2021 -0400
c++: cv-qualified dependent name of alias tmpl [PR100592]
Here, the dependent template name in the return type of f() resolves to
an alias of int& after substitution, and we end up complaining about
qualifying this reference type with 'const' from cp_build_qualified_type
rather than just silently dropping the qualification as per [dcl.ref]/1.
The problem is ultimately that make_typename_type ignores the
tf_keep_type_decl flag when the dependent name is a template-id. This
in turn causes the TYPE_DECL check within tsubst <case TYPENAME_TYPE>
to fail, and so we end up not passing tf_ignore_bad_quals to
cp_build_qualified_type. This patch fixes this by making
make_typename_type respect the tf_keep_type_decl flag in this situation.
PR c++/100592
gcc/cp/ChangeLog:
* decl.c (make_typename_type): After calling
lookup_template_class, adjust the result to its TYPE_NAME and
then consider the tf_keep_type_decl flag.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/alias-decl-71.C: New test.
---
gcc/cp/decl.c | 13 +++++++++----
gcc/testsuite/g++.dg/cpp0x/alias-decl-71.C | 13 +++++++++++++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index fb21a3a1ae8..a3687dbb0dd 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -4136,10 +4136,15 @@ make_typename_type (tree context, tree name, enum tag_types tag_type,
return error_mark_node;
if (want_template)
- return lookup_template_class (t, TREE_OPERAND (fullname, 1),
- NULL_TREE, context,
- /*entering_scope=*/0,
- complain | tf_user);
+ {
+ t = lookup_template_class (t, TREE_OPERAND (fullname, 1),
+ NULL_TREE, context,
+ /*entering_scope=*/0,
+ complain | tf_user);
+ if (t == error_mark_node)
+ return error_mark_node;
+ t = TYPE_NAME (t);
+ }
if (DECL_ARTIFICIAL (t) || !(complain & tf_keep_type_decl))
t = TREE_TYPE (t);
diff --git a/gcc/testsuite/g++.dg/cpp0x/alias-decl-71.C b/gcc/testsuite/g++.dg/cpp0x/alias-decl-71.C
new file mode 100644
index 00000000000..6a61f93a0b0
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/alias-decl-71.C
@@ -0,0 +1,13 @@
+// PR c++/100592
+// { dg-do compile { target c++11 } }
+
+template<bool>
+struct meta {
+ template<class> using if_c = int&;
+};
+
+template<bool B>
+typename meta<B>::template if_c<void> const f();
+
+using type = decltype(f<true>());
+using type = int&;
</cut>
== This Week ==
* PR66791 (replace builtins with vector extensions in arm_neon.h intrinsics)
- vshl_n: Submitted patch for review and addressing comments by Richard.
- vmul_n fp: Investigated regression on arm-none-eabi and followed up
with Christophe.
- vmul_n int: Waiting for feedback.
- vld1: Created patch.
* Misc
- Fixed breakage in vect metric CI job due to type annotations.
* Off on thursday
- Public holiday
== Next Week ==
- Continue with PR66791
VirtIO Initiative ([STR-9])
===========================
VirtIO RPMB ([STR-5])
- posted [PATCH] virtio-rpmb: fix the description for multi-block
reads Message-Id: <20210722110903.8769-1-alex.bennee(a)linaro.org>
- Ruchika realised the spec didn't allow for multi-block reads
- she also suggested some [fixes for the C daemon]
- finally spent about 1/2 day on my [hacking branch] but making better
progress now trained ;-)
- create some sub-cards to track what we are doing
[STR-5] <https://projects.linaro.org/browse/STR-5>
[fixes for the C daemon]
<https://github.com/ruchi393/qemu/tree/vhost-user-rpmb-fixes>
[hacking branch] <https://github.com/stsquad/virtio-rpmb/tree/hacking>
QEMU Upstream Work ([UM-2])
===========================
- spent some time pulling together various maintainer trees for final
6.1 PRs
- hopefully [this is the last iteration before Monday]
- posted [PATCH for 6.1 v2 0/5] custom device configs Message-Id:
<20210707131744.26027-1-alex.bennee(a)linaro.org>
- chips away at the mega ARM re-factor patch set
- posted [PATCH v1 0/2] some device emulation documentation cleanup
Message-Id: <20210707184549.24436-1-alex.bennee(a)linaro.org>
- posted [PULL for 6.1 00/40] testing and plugin updates Message-Id:
<20210712122653.11354-1-alex.bennee(a)linaro.org>
- posted [PATCH for 6.1 v3 0/3] tricore fixes Message-Id:
<20210720114057.32053-1-alex.bennee(a)linaro.org>
- various iterations of review of rth's breakpoints
- posted [PULL for 6.1-rc1 00/28] doc, metadata, plugin and testing
updates Message-Id: <20210723170354.18975-1-alex.bennee(a)linaro.org>
[UM-2] <https://projects.linaro.org/browse/UM-2>
[this is the last iteration before Monday]
<https://patchew.org/QEMU/20210709143005.1554-1-alex.bennee@linaro.org/>
Enable plugins by default on TCG builds
- [X] clean-up testing matrix
Write a generic overview of vhost user usage for the manual
Other
=====
- preparing for [LOD discussion]
- some hackbox disk space admin
[LOD discussion]
<https://linaro.atlassian.net/wiki/spaces/LOD/pages/28544303418/2021-07-23+M…>
Completed Reviews [7/7]
=======================
[PATCH v6 0/4] GitLab Custom Runners and Jobs (was: QEMU Gating CI)
Message-Id: <20210608031425.833536-1-crosa(a)redhat.com>
[PATCH v4 00/22] tests/docker: start using libvirt-ci's "lcitool" for dockerfiles
Message-Id: <20210623142245.307776-1-berrange(a)redhat.com>
[PATCH v4 0/5] plugins: New TCG plugin for cache modelling
Message-Id: <20210623125458.450462-1-ma.mandourr(a)gmail.com>
[PATCH v3 0/2] execlog TCG plugin to log instructions
Message-Id: <20210702081307.1653644-1-erdnaxe(a)crans.org>
[PATCH 0/3] ci: use cirrus-run to utilize Cirrus CI from GitLab CI
Message-Id: <20210625172211.451010-1-berrange(a)redhat.com>
[PATCH v3 0/4] virtio: Add vhost-user based RNG
Message-Id: <20210710005929.1702431-1-mathieu.poirier(a)linaro.org>
[PATCH for-6.1 v6 00/17] tcg: breakpoint reorg
Message-Id: <20210720195439.626594-1-richard.henderson(a)linaro.org>
Absences
========
- several days of internet outages made things tricky
- July 26th-29th holiday
- On holiday for large chunks of August
Current Review Queue
====================
Needs reorganising ;-)
--
Alex Bennée
Progress:
* UM-2 [QEMU upstream maintainership]
+ Noticed we didn't enforce the M-profile "low 2 bits of SP are always 0"
rule, and wrote a patch to fix that
+ Found and fixed a handful of other corner-case M-profile bugs
+ Some minor docs improvements
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
+ Implemented the last 4 instruction patterns (VCVT, VRINT), bringing
us to Progress: 210/210 (100%)
+ Found and fixed a few bugs in already-implemented instructions
+ Started looking at how to make the MVE loads/stores correctly
raise alignment faults for unaligned addresses (this runs into
problems because QEMU doesn't currently have a good API for doing
the load/store the way we want to do it and also handling alignment
faults)
+ Remaining TODO list for this task:
- alignment fault behaviour, if not too difficult
- report MVE registers via the gdbstub (pending on the XML format being
fixed by gdb upstream)
- send out patches for code review
-- PMM
Successfully identified regression in *gcc* in CI configuration tcwg_bmk_llvm_tk1/llvm-master-arm-spec2k6-O3_LTO. So far, this commit has regressed CI configurations:
- tcwg_bmk_llvm_tk1/llvm-master-arm-spec2k6-O3_LTO
Culprit:
<cut>
commit c77230856eac2d28eb7bf10985846885c3c8727b
Author: Iain Buclaw <ibuclaw(a)gdcproject.org>
Date: Sat Jul 3 00:13:29 2021 +0200
d: RHS value lost when a target_expr modifies LHS in a cond_expr
To prevent the RHS of an assignment modifying the LHS before the
assignment proper, a target_expr is forced so that function calls that
return with slot optimization modify the temporary instead. This did
not work for conditional expressions however, to give one example. So
now the RHS is always forced to a temporary.
PR d/101282
gcc/d/ChangeLog:
* d-codegen.cc (build_assign): Force target_expr on RHS for non-POD
assignment expressions.
gcc/testsuite/ChangeLog:
* gdc.dg/torture/pr101282.d: New test.
</cut>
Results regressed to (for first_bad == c77230856eac2d28eb7bf10985846885c3c8727b)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -O3_LTO_marm -- artifacts/build-c77230856eac2d28eb7bf10985846885c3c8727b/results_id:
1
# 447.dealII,dealII_base.default regressed by 103
from (for last_good == 6feb628a706e86eb3f303aff388c74bdb29e7381)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -O3_LTO_marm -- artifacts/build-6feb628a706e86eb3f303aff388c74bdb29e7381/results_id:
1
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Results ID of last_good: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-master-arm-spec2k6-O3_LTO/1951
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Results ID of first_bad: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-master-arm-spec2k6-O3_LTO/1938
Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Configuration details:
Reproduce builds:
<cut>
mkdir investigate-gcc-c77230856eac2d28eb7bf10985846885c3c8727b
cd investigate-gcc-c77230856eac2d28eb7bf10985846885c3c8727b
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
rsync -a --del --delete-excluded --exclude bisect/ --exclude artifacts/ --exclude gcc/ ./ ./bisect/baseline/
cd gcc
# Reproduce first_bad build
git checkout --detach c77230856eac2d28eb7bf10985846885c3c8727b
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 6feb628a706e86eb3f303aff388c74bdb29e7381
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/…
Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Build log: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Full commit (up to 1000 lines):
<cut>
commit c77230856eac2d28eb7bf10985846885c3c8727b
Author: Iain Buclaw <ibuclaw(a)gdcproject.org>
Date: Sat Jul 3 00:13:29 2021 +0200
d: RHS value lost when a target_expr modifies LHS in a cond_expr
To prevent the RHS of an assignment modifying the LHS before the
assignment proper, a target_expr is forced so that function calls that
return with slot optimization modify the temporary instead. This did
not work for conditional expressions however, to give one example. So
now the RHS is always forced to a temporary.
PR d/101282
gcc/d/ChangeLog:
* d-codegen.cc (build_assign): Force target_expr on RHS for non-POD
assignment expressions.
gcc/testsuite/ChangeLog:
* gdc.dg/torture/pr101282.d: New test.
---
gcc/d/d-codegen.cc | 7 +++++++
gcc/testsuite/gdc.dg/torture/pr101282.d | 23 +++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/gcc/d/d-codegen.cc b/gcc/d/d-codegen.cc
index 9a9447371aa..ce7c17baaaf 100644
--- a/gcc/d/d-codegen.cc
+++ b/gcc/d/d-codegen.cc
@@ -1344,6 +1344,13 @@ build_assign (tree_code code, tree lhs, tree rhs)
d_mark_addressable (lhs);
CALL_EXPR_RETURN_SLOT_OPT (rhs) = true;
}
+ /* If modifying an LHS whose type is marked TREE_ADDRESSABLE. */
+ else if (code == MODIFY_EXPR && TREE_ADDRESSABLE (TREE_TYPE (lhs))
+ && TREE_SIDE_EFFECTS (rhs) && TREE_CODE (rhs) != TARGET_EXPR)
+ {
+ /* LHS may be referenced by the RHS expression, so force a temporary. */
+ rhs = force_target_expr (rhs);
+ }
/* The LHS assignment replaces the temporary in TARGET_EXPR_SLOT. */
if (TREE_CODE (rhs) == TARGET_EXPR)
diff --git a/gcc/testsuite/gdc.dg/torture/pr101282.d b/gcc/testsuite/gdc.dg/torture/pr101282.d
new file mode 100644
index 00000000000..b75d5fc678f
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/torture/pr101282.d
@@ -0,0 +1,23 @@
+// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101282
+// { dg-do run }
+
+void main()
+{
+ struct S101282
+ {
+ int impl;
+ S101282 opUnary(string op : "-")()
+ {
+ return S101282(-impl);
+ }
+ int opCmp(int i)
+ {
+ return (impl < i) ? -1 : (impl > i) ? 1 : 0;
+ }
+ }
+ auto a = S101282(120);
+ a = -a;
+ assert(a.impl == -120);
+ a = a >= 0 ? a : -a;
+ assert(a.impl == 120);
+}
</cut>
Successfully identified regression in *llvm* in CI configuration tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-Os. So far, this commit has regressed CI configurations:
- tcwg_bmk_llvm_tk1/llvm-release-arm-spec2k6-Os
Culprit:
<cut>
commit ab97c9bdb747c873cd35a18229e2694156a7607d
Author: David Green <david.green(a)arm.com>
Date: Sat Dec 12 14:21:40 2020 +0000
[LV] Fix scalar cost for tail predicated loops
When it comes to the scalar cost of any predicated block, the loop
vectorizer by default regards this predication as a sign that it is
looking at an if-conversion and divides the scalar cost of the block by
2, assuming it would only be executed half the time. This however makes
no sense if the predication has been introduced to tail predicate the
loop.
Original patch by Anna Welker
Differential Revision: https://reviews.llvm.org/D86452
</cut>
Results regressed to (for first_bad == ab97c9bdb747c873cd35a18229e2694156a7607d)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -Os_mthumb -- artifacts/build-ab97c9bdb747c873cd35a18229e2694156a7607d/results_id:
1
# 401.bzip2,bzip2_base.default regressed by 103
# 401.bzip2,[.] BZ2_compressBlock regressed by 113
# 473.astar,astar_base.default regressed by 103
from (for last_good == d716eab197abec0b9aab4a76cd1a52b248b8c3b1)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -Os_mthumb -- artifacts/build-d716eab197abec0b9aab4a76cd1a52b248b8c3b1/results_id:
1
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release…
Results ID of last_good: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-release-arm-spec2k6-Os/1878
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release…
Results ID of first_bad: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-release-arm-spec2k6-Os/1876
Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release…
Configuration details:
Reproduce builds:
<cut>
mkdir investigate-llvm-ab97c9bdb747c873cd35a18229e2694156a7607d
cd investigate-llvm-ab97c9bdb747c873cd35a18229e2694156a7607d
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
rsync -a --del --delete-excluded --exclude bisect/ --exclude artifacts/ --exclude llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach ab97c9bdb747c873cd35a18229e2694156a7607d
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach d716eab197abec0b9aab4a76cd1a52b248b8c3b1
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/…
Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release…
Build log: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-release…
Full commit (up to 1000 lines):
<cut>
commit ab97c9bdb747c873cd35a18229e2694156a7607d
Author: David Green <david.green(a)arm.com>
Date: Sat Dec 12 14:21:40 2020 +0000
[LV] Fix scalar cost for tail predicated loops
When it comes to the scalar cost of any predicated block, the loop
vectorizer by default regards this predication as a sign that it is
looking at an if-conversion and divides the scalar cost of the block by
2, assuming it would only be executed half the time. This however makes
no sense if the predication has been introduced to tail predicate the
loop.
Original patch by Anna Welker
Differential Revision: https://reviews.llvm.org/D86452
---
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 7 ++++---
llvm/test/Transforms/LoopVectorize/ARM/scalar-block-cost.ll | 2 +-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index c381377b67c9..663ea50c4c02 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -6483,9 +6483,10 @@ LoopVectorizationCostModel::expectedCost(ElementCount VF) {
// if-converted. This means that the block's instructions (aside from
// stores and instructions that may divide by zero) will now be
// unconditionally executed. For the scalar case, we may not always execute
- // the predicated block. Thus, scale the block's cost by the probability of
- // executing it.
- if (VF.isScalar() && blockNeedsPredication(BB))
+ // the predicated block, if it is an if-else block. Thus, scale the block's
+ // cost by the probability of executing it. blockNeedsPredication from
+ // Legal is used so as to not include all blocks in tail folded loops.
+ if (VF.isScalar() && Legal->blockNeedsPredication(BB))
BlockCost.first /= getReciprocalPredBlockProb();
Cost.first += BlockCost.first;
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/scalar-block-cost.ll b/llvm/test/Transforms/LoopVectorize/ARM/scalar-block-cost.ll
index 959fbe676e67..fc8ea4fc938c 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/scalar-block-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/scalar-block-cost.ll
@@ -15,7 +15,7 @@ define void @pred_loop(i32* %off, i32* %data, i32* %dst, i32 %n) #0 {
; CHECK-COST-NEXT: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %add1, i32* %arrayidx2, align 4
; CHECK-COST-NEXT: LV: Found an estimated cost of 1 for VF 1 For instruction: %exitcond.not = icmp eq i32 %add, %n
; CHECK-COST-NEXT: LV: Found an estimated cost of 0 for VF 1 For instruction: br i1 %exitcond.not, label %exit.loopexit, label %for.body
-; CHECK-COST-NEXT: LV: Scalar loop costs: 2.
+; CHECK-COST-NEXT: LV: Scalar loop costs: 5.
entry:
%cmp8 = icmp sgt i32 %n, 0
</cut>
Successfully identified regression in *llvm* in CI configuration tcwg_bmk_llvm_tk1/llvm-master-arm-spec2k6-O2. So far, this commit has regressed CI configurations:
- tcwg_bmk_llvm_tk1/llvm-master-arm-spec2k6-O2
Culprit:
<cut>
commit d181fd918d18cbd99768f025e14a69d35d275f14
Author: Simon Pilgrim <llvm-dev(a)redking.me.uk>
Date: Fri Jul 2 14:27:27 2021 +0100
[CostModel][X86] Drop some hard coded fp<->int scalarization costs
Scalarization costs handling is a lot better now, and the hard coded costs were higher than the worse case numbers from the script in D103695
</cut>
Results regressed to (for first_bad == d181fd918d18cbd99768f025e14a69d35d275f14)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -O2_marm -- artifacts/build-d181fd918d18cbd99768f025e14a69d35d275f14/results_id:
1
# 400.perlbench,libc-2.33.9000.so regressed by 113
from (for last_good == 5df556ac8bb8c5f4ef3dff1a2039dd389d1d27c0)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -O2_marm -- artifacts/build-5df556ac8bb8c5f4ef3dff1a2039dd389d1d27c0/results_id:
1
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Results ID of last_good: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-master-arm-spec2k6-O2/1840
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Results ID of first_bad: tk1_32/tcwg_bmk_llvm_tk1/bisect-llvm-master-arm-spec2k6-O2/1837
Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Configuration details:
Reproduce builds:
<cut>
mkdir investigate-llvm-d181fd918d18cbd99768f025e14a69d35d275f14
cd investigate-llvm-d181fd918d18cbd99768f025e14a69d35d275f14
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
rsync -a --del --delete-excluded --exclude bisect/ --exclude artifacts/ --exclude llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach d181fd918d18cbd99768f025e14a69d35d275f14
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 5df556ac8bb8c5f4ef3dff1a2039dd389d1d27c0
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/…
Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Build log: https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tk1-llvm-master-…
Full commit (up to 1000 lines):
<cut>
commit d181fd918d18cbd99768f025e14a69d35d275f14
Author: Simon Pilgrim <llvm-dev(a)redking.me.uk>
Date: Fri Jul 2 14:27:27 2021 +0100
[CostModel][X86] Drop some hard coded fp<->int scalarization costs
Scalarization costs handling is a lot better now, and the hard coded costs were higher than the worse case numbers from the script in D103695
---
llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 13 -------------
llvm/test/Analysis/CostModel/X86/sitofp.ll | 6 +++---
2 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index d55cd8a8c7a8..9eb5abe4dd9b 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -1977,13 +1977,6 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
{ ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 },
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 },
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 },
- // The generic code to compute the scalar overhead is currently broken.
- // Workaround this limitation by estimating the scalarization overhead
- // here. We have roughly 10 instructions per scalar element.
- // Multiply that by the vector width.
- // FIXME: remove that when PR19268 is fixed.
- { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
- { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 },
{ ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 },
{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 },
@@ -2003,12 +1996,6 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
{ ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 },
{ ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 9 },
{ ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 19 },
- // This node is expanded into scalarized operations but BasicTTI is overly
- // optimistic estimating its cost. It computes 3 per element (one
- // vector-extract, one scalar conversion and one vector-insert). The
- // problem is that the inserts form a read-modify-write chain so latency
- // should be factored in too. Inflating the cost per element by 1.
- { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
{ ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 },
{ ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },
diff --git a/llvm/test/Analysis/CostModel/X86/sitofp.ll b/llvm/test/Analysis/CostModel/X86/sitofp.ll
index b3c400c93b9f..b327454c1d09 100644
--- a/llvm/test/Analysis/CostModel/X86/sitofp.ll
+++ b/llvm/test/Analysis/CostModel/X86/sitofp.ll
@@ -122,14 +122,14 @@ define i32 @sitofp_i64_double() {
; AVX-LABEL: 'sitofp_i64_double'
; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cvt_i64_f64 = sitofp i64 undef to double
; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %cvt_v2i64_v2f64 = sitofp <2 x i64> undef to <2 x double>
-; AVX-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %cvt_v4i64_v4f64 = sitofp <4 x i64> undef to <4 x double>
-; AVX-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %cvt_v8i64_v8f64 = sitofp <8 x i64> undef to <8 x double>
+; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %cvt_v4i64_v4f64 = sitofp <4 x i64> undef to <4 x double>
+; AVX-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %cvt_v8i64_v8f64 = sitofp <8 x i64> undef to <8 x double>
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512F-LABEL: 'sitofp_i64_double'
; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %cvt_i64_f64 = sitofp i64 undef to double
; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %cvt_v2i64_v2f64 = sitofp <2 x i64> undef to <2 x double>
-; AVX512F-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %cvt_v4i64_v4f64 = sitofp <4 x i64> undef to <4 x double>
+; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %cvt_v4i64_v4f64 = sitofp <4 x i64> undef to <4 x double>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %cvt_v8i64_v8f64 = sitofp <8 x i64> undef to <8 x double>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
</cut>
All,
During Connect the suggestion was made that each working group should have
its own IRC Channel for discussions and topics relating to the group in
particular (as opposed to #linaro which is 'generic' Linaro conversations).
Therefore I have just set up #linaro-tcwg on Freenode for the Toolchain
Working Group.
This channel is public and open to anyone who wants to talk with the TCWG
group about anything toolchain related.
Thanks,
Matt
--
Matthew Gretton-Dann
Toolchain Working Group, Linaro
Progress:
* UM-2 [QEMU upstream maintainership]
+ Code review:
- ITS patchset v6
- RTH's series to allow usermode emulation users to set default vector length
+ Arm pullreq; shepherding stuff in for softfreeze
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
+ Sent out patchset with the 3rd slice of MVE insns; I now have
all the non-floating-point insns done, I think. New insns:
scatter-gather loads/stores, interleaving loads/stores, VCTP,
realized I already did VMOVL as it is "VSHLL-by-0"
+ Implemented most of the floating point insns: implemented
VADD fp, VSUB fp, VABD fp, VMUL fp, VMAXNM, VMINNM, VCADD fp,
VFMA, VFMS, VCMUL, VCMLA, VMAXNMA, VMINNMA, VADD fp scalar,
VSUB fp scalar, VMUL fp scalar, VFMA fp scalar, VFMAS fp scalar,
VMAXNMV, VMAXNMAV, VMINNMV, VMINNMAV, VCMP and VPT fp vector and scalar,
VCVT fixed-point
+ Just 4 insns to go: three flavours of VCVT, plus VRINT (and then
all the other stuff that wasn't included in this simplistic
measure of progress :-))
+ Progress: 206/210 (98%)
-- PMM
Successfully identified regression in *gcc* in CI configuration tcwg_bmk_gnu_tk1/gnu-release-arm-spec2k6-O3_LTO. So far, this commit has regressed CI configurations:
- tcwg_bmk_gnu_tk1/gnu-release-arm-spec2k6-O3_LTO
Culprit:
<cut>
commit c7207339a7dbce5b68f872064e624dcf1639ba46
Author: Wilco Dijkstra <wdijkstr(a)arm.com>
Date: Mon Oct 14 12:21:14 2019 +0000
[ARM] Switch to default sched pressure algorithm
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. Building SPEC2006 showed significant codesize gains
with the default pressure algorithm, so switch back to that. PR77308 shows
~800 fewer instructions.
SPECINT2006 is ~0.6% faster on Cortex-A57 together with the other DImode
patches. Overall SPEC codesize is 1.1% smaller.
gcc/
* config/arm/arm.c (arm_option_override): Don't override sched
pressure algorithm.
From-SVN: r276960
</cut>
Results regressed to (for first_bad == c7207339a7dbce5b68f872064e624dcf1639ba46)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-5
# true:
0
# benchmark -O3_LTO_marm -- artifacts/build-c7207339a7dbce5b68f872064e624dcf1639ba46/results_id:
1
# 410.bwaves,bwaves_base.default regressed by 108
# 454.calculix,calculix_base.default regressed by 105
# 482.sphinx3,sphinx_livepretend_base.default regressed by 104
# 436.cactusADM,cactusADM_base.default regressed by 116
# 444.namd,namd_base.default regressed by 103
# 435.gromacs,gromacs_base.default regressed by 106
from (for last_good == 7bd8bec53f0e43c7a7852c54650746e65324514b)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--with-mode=arm --set gcc_override_configure=--disable-libsanitizer:
-5
# true:
0
# benchmark -O3_LTO_marm -- artifacts/build-7bd8bec53f0e43c7a7852c54650746e65324514b/results_id:
1
Artifacts of last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a…
Results ID of last_good: tk1_32/tcwg_bmk_gnu_tk1/bisect-gnu-release-arm-spec2k6-O3_LTO/1468
Artifacts of first_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a…
Results ID of first_bad: tk1_32/tcwg_bmk_gnu_tk1/bisect-gnu-release-arm-spec2k6-O3_LTO/1469
Build top page/logs: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a…
Configuration details:
Reproduce builds:
<cut>
mkdir investigate-gcc-c7207339a7dbce5b68f872064e624dcf1639ba46
cd investigate-gcc-c7207339a7dbce5b68f872064e624dcf1639ba46
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… --fail
curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… --fail
curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a… --fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
cd gcc
# Reproduce first_bad build
git checkout --detach c7207339a7dbce5b68f872064e624dcf1639ba46
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach 7bd8bec53f0e43c7a7852c54650746e65324514b
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results: https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/…
Artifacts: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a…
Build log: https://ci.linaro.org/job/tcwg_bmk_ci_gnu-bisect-tcwg_bmk_tk1-gnu-release-a…
Full commit (up to 1000 lines):
<cut>
commit c7207339a7dbce5b68f872064e624dcf1639ba46
Author: Wilco Dijkstra <wdijkstr(a)arm.com>
Date: Mon Oct 14 12:21:14 2019 +0000
[ARM] Switch to default sched pressure algorithm
Currently the Arm backend selects the alternative sched pressure algorithm.
The issue is that this doesn't take register pressure into account, and so
it causes significant additional spilling on Arm where there are only 14
allocatable registers. Building SPEC2006 showed significant codesize gains
with the default pressure algorithm, so switch back to that. PR77308 shows
~800 fewer instructions.
SPECINT2006 is ~0.6% faster on Cortex-A57 together with the other DImode
patches. Overall SPEC codesize is 1.1% smaller.
gcc/
* config/arm/arm.c (arm_option_override): Don't override sched
pressure algorithm.
From-SVN: r276960
---
gcc/ChangeLog | 5 +++++
gcc/config/arm/arm.c | 5 -----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c2cbd4274ca..f07a0e61e6b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-10-14 Wilco Dijkstra <wdijkstr(a)arm.com>
+
+ * config/arm/arm.c (arm_option_override): Don't override sched
+ pressure algorithm.
+
2019-10-14 Richard Biener <rguenther(a)suse.de>
PR tree-optimization/92069
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 39e1a1ef9a2..394b1dd1902 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3555,11 +3555,6 @@ arm_option_override (void)
global_options.x_param_values,
global_options_set.x_param_values);
- /* Use the alternative scheduling-pressure algorithm by default. */
- maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PRESSURE_MODEL,
- global_options.x_param_values,
- global_options_set.x_param_values);
-
/* Look through ready list and all of queue for instructions
relevant for L2 auto-prefetcher. */
int param_sched_autopref_queue_depth;
</cut>