== Progress ==
* TCWG-1205 - Minor tweaks to Jenkins LLVM jobs [1/10]
- Sent a few patches to make the Jenkins jobs more friendly and/or
fix them for new changes in the upstream release script
* TCWG-1206 - Investigate timeouts on buildbots [1/10]
- Had some mysterious timeouts on some of the buildbots
- Didn't manage to reproduce, will keep an eye out in case it happens again
* TCWG-1199, 1200 - LLVM 5.0.0 for ARM and AArch64 [1/10]
- RC1 is out, there are some failures in some libunwind and
sanitizer tests; reported upstream
* TCWG-1194 - [ARM GlobalISel] Support simple, static globals [4/10]
- Committed some simple stuff and sent a patch for upstream review
* TCWG-1209 - [MIR] Print ARM constant pools [1/10]
- Printing target-specific constant pools is trivial, but testing is
a bit problematic
- All current MIR tests read in and then print out the same MIR,
which means that we'd have to add support for target-specific constant
pools in the parser as well
- This is complicated by the fact that at a first glance the parser
doesn't seem to handle any other target-specific stuff and I'm not
sure it's ok to pull ARMConstantPool into it
* Misc [2/10]
- Mailing lists, code reviews, meetings
== Plan ==
* Figure out what to do about TCWG-1209
* More code reviews and global isel
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [1/10]
Commit one patch of v3. No review comments. Usually it means I don't
review patches, so other people don't review my patches.
* PR 21555. [3/10]
Think it again, and fix it with a better approach. Patches are posted.
* PR 21717. [2/10]
Fix a bug on getting/setting FPSCR on VFPv2. I am surprised that we don't
find it before. Testing patches.
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [1/10]
Blocked by OpenOCD bugs. Chat with OpenOCD maintainer to make sure
these bugs are opened in the right place.
* TCWG-561, [3/10]
I finish the patches, but not confident because I use copy-and-swap idiom
for the first time. Need more time to bake it, write unit tests, etc. Maybe,
still need to read "More effective C++" further.
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards.
Blocked by OpenOCD bugs. Chat with OpenOCD maintainer to make sure
these bugs are opened in the right place. Matthew (who contributed OpenOCD
AArch64) pinged me on irc, but he lost connection immediately. Probably, he
contact me for the OpenOCD bugs.
* Think about presenting GDB target description work in Linaro SFO17,
may add some SVE stuff if possible, to make it more attractive.
# Plan #
* TCWG-1159,
* PR 21717, 21555,
* TCWG-561,
* Register the presentation for Linaro SFO17,
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Support globals [6/10]
- This is going to be very hairy because of all the different
relocation models (PIC, ROPI etc), differences between ELF and MachO,
and differences between targets with MOVT or without it
- Started adding support for simple, statically linked globals, it
might take me a while to get all the pseudoinstructions right even for
this simple case
* Misc [4/10]
- Meetings, mailing lists, code reviews, buildbots
== Plan ==
* More GlobalISel
* More code reviews
== Progress ==
* Infrastructure/validation:
- minor fixes in the release jobs
* Benchmarking:
- fixes on reporting scripts
- using more iterations didn't produce more stable results (still noise)
- trying to reboot the boards before running the benchs
* GCC upstream validation:
- further reduced noise ("random" pass/failures)
- sent a patch to fix an aarch64 problem with -mstrict-align
* misc (conf-calls, meetings, emails, ....)
== Next ==
Holidays until August 21st
[TCWG-614] Range Thunks
Finally managed to get some review on the entirety of the Range Thunks
patches. Have reorganised the patches and wrote some documentation to
make it easier to review. Responded to all review comments so far.
Compiler-rt
A long tail of frustration.
Managed to get a hello world semi-hosting test case running on the
latest QEMU running newlib-nano. This was much more difficult than I
expected due to:
- The semihosting startup code of newlib does a semi-hosting call for
top of memory regardless of whether the heap and stack location have
been identified in a linker-script.
- The QEMU semihosting response to top of memory is not helpful
leaving the stack location in an invalid memory location (latest QEMU
requires emulation of a board and not a generic machine)
- QEMU doesn't data-abort when writing to a stack location, so my
return address is helpfully read back as 0x0
Worked around by providing a large enough memory size to QEMU that the
semihosting call for top of memory returns 0, allowing newlib to use
the values in the linker script. Will probably need to spend some time
to write my own startup code that just uses the linker script for the
heap and stack.
Building compiler-rt for v6-m and v7-m has been much more difficult
than I expected as well. I've managed to find a configuration that
works, although it relies on some experimental work in moving
compiler-rt to the runtimes directory.
Plans for next week:
- LLD is top priority
- Get testing for compiler-rt working via qemu on v7-m, the recipe
that works for build does not support testing. I've got to either
extract the cmake magic flags or find a way to plumb through the runes
that make the tests work to the recipe I've got.
- On holiday Thursday, Friday and the following Monday
* Short week (Friday off)
== Progress ==
* Infrastructure/validation:
* Benchmarking:
- production scripts are now up-to-date, still observing noise on
some benchmarks
- fixed a couple of small issues with the scripts
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported/fixed a few regressions
- committed testsuite patch with de-require-stack-check
- looking at a problem with unaligned accesses
* misc (conf-calls, meetings, emails, ....)
== This Week ==
* PR78736 (2/10)
- Submitted patch upstream
* type-promotion (3/10)
- Scheduling path-splitting before type-promotion fixes the regression
with path-split-1.c
- Created patch to fix issues with type-promotion interfering with
widening_mul and bswap
optimizations
* malloc-propagation (4/10)
- Updated patch, passes bootstrap+test on x86_64
- Working through ICE's with lto-bootstrap
* Misc (1/10)
- Meetings
== Progress ==
* TCWG-1187 - [ARM GlobalISel] Support G_FCMP for s64 [5/10]
- Committed upstream
- Also refactored the existing code a bit
* TCWG-1190 - [ARM GlobalISel] Support G_BR and G_BRCOND [2/10]
- Committed upstream
* TCWG-1191 - Test zorg patch [1/10]
- Test a patch for running the test-suite with the CMake producer on
the buildbots
* Misc [3/10]
- Meetings, mailing lists, code reviews, buildbots
== Plan ==
* More GlobalISel
* More code reviews
# Progress #
* TCWG-1159,New design of GDB/GDBserver target description. [2/10]
v3 are posted, after fixing some regressions introduced by improper
merge. No comments from upstream yet.
* PR 21555. [2/10]
Has already a fix, but I am not satisfied. Post an RFC for a
discussion in general. My fix is to fix each GDB backend one by one,
while my RFC is about fixing it in GDB core side.
* TCWG-1162, Test GDB+OpenOCD with AArch64 boards. [4/10]
OpenOCD doesn't support semi-hosting, so I pass --specs=nosys.specs to
aarch64-none-elf gcc, but linker can't find a symbol from newlib.
Looks nobody tests aarch64-none-elf gcc with --specs=nosys.specs
before. Hack in newlib here and there, and get compiler/linker happy.
I can download code to HiKey via OpenOCD, but "continue" becomes
"single step". Open two OpenOCD bugs upstream. My work is blocked by
OpenOCD bugs.
* Upstream patches review. [2/10]
** Review sparc64 adi patch v3,
** Investigate and review the patch fixing GDB crashes on amd64-linux,
** Review Alan H.'s patch, and discuss on the design,
** Some conversation with Maciej on MIPS16 and microMIPS disassembler,
because my disassembler rework breaks MIPS.
# Plan #
* PR 21555,
* TCWG-1159
* TCWG-561,
# Issue #
* TCWG-1162 is blocked by OpenOCD bugs.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.07
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.1+svn250046 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.08 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.1+svn250046
* Backport of [Bugfix] [AArch32] PR target/71778 ICE using
non-constant argument to Neon intrinsic that requires constant
arguments
* Backport of [Bugfix] [AArch64] PR target/71663 aarch64 Vector
initialization can be improved slightly
* Backport of [AArch32] Enable FP16 vector arithmetic operations
* Backport of [AArch32] Fix ARM bootstrap failure due to an odd warning
* Backport of [AArch32] Modify idiv costs for Cortex-A53
* Backport of [AArch64] Add combine pattern for storing lane zero of a vector
* Backport of [AArch64] Add HF vector modes to lane-to-lane INS pattern
* Backport of [AArch64] Add prefetch configuration to aarch64 backend
* Backport of [AArch64] Adjust costs so udiv is preferred over sdiv
when both are valid
* Backport of [AArch64] Allow CMP+SHIFT when comparing with zero
* Backport of [AArch64] Allow const0_rtx operand for atomic
compare-exchange patterns
* Backport of [AArch64] Emit tighter strong atomic compare-exchange
loop when comparing against zero
* Backport of [AArch64] Enable -fprefetch-loop-arrays at given
optimization level
* Backport of [AArch64] Fix -fstack-check with really big frames on aarch64
* Backport of [AArch64] Fix subreg bug in scalar copysign
* Backport of [AArch64] Peephole for SUBS
* Backport of [AArch64] Simplify call, call_value, sibcall,
sibcall_value patterns
* Backport of [AArch64] Update prefetch tuning parameters for qdf24xx.
* Backport of [AArch64] Use SUBS for parallel subtraction and
comparison with immediate
* Backport of [Misc] Add debug counter for loop array prefetching
* Backport of [Misc] Improve debug output of loop data prefetching
* Backport of [Cleanup] [AArch32] Complete legend for ARM register
allocation in arm.h
* Backport of [Cleanup] [AArch32] Fix comment for
cmse_nonsecure_call_clear_caller_saved
* Backport of [Cleanup] [AArch32] Fix typo in comment in arm_expand_prologue
* Backport of [Testsuite] [AArch32] Add MOVT testing for ARMv8-M Baseline
* Backport of [Testsuite] Add dg-require-stack-check
* Backport of [Testsuite] Fix stack-check-1.c
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn250045 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the 2017.08 stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn250045
* Linaro BZ #3040 -- CC1 and cc1plus cannot convert UTF-8: Regenerate
intl configure
* Backport of [AArch64] Fix -fstack-check with really big frames on aarch64
* Backport of [Testsuite] Add dg-require-stack-check
* Backport of [Testsuite] Fix stack-check-1.c
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Achievements:
Some progress on Range Thunks. [TCWG-614]
- I have all the enabling patches that allow assignAddresses() to be
run multiple times committed.
- Need review for the actual range thunks implementation itself.
Compiler-rt [TCWG-1156]
- Clang (as opposed to llvm) is assuming that all builtins for ARM are
mandated to have a soft-float interface. I have a tentative patch but
need to test it a bit more first.
- Found out a bit more about the structure of how compiler-rt, and why
it behaves differently when I use the default target and
auto-detection of toolkit as opposed to supplying the target via
options.
-- There is quite a bit of hidden magic and hacks going on in the
default case, some of it I don't think is quite right. For example
Compiler-rt seems to conflate architecture with abi.
Set myself the task of getting compiler-rt tests running on v6-m with
testing on qemu.
- v6-m is the only auto-detected default target that I haven't been
able to reproduce results on.
- A review claimed that tests had been run on qemu, and I'm now trying
to work out how to reproduce this with clang and an arm-none-eabi
sysroot.
-- Not having a lot of luck so far, latest qemu only supports
emulation of 2 cortex-m3 dev-boards and I have yet to make a
standalone program that works [*]
-- I'm not looking forward to plumbing in the options to make the
arm-none-eabi testing work.
[*] I thought I would try semi-hosting first, but it turns out the
default semihosting startup code supplied with arm-none-eabi replaces
my heap and stack locations with a semi-hosting call to get top of
memory which qemu gives an inappropriate result for a dev-board
emulation with non contiguous memory. Would like to see if I can get
this working via a quick experiment to rewrite the start-up code,
although for the full tests I may fall back to retargeting the IO via
an emulated serial port.
Plans:
- First priority is range thunks for lld
- Second priority is getting a v6m test of compiler-rt to check for
any latent problems
- Submit clang patch when I know it works for all the supported platforms
- Look into v7-m support, particularly v7-m + single precision floating point.
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [7/10]
It takes me a lot of time making the patch series v3 work, to address
review comments, to fix regressions, and to make sure each commit
doesn't break build. Almost done.
Looks 30 patches in one series is my limit, and wonder how does other
people manage large patch series.
* Help people runing GDB tests, and get some fails. It turns out we
encounter PR 21555. [1/10]
* Misc, [2/10]
# Plan #
* TCWG-1159
* PR 21555
* TCWG-561,
--
Yao Qi
== This Week ==
* PR78736 (4/10)
- Improved patch to not warn for enums with equal value ranges
- Caused fallouts in libgomp and libgfortran
- Large kernel fallout!
* type promotion (5/10)
- Looking at interference between path-splitting and type-promotion
optimizations
- miscompilation of memcpy-bi.c on
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
== Progress ==
* Infrastructure/validation:
- abe patch for bug #3040 committed, now we need to fix
regression-detection because it builds a toolchain that does not
support this fix (lacks a gcc patch)
- upgrade of dejagnu used for binutils validation fixed the random
errors we were seeing
* Benchmarking:
- production scripts were not up-to-date, but the new ones have a
conflict/dependency on ntp
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported/fixed a few regressions
- committed testsuite patch with de-require-stack-check
* misc (conf-calls, meetings, emails, ....)
== Progress ==
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- The bot is finally upstream and working well
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP for s32 [7/10]
- Committed support for 32-bit floating point compares, both
hardware and software
* TCWG-1141 - Add "push" capability [1/10]
- Finally committed llvm-push
* Misc [1/10]
- Mailing lists, meetings, buildbots
== Plan ==
* TCWG-1187 - [ARM GlobalISel] Support G_FCMP for s64
== Activity ==
- Rebased and posted for review all my range-thunks work for LLD as
there had been some interest from some individuals on IRC in trying
out the patch.
-- Seems to work for them
-- Hoped that this might provoke upstream into looking and reviewing
the patches but no such luck.
- Landed the patch that sets _GLOBAL_OFFSET_TABLE_ so that FreeBSD can
link on ARM
- Some other small lld patches
- Investigations into whether an X86 patch might affect CFI generation
for AArch64.
Spent some time banging my head against the compiler-rt build system
to try and see if I can get a cross-compiled build and test run on
Qemu when my compiler-rt target != the default target (i.e. I want to
build clang with ARM and AArch64 targets and cross-build and test all
the ARM compiler-rt targets from that)
- Thwarted by what seems to be inconsistent decisions about
auto-detection of options, what is an architecture, target, sub-target
and abi.
- By passing in all auto-generated options by steam I'm still hitting
some problems with some tests that have an external assembly file.
Found numerous other small inconsistencies that I'll need to write up.
== Plans ==
- Ping the Range Thunks reviews again.
- Compiler-rt
Aim to get to the point where I can write a coherent mail to llvm-dev
explaining what I think is wrong and what I think needs changing.
== Progress ==
o Linaro GCC/Validation (7/10)
* Fixed AArch64 GCC options documentation
ARM part clean-up on-going
* libgomp/mingw patch: Upstream review pending
* pc-relative-literal-loads patch for GCC 6 branch: Upstream review pending
reviewed fxi for trunk.
* Following upstream discussions on stack clash CVE:
- One AArch64 specific commit done (backport in our branch on-going)
- Fix still under discussion upstream, nothing committed yet
* catching-up with re-association work
* libunwind support
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o backports for 2017.07, CVE, ...
== This Week ==
* Type promotion (6/10)
- Created patch to fix ICE with pr81083.c on ppc64
- Investigated mis-compilation of memcpy-bi.c on ppc64
* Malloc propagation (1/10)
- Working on patch based on feedback received.
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Type promotion: Look at miscompilation bug, and investigate
performance regression for path
splitting optimization
- Malloc propagation
== Progress ==
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- Moved to the public silent master, ready for the final move on
Monday if it's stable until then
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [5/10]
- Most of the functionality is implemented, but I intend to do a lot
of refactoring before committing
* TCWG-1174 - [ARM GlobalISel] Support G_SELECT [1/10]
- Committed upstream
* Misc [3/10]
- Mailing lists, buildbots, discussions
== Plan ==
* Wrap up TCWG-1172
* More GlobalISel
* More code reviews
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [4/10]
People agree on the direction this patch series goes to! Still
need to polish v3.
Started to write v3 to address comments, split patches, and rebase
patches, etc...
My Cauldron talk "A flexible GDB target
description for processor diversity " is registered.
* TCWG-561, Handle unavailable memory during frame unwinding. [2/10]
Decided how to do it, coding.
* Investigate the usage of obstack in GNU toolchain. [1/10]
We recently add a convenient class wrapper for obstack in GDB, and
I think it is better to "upstream" it to inlcude/ so that GCC can use
it as well. Did some archeology on C++ transition in GCC, find some
difficulties. Still good to know some GCC maintainers' preference on
C++.
* Travel, [1/10]
** US EVUS enrollment, to update my US visa information.
** Figure out the Cauldron flight.
* Misc, meeting, [2/10].
# Plan #
* TCWG-1159, patch v3.
--
Yao Qi
== Progress ==
* Infrastructure/validation:
- iterated on patch for bug #3040: 1 abe patch to use libiconv, 1
linaro-gcc-6 patch (partial backport to make enable-nls and libiconv
work together)
* Benchmarking:
- noticed large differences in bench results from one run to another
while looking at "deprecated it block" patch
- trying less aggressive configuration
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported/fixed a few regressions
- committed testsuite patch (for arm-neon flags)
* misc (conf-calls, meetings, emails, ....)
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [3/10]
Update patches to address review comments. Commit three patches.
Need to post V3.
* TCWG-561, Handle unavailable memory during frame unwinding. [2/10]
Think about the plan.
* Upstream patches review. [3/10]
** Review IBM kernel-awareness patches.
** Review sparc64 adi patch.
** Review Alan's patch on removing MAX_REGISTER_SIZE. Evaluate other
better but expensive approach.
* Misc, [2/10]
Write a STL container allocator which uses stack instead of heap.
Underestimate the complexity of C++. Need to replace some std::vector
with my vector with stack_allocator in GDB. It should be also useful
to Alan.
# Plan #
* TCWG-1159, send v3.
* TCWG-561, Handle unavailable memory during frame unwinding.
--
Yao Qi
[TCWG-614] Range extension thunks
- No progress on upstream reviews from maintainers this week
I have received some interest on IRC and on at least one of the
reviews from other people wanting the feature so I'm hoping that this
may speed up the process.
- I've committed to rebasing and posting the full patch-set for review
so that interested people can take it and test.
PR31159 Tracked down why LLD wasn't correctly linking ARM BSD port
- lld only provides a dummy absolute value for _GLOBAL_OFFSET_TABLE_
- llvm-mc doesn't transform .word _GLOBAL_OFFSET_TABLE_ - . into
R_ARM_BASE_PREL like GNU as does, this relocation doesn't use the
value of _GLOBAL_OFFSET_TABLE_ . Instead we get R_ARM_REL32 which
needs _GLOBAL_OFFSET_TABLE_ to be set correctly. PR335511
- Patch accepted upstream will commit today
Misc:
- lld consultancy for Android
- Help to fix build error on clang for ARM colleague
- Query on lld behaviour with respect to .ARM.extab, I think lld
behaviour is within spec, but it may be producing larger files so
probably enough to argue the case for a small patch.
-No time to spend on compiler-rt this week
Plans:
- Post all the range-thunk patches for the people interested in it.
- Commit patches accepted last week
== Progress ==
* Out of office on Friday [2/10]
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- Committed a quick fix and started seeing green builds on this, we
can probably move it upstream soon
* TCWG-836 - Replace D01s by Scaleway boards [2/10]
- Set up a selfhost buildbot on one of the Scaleway boards
- It is very, very slow, I did some performance experiments but
there's probably more that can be attempted here
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP [2/10]
- The hard float part is implemented, fiddling with the soft float now
- Forked some of that work into a different story for supporting G_SELECT
* TCWG-1174 - [ARM GlobalISel] Support G_SELECT [1/10]
- In progress
* Misc [2/10]
- Mailing lists, code reviews
- TCWG-1136 - LLVM 4.0.1 - Spun up and uploaded the final release candidate
- TCWG-1177 - Investigate failure on clang-cmake-aarch64-lld -
Bisected and reverted a commit upstream
== Plan ==
* More GlobalISel
* More buildbots
* More code reviews
